A HIGHLY RELIABLE AND RADIATION-HARDENED

10T SRAM CELL WITH PMOS ACCESS TRANSISTORS

A thesis
Submitted in partial fulfillment of the
requirements for the award of the Degree of

MASTER OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION

BY

AAKANSHA

(MT/EC/10006/18)

ELECTRONICS AND COMMUNICATION DEPARTMENT

BIRLA INSTITUTE OF TECHNOLOGY
MESRA-835215, RANCHI
 APPROVAL OF THE GUIDE

Recommended that the thesis entitled “A Highly Reliable and

Radiation-Hardened 10T SRAM cell with PMOS access
transistors ” presented by Miss. Aakansha under my supervision
and guidance be accepted as fulfilling this part of the requirements
for the award of Degree of Master of Technology. To the best of
my knowledge, the content of this thesis did not form a basis for
the award of any previous degree to anyone else.

X
Date: 16 June 2020 S ig n e d b y : A m in u l Is la m

Dr. Aminul Islam

Associate Professor
Dept. of ECE
Birla Institute of Technology
Mesra, Ranchi
 DECLARATION CERTIFICATE

I certify that
a) The work contained in the thesis is original and has been
done by myself under the general supervision of my
supervisor.
b) The work has not been submitted to any other Institute for any
other degree or diploma.
c) I have followed the guidelines provided by the Institute in
writing the thesis.
d) I have conformed to the norms and guidelines given in the
Ethical Code of Conduct of the Institute.
e) Whenever I have used materials (data, theoretical analysis,
and text) from other sources, I have given due credit to them
by citing them in the text of the thesis and giving their details in
the references.
f) Whenever I have quoted written materials from other sources,
I have put them under quotation marks and given due credit to
the sources by citing them and giving required details in the
references.

Aakansha
(MT/EC/10006/2018)
 CERTIFICATE OF APPROVAL

This is to certify that the work embodied in this thesis entitled “A

Highly Reliable and Radiation-Hardened 10T SRAM cell with
PMOS access transistors”, is carried out by Miss. Aakansha
(MT/EC/10006/18) has been approved for the degree of Master
of Technology in Electronics and Communication Engineering of
Birla Institute of Technology, Mesra, Ranchi.

Date:

Place:

Internal Examiner External Examiner

(Chairman)
Head of Department
 ABSTRACT
The major design metric for designing a basic SRAM cell include high value
of RSNM, low power consumption and higher reliability. Whereas a radiation
tolerant SRAM cell includes the design metric of soft error robustness. In
this paper, we have proposed a Quad-node 10 transistor (10T) SRAM cell
which has more soft error robustness than the Quatro 10T cell. The NMOS
access transistors of the Quatro 10T cell are replaced by the PMOS access
transistors in the proposed 10T cell. The benefit of using PMOS access
transistors is due to its high radiation tolerance. The leakage currents in
PMOS access transistors are not affected by the radiation bombardment.
Whereas they increase rapidly in NMOS transistors. In hold operation, both
the cells consume same amount of power as the access transistors are
cutoff. We also have smaller gate leakages in the case of PMOS access
transistors than NMOS access transistors. In the case of hold operation,
both the Quatro and proposed cells are able to recover 1→0 single event
transients (SET). For 0→1 single event transients (SET) in hold operation,
proposed cell shows an increment of 3µA in current margin. This improves
the hold failure probability of the proposed cell. The increment in current
margin is obtained by compromising the increment in the value of read
access time by 2.04%. Rest of the design matrices such as Read Static
Noise Margin (RSNM), Hold power, Write Static Noise Margin (WSNM) and
Cell Area remains same.

i
 ACKNOWLEDGEMENT

I would like to express my profound gratitude to my project guide, Dr.

Aminul Islam for his guidance and support during my thesis work. I
benefited greatly by working under his guidance. It was his effort for which I
am able to develop a detailed insight on this subject and special interest to
study further. His encouragement motivation and support has been
invaluable throughout my studies at BIT, Mesra, Ranchi.
I convey my sincere gratitude to Dr. S. Pal, Head, Dept. of ECE, BIT, Mesra,
Ranchi, for providing me various facilities needed to complete my project
work. I would also like to thank all the faculty members of ECE department
who have directly or indirectly helped during the course of the study. I would
also like to thank all the staff (technical and non-technical) and my friends at
BIT, Mesra, Ranchi who have helped me greatly during the course.
Finally, I must express my very profound gratitude to my parents for providing
me with unfailing support and continuous encouragement throughout the
years of my study. This accomplishment would not have been possible
without them.
My apologies and heartful gratitude to all who have assisted me yet have not
been acknowledged by name.

Thank you.

DATE: AAKANSHA
(MT/EC/10006/18)

ii
CONTENTS
ABSTRACT i

ACKNOWLEDGMENT ii

LIST OF FIGURES v

LIST OF TABLES vii

1 RADIATION HARDENED CELL……………………………………………...1

1.1 INTRODUCTION……………………………………………………………………………1

1.2 MECHANISM OF RADIATION HARDENED CELL……………………………….…….2

1.3 FUNDAMENTALS OF SOFT ERRORS ………………………………...…………………3

1.4 MECHANISM OF SOFT ERRORS………………………...……………………………….3

1.5 SOURCES OF SOFT ERRORS……………………………………………………………...5

1.5.1 ALPHA PARTICLE…..………………………………………………………....…….5

1.5.2 NEUTRON.....................................................................................................................5

1.5.3 PROTON……………………………………………………………………………....6

1.5.4 HEAVY IONS…………………………………………………………………............6

1.6 LITERATURE REVIEW…………………………………………………………….………7

1.7 MOTIVATION……………………………………………………………………….......….10

1.8 OBJECTIVE……………………………………………………….…………………….…..11

1.9 THESIS ORGANIZATION………………………………………………….………………11

2 RADIATION ENVIRONMENT………………………………………………..12
2.1 INTRODUCTION………………………………………………………….……………..….12

2.2.1 THE SPACE ENVIRONMENT………………………………….…………………12

2.2.2 THE GROUND LEVEL………………………………………….………………....14

2.2.3 THE NUCLEAR REACTOR ENVIRONMENT………………….………………..14

2.2.4 THE RADIATION PROCESSING ENVIRONMENT ………………………….…15

2.2.5 THE WEAPONS ENVIRONMENT ……………..……………...............................16

2.2.6 HIGH-ENERGY PHYSICS ACCELERATORS………………….………………..17

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3 RADIATION HARDENED BY DESIGN (RHBD)……………………….……..18
3.1 INTRODUCTION…………………………………………………………………..……....…18

3.2 CURRENT RHBD APPROACHES ……………………………..…………..……………….18

3.3 RHBD SRAM BITCELLS ……………………………………………..…..……...………….19

3.4 SINGLE-EVENT EFFECTS ……………………………………………………..….………..19

3.5 SOFT UPSETS ……………………………………………………………….......…………...19

3.6 SINGLE-EVENT UPSET………………………………………...…………..……………….19`

3.7 SINGLE-EVENT FUNCTIONAL INTERRUPT…………………………..………………....20

3.8 MULTIPLE-BIT UPSET…………………….................................................................……..20

3.9 HARD UPSETS………………………………….………………………………….………...21

3.10 SINGLE-EVENT LATCH-UP……………………………………………………….……….21

3.11 SINGLE HARD ERROR……………………………………………..………….……...…….21

3.12 SINGLE-EVENT GATE RUPTURE…………………………………………….…...………22

3.13 SINGLE-EVENT BURN OUT…………………………………………………….………….22

3.14 SUMMARY……………………………………………………………………….……..……22

4 EXISTING SRAM BITCELL DESIGNS………………………………………..23

4.1 INTRODUCTION…………………………………………………………………………...…23

4.2 6T SRAM BITCELL ………………………………………………….……………………….23

4.3 DUAL INTERLOCK STORAGE CELL…………………………………………...………….25

4.4 QUATRO 10T SRAM CELL…………………………………………………………………..27

5 PROPOSED CELL, OPERATIONS AND RESULT………….………………..30

5.1 INTRODUCTION………………………………………………………………….………......30

5.2 PRIOR WORK ………………………………………………..……….…………….………...31

5.3 PROPOSED 10T SRAM CELL ……………………………………………..………………...33

5.4 CELL SIZING …………………………………..……………….…………………………….34

5.5 OPERATIONS OF THE PROPOSED 10T CELL ……………………………….………...….36

5.5.1. READ ACCESS TIME (TRA)………………………………………………………….36

5.5.2. HOLD POWER………………………………………………………………………....37

5.5.3. READ STATIC NOISE MARGIN (RSNM)……….…………………………………..39

5.5.4. WRITE STATIC NOISE MARGIN (WSNM)………………………………………....41

5.5.5. SOFT ERROR ROBUSTNESS…………………………………………………….......42

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6 CONCLUSION AND FUTURE SCOPE OF WORK………………....….………..49
6.1 CONCLUSION…………………………………………………...………………..………...…49

6.2 FUTURE SCOPE OF THIS WORK …………………………………..……………………….49

APPENDIX A: ACCEPTED PAPER……………………………………………….50

REFERENCES………………………………………………………………………..51

LIST OF FIGURES
Figure 1.1 Charge generation and collection in a PN junction 4
Figure 4.1 (a) Schematic of traditional 6T SRAM bitcell (b) 6T bitcell composed 24
of two back to-back inverters and two access transistors A1, A2
Figure 4.2 Schematic of DICE bitcell 25
Figure 4.3.1 Recovery waveform of logic when X2 is flipped from 1 to 0 26
Figure 4.3.2 Recovery waveform of logic when X1 is flipped from 0 to 1 27
Figure 4.4 Schematic of Quatro-10T bitcell 28
Figure 4.4.1 Quatro cell recover when Node A is flipped from 1 to 0 28
Figure 4.4.2 Quatro cell is upset because Node A is flipped from 0 to 1 29
Figure 5.1 Schematic of Quatro-10T SRAM cell 31
Figure 5.2 Schematic of proposed 10T SRAM cell with PMOS access 33
transistors
Figure 5.3 Cell Sizing of the Quatro 10T SRAM cell (all the W/L 34
dimensions of the MOSFETs are in nanometers)
Figure 5.4 Cell Sizing of the proposed 10T SRAM cell (all the W/L 34
dimensions of the MOSFETs are in nanometers)
Figure 5.5 TRA of Quatro 10T cell and proposed 10T cell at various VDD 37

v
Figure 5.6 Comparison of TRA distribution plots for Quatro-10T and 37
Proposed 10T SRAM cells with sample size of 5000 while
performing Monte Carlo simulation
Figure 5.7 Hold Power of Quatro 10T cell and proposed 10T cell at 38
various VDD
Figure 5.8 Quatro 10T cell with DC noise inserted at storage nodes A and 39
B
Figure 5.9 Proposed 10T cell with DC noise inserted at storage nodes A 39
and B
Figure 5.10 RSNM butterfly curves for Quatro 10T and proposed cell 40
Figure 5.11 WSNM graph of Quatro and proposed 10T cell 41
Figure 5.12 Simulation showing recovery of the Quatro-10T cell for an 42
injected exponential current mimicking (pulse width of 50 ns
and peak voltage selected based on current margin) a 1 to 0 at
nodes A and B (for all values of current)
Figure 5.13 Simulation showing recovery of the Quatro-10T cell for an 43
injected exponential current mimicking (pulse width of 50 ns
and peak voltage selected based on current margin) 1 to 0 at
nodes C and D (for all values of current)
Figure 5.14 Simulation showing recovery of the proposed-10T cell for an 43
injected exponential current mimicking (pulse width of 50 ns
and peak voltage selected based on current margin) 1 to 0 at
nodes A and B (for all values of current)
Figure 5.15 Simulation showing recovery of the proposed-10T cell for an 44
injected exponential current mimicking (pulse width of 50 ns
and peak voltage selected based on current margin) 1 to 0 at
nodes C and D (for all values of current)
Figure 5.16 Simulation showing recovery of the Quatro-10T cell for an 44
injected exponential current mimicking (pulse width of 50 ns
and peak voltage of 229 µA) 0 to 1 at nodes A and B
Figure 5.17 Simulation showing recovery of the Quatro-10T cell for an 45
injected exponential current mimicking (pulse width of 50 ns

vi
 and peak voltage of 229 µA) 0 to 1 at nodes C and D
Figure 5.18 Simulation showing non-recovery of the Quatro-10T cell for an 45
injected exponential current mimicking (pulse width of 50 ns
and peak voltage of 230 µA) 0 to 1 at nodes A and B
Figure 5.19 Simulation showing non-recovery of the Quatro-10T cell for an 46
injected exponential current mimicking (pulse width of 50 ns
and peak voltage of 230 µA) 0 to 1 at nodes C and D
Figure 5.20 Simulation showing recovery of the proposed-10T cell for an 46
injected exponential current mimicking (pulse width of 50 ns
and peak voltage of 232 µA) 0 to 1 at nodes A and B

Simulation showing recovery of the proposed-10T cell for an

Figure 5.21 47
injected exponential current mimicking (pulse width of 50 ns
and peak voltage of 232 µA) 0 to 1 at nodes C and D.
Figure 5.22 Simulation showing non-recovery of the proposed-10T cell for 47
an exponential injected current mimicking (pulse width of 50
ns and peak voltage of 233 µA) 0 to 1 at nodes A and B
Figure 5.23 Simulation showing non-recovery of the proposed-10T cell for 48
an injected exponential current mimicking (pulse width of 50
ns and peak voltage of 233 µA) 0 to 1 at nodes C and D
Figure 5.24 Enlarged version of the injected exponential current spike at 48
node A for proposed cell (pulse width = 50 ns)

LIST OF TABLES
Table 5.1 Comparison of TRA values for different VDD 36
Table 5.2 Comparison of Hold Power values for different VDD 38

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CHAPTER 1

RADIATION HARDENED CELL

1.1 INTRODUCTION
Excessive demand of Electronic gadgets has led to a new revolution in the field
of VLSI technology. These devices are replacing the basic amenities of human
life and therefore need to be upgraded for various improvements with the
passage of time. Application of VLSI technology is widely spread to various
electronic devices from a simple mobile to smart phones, GPS positioning
systems, defense and military operations, global communication systems,
radars, satellites, medical services and is still not limited. Most of the
applications in VLSI possess memories as their integral part to perform various
functions and to store the data wherever it is required. Memories play a vital
role in making the system intelligent. There are numerous categories of
memory to be used in various operations and may possess permanent storage or
temporary storage with static or dynamic operations.

Static Random Access Memory (SRAM) is a type of volatile memory, which

means it can only store data when its power supply is turned on. When the
power is turned off, the data will be lost. The users can read any data given the
address of the data, or the users can write data to a specific address. It is an
important component of integrated circuits and Systems on Chip (SoC). It
occupies a large portion of the total-die area and it is also predicted that nearly
94% of the total die area would be occupied by onchip cache memory in near
future nano-scale technologies. It’s faster read and write speed compared to
other type of memories makes it desirable in many speed contingent
applications. They are widely used for register files and memory caches. They
are composed of a memory bitcell array, address decoders (column and row
decoders), multiplexers, sense amplifiers, write drivers and pre-charged
circuits. However, there are drawbacks of SRAM, with one being the large area
penalty and another being the susceptibility to radiation damage.

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