COMBINATIONAL CIRCUIT

PART 2
MULTIPLEXER
• combinational circuit that selects binary information from
one of many input lines and directs it to a single output
line.
• The selection of a particular input line is controlled by a
set of select lines. Normally, there are 2𝑛 input lines and n
select lines whose bit combinations determine which input
is selected.
• It is also known as data selector, universal logic module
and Boolean generator.
2-TO-1 LINE MULTIPLEXER

I0
2x1
MUX Y Output
I1

S Y
0 I0
Block Diagram 1 I1

Function Table
2-TO-1 LINE MULTIPLEXER
I0

Y
I1

S Y
0 I0
1 I1
S Function Table
4-TO-1 LINE MULTIPLEXER

I0
I1 4x1
MUX Y Output
I2
I3
S1 S0

S1 S0 Y
0 0 I0
0 1 I1
Block Diagram 1 0 I2
1 1 I3

Function Table
 4-TO-1 LINE MULTIPLEXER
I0

I1

Y
I2

I3

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
S1 Function Table

S0
A1
Y1

A2
Y2

A3
Y3

A4
Y4

B1

B2

B3

E S Output Y
B4
1 X All 0’s
0 0 Select A
0 1 Select B

S Function Table
QUADRUPLE 2-to-1 line multiplexer
E
 (a) Express the function in SOP form and
derive its truth table.
(b) Assign one of the n variables of the
Boolean function to be the data input variable
BOOLEAN of the multiplexer. Assign the other (n-1)
FUNCTION variables to be the select line input variables.
IMPLEMENTATION (c) Determine the implementation table. List the
USING
inputs of the multiplexer in columns (I0 , I1 , I2 ,
MULTIPLEXER
I3…) and under them list all minterms in 2
rows. The 1st row is the list of all minterms with
data input variable complemented. The 2nd
row is the list of all minterms with data input
variable uncomplemented.
(d) Circle all minterms that gives a logic-1 output.

(e) Inspect each column separately.

• If the 2 minterms in a column are not circled, apply 0 to the
corresponding multiplexer input.
• If the 2 minterms in a column are circled, apply 1 to the corresponding
multiplexer input.
• If the bottom minterm is circled and the top minterm is not circled, connect
the uncomplemented data variable to the corresponding multiplexer
input.
• If the top minterm is circled and the bottom minterm is not circled, connect
the complemented data variable to the corresponding multiplexer input.

(f) The output variable of the function is the multiplexer's output, Y.

EXAMPLE1
inputs output
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
EXAMPLE1
Implementing F(A,B,C) = m(1,3,5,6)
with a multiplexer

Implementation table
I0 I1 I2 I3
A’
A
EXAMPLE1
Implementing F(A,B,C) = m(1,3,5,6)
with a multiplexer

0 I0

1 I1 4x1
MUX Y Output
A I2
A’ I3
S1 S0

Block Diagram
 EXAMPLE1
Implementing F(A,B,C) = m(1,3,5,6)
with a multiplexer
Implementation table
I0 I1 I2 I3
B’
B

I0 I1 I2 I3
C’
C
EXAMPLE1
Implementing F(A,B,C) = m(1,3,5,6)
with a multiplexer

I0
I1 4x1
MUX Y Output
I2
I3
S1 S0

Block Diagram
 I0 I1 I2 I3 I0 I1 I2 I3
A’ A’
A A
EXAMPLE 2
I0

I1
I2
I3 8x1
Y Output
MUX
I4

I5

I6
I7

S2 S1 S0

Block Diagram
EXAMPLE 2
Implementing F(A,B,C,D) = m(0,1,3,4,8,9,15)
with a multiplexer

Implementation table
I0 I1 I2 I3 I4 I5 I6 I7
DEMULTIPLEXER
• A circuit that receives information on a single line and
transmits this information to one of 2n possible output lines

D0

1x 4 D1
E DEMUX outputs
D2
input
D3

A B
SELECT LINES

Block Diagram
 EXAMPLE
• Consider an active-high 1 x 4 demultiplexer,
Block diagram: Truth table: Logic Diagram:
I S1 S0 D0 D1 D2 D3
0 X X 0 0 0 0
D0
1 0 0 1 0 0 0
Data 1x4 D1
I 1 0 1 0 1 0 0
input demux D2
D3 1 1 0 0 0 1 0
21 20
1 1 1 0 0 0 1

S1 S0
Output Boolean functions:
D0 = I S1’ S0’
D1 = I S1’ S0
D2 = I S1 S0’
D3 = I S1S0
PROGRAMMABLE LOGIC
DEVICES
 PROGRAMMABLE LOGIC DEVICE
(PLDS)
• Programmable logic devices (PLDs) are used in many applications to
replace SSI and MSI circuits; they save space and reduce the actual
number and cost of devices in a given design.

• A PLD consists of a large array of AND gates and OR gates that can
be programmed to achieve specified logic functions.
 PROGRAMMABLE ARRAYS

• All PLDs consists of programmable arrays.

• A programmable array is essentially a grid of conductors to form rows
and columns with a fusible link at each cross point. Arrays can be
either fixed or programmable.
• Programmable Logic Array (PLA)
x 1 x2 xn
• Use to implement
circuits in SOP form
Input buffers
and
• The connections in inverters
the AND plane are
x1 x1 xn xn
programmable

P1
• The connections in
the OR plane are AND plane OR plane
Pk
programmable

f1 fm
 CLASSIFICATIONS OF
PROGRAMMABLE LOGIC DEVICES
• Programmable logic devices are classified according to their architecture, which
is basically the internal functional arrangement of the elements that give a
device its particular operating characteristic. The different types of PLDs re:
(A) Programmable Read-Only Memory (PROM)
(B) Programmable Logic Array (PLA)
(C) Programmable Array Logic (PAL)
(D) Generic Array logic (GAL)
 PROGRAMMABLE READ-ONLY
MEMORY (PROM)
• PROM is consists of a set of fixed (non-programmable) AND
gates
connected as a decoder and a programmable OR array.
• The generalized block diagram of a PROM is shown below.

Input 1 Output 1 This type of PLD is used

primarily as an
:
Input 2
Fixed :
Output 2 addressable memory and
Programmable
: AND Array :
OR Array not as a logic device
:
: because of limitations
Input n :
Output m imposed by the fixed
AND gates.
READ ONLY MEMORY
(ROM)
 READ ONLY MEMORY (ROM)
• It contains permanently or semi permanently stored data, which can be read from the
memory but either cannot be changed at all or cannot be changed without specialized
equipment.
• It stores data that are used repeatedly in system applications such as tables, conversions,
or programmed instructions for system initialization and operation.
• It is a device that includes both decoder and OR gates in a single IC package. The decoder is
a minterm generator and OR gates can be used to sum the minterms of Boolean functions.
• ROM comes with special internal fuses that can be programmed for a specific
configuration. Once the pattern is established, it stays within the unit even the power if
turned off and on again. This is why ROM is also known as non-volatile memory.
 ROM TYPES

ROM

MASK FLASH
PROM EPROM EEPROM
ROM ROM
 ROM BLOCK DIAGRAM

n 2n xm m
inputs ROM outputs

• Each combination of the n inputs lines is called an address. The

number of distinct addresses possible with n inputs lines is 2n.
• Each bit combination that comes out of the output lines is called a word. The
number of bits per word is equal to the number of output lines, m.
• An output word can be selected by a unique address, and since
there are 2n distinct addresses, there are 2n distinct words.
 EXAMPLE

• Consider a 8 x 4 ROM as illustrated below,

Logic Diagram:
Block diagram:
 BOOLEAN FUNCTION
IMPLEMENTATION USING ROM
• (a) Express the function in sum of minterm form.
• (b) Break the links of those minterms not included in the function, each
ROM output can be made to represent the Boolean function of one of
the output variables in the combinational circuit. This blowing of fuse
is also referred to as “programming” the ROM.
 EXAMPLE
• Implement a combinational circuit described by the following

• Boolean functions: Logic Diagram:

F1(A1,A0) = Σ(1,2,3)
F2(A1,A0) = Σ(0,2)
 EXAMPLE
• Design a combinational circuit using a 8 x 4 ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of the
input number.

Block Diagran
Truth Table:
 Logic Diagram
ROM Truth Table:

OR
PROGRAMMABLE LOGIC
ARRAY(PLA)
 PROGRAMMABLE LOGIC ARRAY

• The PLA consists of a programmable AND array and a programmable

OR array.

• The main feature of PLA lies in the fact that not all addresses are
decoded. The AND array does not produce all the minterms as in the
ROM, thus programmable.

• PLA can be used to implement combinational circuit with don’t care

conditions unlike ROM.
• The block diagram of a PLA is shown below.
 BOOLEAN FUNCTION
IMPLEMENTATION USING PLA
a. Determine the simplified Boolean functions (both its true form and
complemented form) in SOP form using previously discussedBoolean function
simplification techniques.
b. Get distinct product terms (choose from either the uncomplemented or
complemented output functions).
c. Construct a PLA program table.
d. Program the PLA circuit.
 EXAMPLE

A combinational circuit is defined by the functions:

F1 (ABC)= (3,5,6,7)
F2 (ABC)= (0,2,4,7)
Implement the output functions F1 and F2 with a PLA having three
inputs, four product terms, and two outputs.
 SOLUTION
a) Determine the simplified Boolean functions (both its true form and complemented form)
in SOP form
B) GET DISTINCT PRODUCT TERMS (CHOOSE FROM EITHER THE UNCOMPLEMENTED OR
COMPLEMENTED OUTPUT FUNCTIONS).
 D) PROGRAM THE PLA CIRCUIT.

c) Construct a PLA program table.

 EXAMPLE 2

A combinational circuit is defined by the functions:

F1 (ABCD)= (1,3,5,6,9,11,12,13,14)
F2 (ABCD)= (1,3,4,5,8,9,11,12,13,14,15)
Implement the output functions F1 and F2 with a PLA. Show the PLA
program table
SOLUTION
 PROGRAMMABLE ARRAY LOGIC
(PAL)
• The PAL consists of a programmable AND array and a fixed OR array with
the output logic.
• Because only the AND gates are programmable, the PAL is easier to program, but
is not as flexible as the PLA.
• The PAL is the most-common one-time programmable logic device andis implemented
with bipolar technology (TTL or ECL).
Input 1 Output 1

Input 2 : Output 2
Programmable Fixed OR Array
: and Output Logic
: AND Array
:
:
:
Input n : Output m
 BOOLEAN FUNCTION
IMPLEMENTATION USING PAL
a. Simplify the function(s) in SOP form using previously discussed
Boolean function simplification techniques.
b. Construct a PAL program table.
c. Program the PAL circuit.
 EXAMPLE
A combinational circuit is defined by the functions:
w (ABCD)= (2,12,13)
x (ABCD)= (7,8,9,10,11,12,13,14,15)
y (ABCD)= (0,2,3,4,5,6,7,8,10,11,15)
z (ABCD)= (1,2,8,12,13)

Implement the circuit using PAL with 12 programmable AND gate and 4 fixed OR gate. Show the PAL
program table.
 SOLUTION
a. Simplify the function(s) in SOP form using previously discussedBoolean
function simplification techniques.
 C. PROGRAM THE PAL CIRCUIT.

b. Construct a PAL program table.

MULTIPLEXERS:
EXERCISES
a. DIRECT METHOD
1. Implement the following Boolean expressions using MUX
a. F(x, y, z) = (0, 1 , 5, 7)
b. F(x, y, z) = Π(1, 2 , 3, 6, 7)
c. F(w, x, y, z) = (2, 3 ,12, 13, 14, 15)
d. F(A, B, C, D) = Π ( 3 ,7, 11, 13, 14, 15)
b. FOLDING METHOD
1. Implement the following Boolean expression using MUXs.
a. F(w, x, y, z) = (1, 4 ,5, 6, 12, 14, 15) using w as input variable
b. F(A, B, C, D) =  ( 0 ,1, 2, 4, 5, 7, 11, 15) using B as input variable
c. F(w, x, y, z) = (2, 3 ,10, 11, 12,13, 14, 15) using y as input variable
d. F(A, B, C, D) =  ( 0 ,2, 4, 5, 6, 7, 8, 10, 13, 15) using D as input variable
e. F(w, x, y, z) = Π (0, 2 ,4, 5, 6, 7, 8, 10)
i. using w as input variable
ii. using x as input variable
iii. using y as input variable
iv. using z as inputvariable
PLA
1. A combinational circuit is defined by the functions:
F1 (A, B, C) = (3, 5 ,6, 7)
F2 (A, B, C) =  (0, 2 ,4, 7)
2. Derive the PLA programming table for the combinational circuit that
squares a 3-bit number. Minimize the number of product terms.
3. Tabulate the PLA program table and construct the PLA circuit for the
following Boolean functions.
1. F1(x, y, z) = (0, 1 , 5, 7)
F2(x, y, z) = (1, 2 , 3, 6, 7)
F3(x, y, z) = (3, 5, 7)
2. F1(x, y, z) = (3, 6, 7)
F2(x, y, z) = Π(1, 2 ,4, 6, 7)
F3(x, y, z) = Π (0, 5, 6, 7)
ROM
a. Implement the following Boolean functions using ROM.
1. F1(x, y, z) = (0, 1 , 5, 7)
F2(x, y, z) = (1, 2 , 3, 6, 7)
F3(x, y, z) = (3, 5, 7)

2. F1(x, y, z) = (3, 6, 7)
F2(x, y, z) = Π(1, 2 ,4, 6, 7)
F3(x, y, z) = Π (0, 5, 6, 7)

3. F1(A, B, C, D) = Π ( 1 ,4, 5, 6, 12, 14, 15)

F2(A, B, C, D) =  (2 ,3, 10, 11, 12, 13, 14, 15)
F3(A, B, C, D) =  (0, 2 ,4, 5, 6, 7, 8, 10, 13, 15)
F4(A, B, C, D) = Π (0, 1, 2,4, 5, 7, 11, 15)