www.agelectronica.com www.agelectronica.

com

ADC1001 10-Bit µP Compatible A/D Converter

June 1999

ADC1001
10-Bit µP Compatible A/D Converter
General Description Features
The ADC1001 is a CMOS, 10-bit successive approximation n ADC1001 is pin compatible with ADC0801 series 8-bit
A/D converter. The 20-pin ADC1001 is pin compatible with A/D converters
the ADC0801 8-bit A/D family. The 10-bit data word is read in n Compatible with NSC800 and 8080 µP derivatives — no
two 8-bit bytes, formatted left justified and high byte first. The interfacing logic needed
six least significant bits of the second byte are set to zero, as n Easily interfaced to 6800 µP derivatives
is proper for a 16-bit word. n Differential analog voltage inputs
Differential inputs provide low frequency input common n Logic inputs and outputs meet both MOS and TTL
mode rejection and allow offsetting the analog range of the voltage level specifications
converter. In addition, the reference input can be adjusted n Works with 2.5V (LM336) voltage reference
enabling the conversion of reduced analog ranges with n On-chip clock generator
10-bit resolution.
n 0V to 5V analog input voltage range with single 5V
supply
Key Specifications n Operates ratiometrically or with 5 VDC, 2.5 VDC, or
n Resolution 10 bits analog span adjusted voltage reference
n Linearity error ± 1 LSB n 0.3" standard width 20-pin DIP package
n Conversion time 200µS

Connection Diagram
ADC1001
Dual-In-Line Package

DS005675-11

Top View

Ordering Information
Temperature 0˚C to +70˚C −40˚C to +85˚C
Range
Order Number ADC1001CCJ-1 ADC1001CCJ
Package Outline J20A J20A

TRI-STATE ® is a registered trademark of National Semiconductor Corp.

© 1999 National Semiconductor Corporation DS005675 www.national.com

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

Absolute Maximum Ratings (Notes 1, 2) Lead Temp. (Soldering, 10 seconds) 300˚C

If Military/Aerospace specified devices are required, ESD Susceptibility (Note 10) 800V
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications. Operating Conditions (Notes 1, 2)
Supply Voltage (VCC) (Note 3) 6.5V Temperature Range TMIN ≤TA≤TMAX
Logic Control Inputs −0.3V to +18V ADC1001CCJ −40˚C≤TA≤+85˚C
Voltage at Other Inputs and Outputs −0.3V to (VCC+0.3V) ADC1001CCJ-1 0˚C≤TA≤+70˚C
Storage Temperature Range −65˚C to +150˚C Range of VCC 4.5 VDC to 6.3 VDC
Package Dissipation at TA = 25˚C 875 mW

Converter Characteristics
Converter Specifications: VCC = 5 VDC, VREF/2 = 2.500 VDC, TMIN≤TA≤TMAX and fCLK = 410 kHz unless otherwise specified.
Parameter Conditions MIn Typ Max Units
Linearity Error ±1 LSB
Zero Error ±2 LSB
Full-Scale Error ±2 LSB
Total Ladder Resistance (Note 9) Input Resistance at Pin 9 2.2 4.8 KΩ
Analog Input Voltage Range (Note 4) V(+) or V(−) GND−0.05 VCC+0.05 VDC
DC Common-Mode Error Over Analog Input Voltage Range ± 1⁄8 LSB
Power Supply Sensitivity VCC = 5 VDC ± 5% Over ± 1⁄8 LSB
Allowed VIN(+) and VIN(−)
Voltage Range (Note 4)

AC Electrical Characteristics
Timing Specifications: VCC = 5 VDCand TA = 25˚C unless otherwise specified.
Symbol Parameter Conditions MIn Typ Max Units
Tc Conversion Time (Note 5) 80 90 1/fCLK
fCLK = 410 kHz 195 220 µs
fCLK Clock Frequency (Note 8) 100 1260 kHz
Clock Duty Cycle 40 60 %
CR Conversion Rate In Free-Running INTR tied to WR with 4600 conv/s
Mode CS = 0 VDC, fCLK = 410 kHz
tW(WR)L Width of WR Input (Start Pulse CS = 0 VDC (Note 6) 150 ns
Width)
tACC Access Time (Delay from CL = 100 pF 170 300 ns
Falling Edge of RD to Output
Data Valid)
t1H, t0H TRI-STATE ® Control (Delay CL = 10 pF, RL = 10k 125 200 ns
from Rising Edge of RD to (See TRI-STATE Test
Hi-Z State) Circuits)
tWI, tRI Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR
t1rs INTR to 1st Read Set-Up Time 550 400 ns
CIN Input Capacitance of Logic 5 7.5 pF
Control Inputs
COUT TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)

www.national.com 2

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

DC Electrical Characteristics
The following specifications apply for VCC = 5 VDC and TMIN≤TA≤ TMAX, unless otherwise specified.
Symbol Parameter Conditions MIn Typ Max Units
CONTROL INPUTS [Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1) Logical “1” Input Voltage VCC = 5.25 VDC 2.0 15 VDC
(Except CLK IN)
VIN (0) Logical “0” Input Voltage VCC = 4.75 VDC 0.8 VDC
(Except CLK IN)
IIN (1) Logical “1” Input Current VIN = 5 VDC 0.005 1 µADC
(All Inputs)
IIN (0) Logical “0” input Current VIN = 0 VDC −1 −0.005 µADC
(All Inputs)
CLOCK IN
VT+ CLK IN Positive Going 2.7 3.1 3.5 VDC
Threshold Voltage
VT− CLK IN Negative Going 1.5 1.8 2.1 VDC
Threshold Voltage
VH CLK IN Hysteresis 0.6 1.3 2.0 VDC
(VT+)−(VT−)
OUTPUTS AND INTR
VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VCC = 4.75 VDC 0.4 VDC
VOUT(1) Logical “1” Output Voltage IO = −360 µA, VCC = 4.75 VDC 2.4 VDC
IO = −10 µA, VCC = 4.75 VDC 4.5 VDC
IOUT TRI-STATE Disabled Output VOUT = 0.4 VDC 0.1 −100 µADC
Leakage (All Data Buffers) VOUT = 5 VDC 0.1 3 µADC
ISOURCE VOUT Short to GND, TA = 25˚C 4.5 6 mADC
ISINK VOUT Short to VCC, TA = 25˚C 9.0 16 mADC
POWER SUPPLY
ICC Supply Current (Includes fCLK = 410 kHz,
Ladder Current) VREF/2 = NC, TA = 25˚C
and CS = 1 2.5 5.0 mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(−)≥ VIN(+) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec al-
lows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will
be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial
tolerance and loading.
Note 5: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 3 .
Note 6: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
Note 7: All typical values are for TA = 25˚C.
Note 8: Accuracy is guaranteed at fCLK = 410 kHz. At higher clock frequencies accuracy can degrade.
Note 9: The VREF/2 pin is the center point of a two resistor divider (each resistor is 2.4kΩ) connected from VCC to ground. Total ladder input resistance is the sum
of these two equal resistors.
Note 10: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

3 www.national.com

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

Typical Performance Characteristics

Logic Input Threshold Delay From Falling Edge of CLK IN Schmitt Trip Levels
Voltage vs Supply Voltage RD to Output Data Valid vs Supply Voltage
vs Load Capacitance

DS005675-14
DS005675-16
DS005675-15

Output Current vs
Temperature

DS005675-17

TRI-STATE Test Circuits and Waveforms

t1H, CL = 10 pF

DS005675-3 DS005675-4

tr = 20 ns

t0H, CL = 10 pF

DS005675-6

DS005675-5
tr = 20 ns

www.national.com 4

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

TRI-STATE Test Circuits and Waveforms (Continued)

Timing Diagrams

DS005675-7

Output Enable and Reset INTR

DS005675-8

*All timing is measured from the 50% voltage points.

5 www.national.com

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

Timing Diagrams (Continued)

Byte Sequencing For The 20-Pin ADC1001

Byte 8-Bit Data Bus Connection
Order DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB
1st Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
LSB
2nd Bit 1 Bit 0 0 0 0 0 0 0

Functional Description
The ADC1001 uses an advanced potentiometric resistive because the SET input can control the Q output of the INTR
ladder network. The analog inputs, as well as the taps of this F/F even though the RESET input is constantly at a “1” level.
ladder network, are switched into a weighted capacitor array. This INTR output will therefore stay low for the duration of
The output of this capacitor array is the input to a sampled the SET signal.
data comparator. This comparator allows the successive ap- When data is to be read, the combination of both CS and RD
proximation logic to match the analog difference input volt- being low will cause the INTR F/F to be reset and the
age [VIN(+)−VIN(−)] to taps on the R network. The most sig- TRI-STATE output latches will be enabled.
nificant bit is tested first and after 10 comparisons (80 clock
cycles) a digital 10-bit binary code (all “1”s = full-scale) is Zero and Full-Scale Adjustment
transferred to an output latch and then an interrupt is as-
Zero error can be adjusted as shown in Figure 1. VIN(+) is
serted (INTR makes a high-to-low transition). The device
forced to +2.5 mV (+1⁄2 LSB) and the potentiometer is ad-
may be operated in the free-running mode by connecting justed until the digital output code changes from 00 0000
INTR to the WR input with CS = 0. To ensure start-up under 0000 to 00 0000 0001.
all possible conditions, an external WR pulse is required dur-
ing the first power-up cycle. A conversion in process can be Full-scale is adjusted as shown in Figure 2, with the VREF/2
interrupted by issuing a second start command. input. With VIN (+) forced to the desired full-scale voltage
less 11⁄2 LSBs (VFS−11⁄2 LSBs), VREF/2 is adjusted until the
On the high-to-low transition of the WR input the internal digital output code changes from 11 1111 1110 to 11 1111
SAR latches and the shift register stages are reset. As long 1111.
as the CS input and WR input remain low, the A/D will remain
in a reset state. Conversion will start from 1 to 8 clock peri-
ods after at least one of these inputs makes a low-to-high
transition.
A functional diagram of the A/D converter is shown in Figure
3. All of the inputs and outputs are shown and the major logic
control paths are drawn in heavier weight lines.
The conversion is initialized by taking CS and WR simulta-
neously low. This sets the start flip-flop (F/F) and the result-
ing “1” level resets the 8-bit shift register, resets the Interrupt
(INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the
input end of the 10-bit shift register. Internal clock signals
then transfer this “1” to the Q output of F/F1. The AND gate,
G1, combines this “1” output with a clock signal to provide a
reset signal to the start F/F. If the set signal is no longer
present (either WR or CS is a “1”) the start F/F is reset and
the 10-bit shift register then can have the “1” clocked in,
which allows the conversion process to continue. If the set
signal were to still be present, this reset pulse would have no
effect and the 10-bit shift register would continue to be held
in the reset mode. This logic therefore allows for wide CS
and WR signals and the converter will start after at least one
of these signals returns high and the internal clocks again
provide a reset signal for the start F/F.
After the “1” is clocked through the 10-bit shift register (which
completes the SAR search) it causes the new digital word to
transfer to the TRI-STATE output latches. When this XFER
signal makes a high-to-low transition the one shot fires, set-
ting the INTR F/F. An inverting buffer then supplies the INTR
output signal.
Note that this SET control of the INTR F/F remains low for
aproximately 400 ns. If the data output is continuously en-
abled (CS and RD both held low), the INTR output will still
signal the end of the conversion (by a high-to-low transition),

www.national.com 6

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

Functional Description (Continued)

DS005675-9 DS005675-10

Note 11: VIN(−) should be biased so that VIN(−)≥ −0.05V when potentiom- FIGURE 2. Full-Scale Adjust
eter wiper is set at most negative voltage position.
FIGURE 1. Zero Adjust Circuit

Typical Application

DS005675-1

7 www.national.com

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

Block Diagram

DS005675-13

Note 12: CS shown twice for clarity.

Note 13: SAR = Successive Approximation Register.
FIGURE 3.

www.national.com 8

www.agelectronica.com www.agelectronica.com
www.agelectronica.com www.agelectronica.com

ADC1001 10-Bit µP Compatible A/D Converter

Physical Dimensions inches (millimeters) unless otherwise noted

Cavity Dual-In-Line Package (J) (Side Brazed)

Order Number ADC1001CCJ or ADC1001CCJ-1
NS Package Number J20A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Asia Pacific Customer Japan Ltd.
Americas Fax: +49 (0) 1 80-530 85 86 Response Group Tel: 81-3-5639-7560
Tel: 1-800-272-9959 Email: [email protected] Tel: 65-2544466 Fax: 81-3-5639-7507
Fax: 1-800-737-7018 Deutsch Tel: +49 (0) 1 80-530 85 85 Fax: 65-2504466
Email: [email protected] English Tel: +49 (0) 1 80-532 78 32 Email: [email protected]
Français Tel: +49 (0) 1 80-532 93 58
www.national.com Italiano Tel: +49 (0) 1 80-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

www.agelectronica.com www.agelectronica.com