DESIGN OF HIGH PERFORMANCE 1-BIT

HYBRID ADDER (VLSI)

A MINI PROJECT WORK

Submitted in partial fulfillment of the requirements for the award of the
degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
By
Likhitha Kacham 18H61A0428
Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

Under the Guidance of

Amrita Sajja
Assistant Professor
Department of ECE

Department of Electronics and Communication Engineering

ANURAG GROUP OF INSTITUTIONS
AUTONOMOUS
SCHOOL OF ENGINEERING
(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)
Venkatapur(V), Ghatkesar(M), Medchal-Malkajgiri Dist-500088
2021-2022
 ANURAG GROUP OF INSTITUTIONS
AUTONOMOUS
SCHOOL OF ENGINEERING
(Affiliated to Jawaharlal Nehru Technological University, Hyderabad
Venkatapur(V),Ghatkesar(M), Medchal-Malkajgiri Dist-500088
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the project report entitled Design of high performance 1-bit
Hybrid Adder (VLSI) being submitted by

Likhitha Kacham 18H61A0428

Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

in partial fulfillment for the award of the Degree of Bachelor of Technology in

Electronics & Communication Engineering to the Jawaharlal Nehru Technological
University, Hyderabad is a record of bonafide work carried out under my guidance
and supervision. The results embodied in this project report have not been submitted
to any other University or Institute for the award of any Degree or Diploma.

Amrita Sajja Dr.Sathees Kumaran

Assistant Professor Head of the Department
DEPT OF ECE

External Examiner
 ACKNOWLEDGEMENT

This project is an acknowledgement to the inspiration, drive and technical assistance

contributed by many individuals. This project would have never seen light of this day without the
help and guidance we have received. We would like to express our gratitude to all the people
behind the screen who helped us to transform an idea into a real application.

It’s our privilege and pleasure to express our profound sense of gratitude to Amrita Sajja,
Assistant Professor Department of ECE for her guidance throughout this dissertation work.

We express our sincere gratitude to Dr.S.Sathees Kumaran, Head of Department,

Electronics and Communication Engineering for his precious suggestions for the successful
completion of this project. He is also a great source of inspiration to our work.
We would like to express our deep sense of gratitude to G.Vishnu Murthy, Dean, School of
Engineering, for his tremendous support, encouragement and inspiration. Lastly, we thank
almighty, our parents, friends for their constant encouragement without which this assignment
would not be possible. We would like to thank all the other staff members, both teaching and
non- teaching, which have extended their timely help and eased our work.

BY
LIKHITHA KACHAM 18H61A0428
VASANTH MEKALA 18H61A0436
SRUJAN PATLOLLA 18H61A0444

i
 DECLARATION

We hereby declare that the result embodied in this project report entitled “Design of
high performance 1-bit Hybrid Adder(VLSI)” is carried out by us during the year
2021-2022 for the partial fulfillment of the award of Bachelor of Technology in
Electronics and Communication Engineering, from ANURAG GROUP OF
INSTITUTION. We have not submitted this project report to any other Universities /
Institute for the award of any degree.

BY

Likhitha Kacham 18H61A0428

Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

ii
 ABSTRACT

Technology evolution increased the demand for high performance and energy
efficient circuits.To meet the design criteria for the modern period, circuit designers
are often facing a dilemma to make trade-offs among area, delay and power
consumption.Along with number of devices used in the circuit should be less and
circuit should occupy less area, consume less power is the major challenge for the
designers.

Basic circuit used in most of the circuit designs is an ADDER. In digital addition,Full
Adder works as the most important elementary block.The improved version of the full
adder design brings overall improvement in the arithmetic units.

This project is an 18-transistor full adder cell based on the full swing hybrid
logic.Hybrid Adder is designed using metal oxide semiconductors(CMOS),Pass
Transistors,Transistor gates.This circuit is designed using Cadence tool with 90nm
technology.Further the proposed adder results of propagation delay is compared with
existing Adder circuits.

Major aim to design this circuit is to enhance the performance of the circuit by
decreasing its propagation delay.

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 TABLE OF CONTENTS

Pg.no
TITLE
Acknowledgement i
Declaration ii
Abstract iii
List of Figure iv
1. Introduction 1
1.1 Introduction 1
1.2 Aim of the project 2
2. Literature Survey 3
2.1 Base Paper 3
2.2 Introduction to VLSI Technology 5
2.3 CMOS Technology 6
2.4 Adders 7
2.5 Full Adder Classification 10
3. Hardware and Software requirements 11
3.1 Cadence tool 11
3.1.1 Introduction 11
3.1.2 Setting the environment for running 11
Cadence remotely for the circuit design
3.1.3 The Library Manager 13
3.1.4 Schematic Design and Simulation 14
3.1.5 Perform a DC Simulation 16
3.1.6 Parametric Simulation 16
3.1.7 Creating the symbol view for the 18
schematic view
4. Methodology 19
4.1 Hybrid Adder 19
4.2 Block Diagram of Full Adder 20
4.3 The Circuit Design 20
4.3.1 Modules 20
4.3.2 components used in the circuit 22
5. Results and Discussion 25
6. Conclusion and Future scope 32
7. References 33
LIST OF FIGURES:
NAME Pg.no
2.1 CMOS fabrication 6
2.2 Half Adder 7
2.3 Full Adder 8
2.5 Carry look Adder 9
2.6 Carry save Adder 10
3.1 Table-1 14
3.2 Analog design environment 16
3.3 Pin position 18
4.1 Block Diagram 20
4.2 Circuit Diagram 21
4.3 nmos and pmos Symbols 22
4.4 Voltage Symbol 22
4.5 Ground Symbol 23
5.1 Schematic Diagram 25
5.2 Netlist 26
5.3 Simulation 28
5.4 Propagation Delay 29
5.5 Comparison Table 30

iv
 CHAPTER 1

INTRODUCTION

1.1 Introduction:

With transistor scaling and technology evolution, the exploration of high-performance

and energy efficient circuits continues unabated.The search for energy and area
efficient circuits has been further enhanced due to the ubiquitous use of portable
devices.

To meet the design criteria of modern high-performance microprocessors, circuit

designers often fall in a dilemma to make trade-offs among area,delay and power
consumption.As a result,logic realization with the least number of devices and low
area with optimal delay and power has become a major challenge.

The addition operation plays the major role because several complex operations are
dependent on addition.In digital addition,full adder works as the most important
elementary building block.Despite having several existing full adder designs, the urge
for new designs continues to address the increasing throughput requirements.

Each circuit has its own specialization like; a circuit can increase the performance and
other can decrease the usage of area etc.A hybrid Adder which consists of different
elements which altogether works as an adder is preferred than initial adder circuit
design to make the adder reach the requirements.

1
1.2 AIM OF THE PROJECT:

This project is to design Hybrid Adder using pass transistors, complementary metal
oxide semi conductors(CMOS). This circuit is implemented using cadence software.
Cadence tool provides great platform to design the circuit and also to simulate the
circuit for the waveform. It also has the feature to calculate power, delay and other
parameters.

The circuit designed in this project used to increase the performance of the adder by
decreasing its delay. Also few parameters of the adder are compared with already
existing Hybrid Adders.

This circuit consists of 18 transistors with which the utilization of the area also
decreases.Thus, this circuit can be used in the bigger projects in which the adder
which have to be used should consist of lesser area consumption.

Also the major of the project is to design a high performance Hybrid Adder. This can
be achieved by decreasing the propagation delay in the circuit.The delay is decreased
because of aligning the transistors in parallel form and the circuit uses only eighteen
transistors to obtain Hybrid Adder.

2
 CHAPTER 2

LITERATURE SURVEY

2.1 BASE PAPER:

On the basis of output voltage, full adder circuits are classified into two categories:
Full swing and non full swing. Full swing circuits have output voltage levels equal to
Vdd or gnd without involving threshold voltage drop issue. Non full swing circuits
considers threshold voltage and suffers from threshold voltage drop.

On the basis of logic style, full adder circuits are classified into two categories:
Single logic and hybrid logic. Single logic circuits uses only one logic style whereas
hybrid logic circuits uses at least two logic styles. Pass transistor based single logic
full adder is the oldest circuit of all. But the drawback in this design is its suffers
threshold voltage drop. To overcome this complementary symmetry CMOS(CCMOS)
is designed. But in CCMOS large number of transistors are used which leads to high
area utilization and it consists of high input impedance which results in slower
working of the circuit.

So instead of using single logic circuits, now designers are interested to design the
hybrid circuits of full adder. Main aim to design hybrid logic circuit is to optimize the
above mentioned drawbacks and to bring better performance. Full adder designed
using the combination of CCMOS and Pass Transistors enhanced the signal strength
but it also resulted in speed issue.

The project-LOW-POWER HYBRID 1-BIT FULL ADDER by Parameshwara M.C.,

Srinivasaiah Hc.Major aim of this project is to introduce a Hybrid Adder for low
power consumption applications with high performance. Drawbacks in this circuit
are-The Full Adder uses four transistors to generate the XNOR signal. Later, the XOR
signal was obtained through an inverter. Finally, two separate circuits were developed
for sum and output carry signals that employed XOR‐XNOR signals as inputs. Since
the XOR signal faces one inverter delay more than the XNOR signal, the sum and

3
carry circuit needs to wait for the computation of the XOR signal which makes the
output signal generation slower.

The project Low-Power High-Speed Hybrid 1-bit Full Adder Circuit by

Partha Bhattacharyya.The main aim of this project is to design Hybrid Adder which
consumes less power and increase speed and decrease the transistor count.It
succeeded to decrease the average power but has a drawback is this circuit produces
high propagation delay.

To overcome all the above issues, full adder structure is formed using XOR-XNOR
circuit simultaneously. But usage of this circuits should be well enough to avoid
signal delay, slower generation of signal. To reduce delays, parallel connection of
XOR-XNOR connection is suitable. But this circuit involves more usage of transistors
which may result in high input impedance.

In order to avoid all these, the circuit we designed consists of transmission gates and
pass transistors. This circuit is constructed in a way to perform XOR and XNOR
operations. This circuit involves at least one full swing path which results to avoid
voltage degradation phenomenon. Circuit also involves parallel combination to reduce
the delay and this circuit does not involve any feedback connection which results in
reduction of delay.

4
2.2 INTRODUCTION TO VLSI TECHNOLOGY:
VLSI stands for "Very Large Scale Integration". This is the field which involves
packing more and more logic devices into smaller and smaller areas.
 Simply we say Integrated circuit is many transistors on one chip.
 Design/manufacturing of extremely small, complex circuitry using modified
semiconductor material
 Integrated circuit (IC) may contain millions of transistors, each a few mm in
size
 Applications wide ranging: most electronic logic devices

In olden days, when huge computers made of vacuum tubes could occupy an
entire dedicated rooms and could do about 360 multiplications of 10 digit numbers in
a second. Modern day computers are getting smaller, faster, and cheaper and more
power efficient for every progressing second. The electronic miniaturizing started
when the occurrence of semiconductor transistor by Bardeen (1947-48) and then the
Bipolar Transistor by Shockley (1949) in the Bell Laboratory.

The first IC (Integrated Circuit) was invented by Jack Kilby in 1958, in the form
of a Flip Flop our ability to pack more and more transistors onto a single chip has
doubled roughly every 18 months, in accordance with the Moore’s Law. Such
exponential or increasing development had never been seen in any other field and still
it is continuing in major areas of research work.

Hybrid Adder circuit consists of 18 transistors connected in an order to get the output
as a full adder. Also the simulation waveform is generated to calculate the delay and
to get better understanding of sum and carry circuits.
VLSI technology is used in many areas:
1. digital electronics control.
2. Electronic system in cars.
3. Transaction processing system(ATM).
4. Personal computers and workstation.
5. Medical electronic system etc..

5
2.3 CMOS TECHNOLOGY:
Introduction to MOS Technology:
In the IC design, the basic and most essential component is the transistor. So
MOSFET is one kind of transistor used in many applications. The formation of this
transistor can be done like a sandwich by including a semiconductor layer, generally a
wafer, a slice from a single crystal of silicon; a layer of silicon dioxide & a metal
layer. These layers allow the transistors to be formed within the semiconductor
material. A good insulator like Sio2 has a thin layer with a hundred molecules
thickness. The transistors which we use polycrystalline silicon (poly) instead of metal
for their gate sections. The Polysilicon gate of FET can be replaced almost using
metal gates in large scale ICs. Sometimes, both polysilicon & metal FET’s are
referred to as IGFET’s which means insulated gate FETs, because the Sio2 below the
gate is an insulator.
CMOS (Complementary Metal Oxide Semiconductor):
The main advantage of CMOS over NMOS and BIPOLAR technology is the much
smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary
MOS circuit has almost no static power dissipation. Power is only dissipated in case
the circuit actually switches. This allows integrating more CMOS gates on an IC than
in NMOS or bipolar technology, resulting in much better performance.
Complementary Metal Oxide Semiconductor transistor consists of P-channel MOS
(PMOS) and N-channel MOS (NMOS).

Figure 2.1-CMOS Fabrication

6
2.4 ADDERS:
An Adder is a digital circuit that performs addition of numbers.
In many computers and other kinds of processors adders are used in the arithmetic
logic units or ALU. They are also used in other parts of the processor, where they are
used to calculate addresses, table indices, increment and decrement operators and
similar operations.
Mostly, adders operate on binary numbers.

Binary Adder:
An Adder which works on binary inputs to add is known as Binary Adder.
Binary Adders are arithmetic circuits in the form of half-adders and full-adders used
to add. together two binary digits.
 Half-Adder:
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C).The carry signal represents an overflow into the next digit of a multi-digit
addition.The Boolean logic for the sum (S) will be A′B + AB′ whereas for the carry
(C) will be AB.

Figure 2.2-Half Adder

 FULL ADDER:
A one-bit full-adder adds three one-bit numbers, often written as A , B
and Cin ; A and B are the operands, and Cin is a bit carried in from the previous
less-significant stage.Output carry and sum typically represented by the
signals Cout and S.

7
A full adder can be implemented in many different ways such as with a
custom transistor-level circuit or composed of other gates. One example
implementation is with S = A ⊕ B ⊕ Cin and Cout = (A . B) ⊕ (Cin ⋅ (A ⊕ B)).
A full adder can be implemented using nine NAND gates.

Figure 2.3-Full Adder

Adders supporting multiple bits:

 Ripple-carry adder:
A ripple carry adder is a logic circuit in which the carry-out of each full adder is the
carry in of the succeeding next most significant full adder. It is called a ripple carry
adder because each carry bit gets rippled into the next stage.
The layout of a ripple-carry adder is simple, which allows fast design time; however,
the ripple-carry adder is relatively slow, since each full adder must wait for the carry
bit to be calculated from the previous full adder.
The gate delay can easily be calculated by inspection of the full adder circuit. Each
full adder requires three levels of logic.

Figure 2.4

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 Carry - lookahead Adder:
Carry lookahead Adder is used in the circuits in which computation time plays a
major role that is to reduce computation time of the circuit.They work by creating two
signals (P and G) for each bit position, based on whether a carry is propagated
through from a less significant bit position (at least one input is a 1), generated in that
bit position (both inputs are 1), or killed in that bit position (both inputs are 0).

Some advanced carry-look ahead architectures are:

Manchester carry chain ,
Brent–Kung adder (BKA),
and the Kogge–Stone adder (KSA).

Figure 2.5

 Carry-save adders:
A carry-save adder is a type of digital adder, used to efficiently compute the sum of
three or more binary numbers. It differs from other digital adders in that it outputs two
(or more) numbers, and the answer of the original summation can be achieved by
adding these outputs together.
The circuit representation of 4-bit carry-save adder is as follows:

9
 Figure 2.6

2.5 FULL ADDER CLASSIFICATION:

Full adders are classified into different types on certain parameters.
1. Based on output voltage.
2. Based on design style.
3. Based on logic style.
On the basis of output voltage, full adder circuits are classified into two categories:
Full swing and non full swing. Full swing circuits have output voltage levels equal to
Vdd or gnd without involving threshold voltage drop issue. Non full swing circuits
considers threshold voltage and suffers from threshold voltage drop.

On the basis of design, design divided into two categories: Static Style and Dynamic
Style.Static Full Adders are reliable,simpler with less power requirement but the on
chip area requirement is usually large when compared to Dynamic Full Adders.

On the basis of logic style, full adder circuits are classified into two categories:
Single logic and hybrid logic. Single logic circuits uses only one logic style whereas
hybrid logic circuits uses at least two logic styles. Pass transistor based single logic
full adder is the oldest circuit of all.

10
 CHAPTER 3

SOFTWARE AND HARDWARE REQUIREMENTS

3.1 CADENCE TOOL:

3.1.1 INTRODUCTION:

Cadence is an Electronic Design Automation (EDA) environment that integrates

several design tools in a single design suite. This tool involves the process in which it
will use the Cadence tools to design CMOS integrated circuits. It is used to go
through mastering schematic entry, layout, simulation, post layout simulation and
layout versus schematics. Each process will consist in designing and simulating
different microelectronic building blocks that you will reuse in the project.

3.1.2 Setting the environment for running Cadence remotely for the
implementation of the circuit:

This section will guide through all the steps to run Cadence remotely over a Linux
terminal for the implementation of the circuit.The following steps are:

Step 1:

Open the Linux terminal.

Step 2:

Open a new terminal window. Select Applications-> System Tools -> terminal

Select tool-> Library Manager

Create File->On opening Library create a new file.

Give the name to the file.

Attach it to the existing Library.

Step 3:

Creating the cell

Select tools --> Library Manager

11
Select the Library name

Give the name of the cell.

Step 4:

To add the components, following process is performed in the tool :

Enter i on the keyboard to select instance.

Select suitable Library.

Step 5:

To perform Analysis, the steps are:

Select launch --> ADE L

Select Analysis --> choose the required option like ‘tran’ for normal analysis.

Select time as ’zoons’ and click ok.

Select output --> to be plotted --> select on schematic

Select inputs and outputs from the schematic circuit.

Enter netlist and run.

Step 6:

To visualize and to perform delay analysis:

Select launch --> ADE L

Select analysis --> choose

Select ‘tran’ ans stop time “Zoons”

Select output --> to be plotted --> select the terminals from the schematic diagram.

To calculate propagation delay, difference between input and output has to be

performed.

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3.1.3 The Library manager :

A library is a collection of cells, such as NOT, AND, NAND, etc. These cells contain
several views, including “schematic”, “layout”, “extracted” and “symbol”.

Open the Library manager: In the CIW window, go to tools -> library manager. The
library manager window opens, has. The left column is listing the available libraries
for the current kit. The “analogLib” and the “cmosp18” libraries contain all the
necessary components to complete this Lab. The center column is listing the available
cells for each library. A cell is a specific building block i.e. a circuit that belongs to a
specific library. The right column is listing the several available views of each cell
(extracted, layout, schematic, etc.).

 Extracted view: contains a representation of the netlist that has been extracted
from a layout view.

 Layout view: contains the mask representations of the silicon devices and wiring.

 Schematic view: contains the schematic representation of a cell.

 Symbol view: contains a symbolic representation of a cell to be instantiated in a

top-level schematic view.

 Behavioural view: contains a HDL description of the cell.

Create a new library:

After having opened the Library manager, do the following steps to create your new
library:

Step 1: In the Library manager, go to file -> new library. Then, type in the name of
the new library, for example Label1, and click OK.

Step 2: Select “attach to an existing techfile”, and click OK.

Step 3: In the new pop-up window, select “cmosp18” as the technology file, and then
click OK.

The library Label1 is now listed in the Library manager.

13
3.1.4 Schematic design and simulation:

This is to know,how to create a simple schematic with the Schematic editor and how
to simulate a digital circuit using Spectre. It also explains how to simulate the
characteristics of a CMOS circuit and how to obtain its parameters. In order to work
efficiently with the Schematic editor, there are few direct keys for the most frequently
used commands as shown in table.

Fig-3.1

Create a new schematic:

Following are the steps to create a new schematic cell view:
Step 1: In the Library manager, select your new Library , then go to File -> new ->
cell view.
Step 2: In the pop-up window, type in a new cell name, like cmos_image_schem,
make sure to select composer-schematic (selected by default), and click Ok.
Step 3: A schematic editor window appears .

Draw a new schematic:

Following are the steps to create the new schematic:
Step 1: For adding any component in the new schematic, type "i" with the schematic
window opened.
A new pop-up window appears.
Step 2: Click Browse. The Library manager pops up. Select the “Generic13” library.
Select the respective cell, and choose the symbol view.

14
Step 3: Go back into the schematic window and place the component with a left click
of the mouse.
Step 4: Select this cell in the schematic, and press “q”. In the “instance properties”
window, change Wire size to required width and keep L to 180nm or 90nm according
to the requirements , then press Esc to deselect the components.
Step 5: Repeat steps 1-3 to add remaining elements. Select this element in the
schematic, and press “q”. In the “instance properties” window, change W to required
width and keep L to 180nm or 90nm to meet the requirements then press Esc to
deselect the element.
Step 6: Add DC voltage sources to the schematic and wire them up. First, press “i”
and click Browse in the “add new instance” window. In the “Generic”or any
respective library select the “vdc” cell and its symbol view. In the “property” window,
type in “1.8 V” an example for the parameter “dc voltage”. Add required number of
voltage sources in the schematic. Press Esc to deselect any component from the
schematic. Click “w” and start wiring up the circuit. For drawing wires, click on each
terminal and move the mouse to the other desired terminal.
Step 7: Add a tie down to the common node . Type “i” or use and add select the
“tiedown” cell, symbol view, from the respective Library.
Step 8: Add a net name between the elements or components. To do so, select the
icon in the left menu and type “Vo“ in the “name“ field. Click “Hide“, and place the
net in the schematic. Add the net "Vi" between the gates of the transistors and the
input source using the same procedure.

Step 9: Make sure that your schematic is identical and press “x” to save your work, or
alternatively, select design -> save and check.

15
3.1.5 Perform a DC simulation :
Step 1: With the schematic window of the test bench opened, go to tool -> analog
environment. The Analog design environment (ADE) window pops up. The
important sections of this tool are described in Table .

Fig 3.2

Step 2: Choose a model file in order to simulate the circuit with the right parameters.
In the Analog design environment window, go to the Setup menu, select “model
library”, and type in
CMC/kits/cmosp18.5.2/models/spectre/spectre445_mixed/mm018.csc
Step 3: Type in “tt” in the section box and click the add button. Then, click OK
before closing the windows.
Step 4: Go to session -> options and choose AWD for waveform tool. Analog
waveform display (AWD) is a waveform display tool that is included with the spectre
simulator in order to print simulation results.
Step 5: Go to the Analyses menu, select Analyses -> choose. In the Choosing
Analyses window, click dc at Analysis and select save DC operating point. Click OK.
Step 6: Click the traffic green light button to run the simulation. Messages will appear
in the CIW window indicating that the simulation has completed successfully .

3.1.6 Parametric simulation (part 1)

A parametric simulation is very useful in order to obtain the Vi-Vo curve of the
circuit for different transistor sizes.
Step 1: In the schematic editing window, select the component and press “q” to open
its “object properties” window. Put required dimension as width, and click ok.
Step 2: In the Analog design environment window, go to variables -> copy from cell
view. The variable "Factor" appears in variable list. Double click on it and put an

16
initial value. Then, click OK. This means the width of the selected component will be
multiplied by given width dimension.
Step 3: In the Analog design environment window, select tools -> parametric
analysis. The parametric analysis window appears. Go to setup -> pick name for
variable -> sweep 1. Select "Factor" and click OK. Configure the “Range Type”.
Click “Analysis” and select “Start”.
The parametric simulation will start running. When the simulation is finished, the
plot of Vi-Vo curves for different value of transistor sizes will be displayed.

Parametric simulation (part 2)

A parametric simulation is useful in order to obtain the Current-Vi curve of the circuit
for different transistor sizes.
Step 1: In the schematic editing window, select the component and press “q” to open
its “object properties” window. Put desired dimension of width, and click ok.
Step 2: In the Analog design environment window, select the Vo output to be plotted
and click the icon to remove it. Go to outputs -> to be plotted -> select on
schematic, and then click on the red square under the V0 source. A circle around it
should appears, it means the current flowing through the source (and the transistors)
will be plotted. Press "Esc" to exit the net selection mode.
Step 3: In the Analog design environment window, select tools -> parametric
analysis. The parametric analysis window appears. Go to setup -> pick name for
variable -> sweep 1. Select "Factor" and click OK. Again, configure the “Range
Type” . Click “Analysis” and select “Start”.
The parametric simulation will start running. When the simulation is finished,the plot
of Current-Vi curves for different value of transistor sizes will be displayed.
In the similar way, the plots between two parameter can be generated.

17
3.1.7 Creating the symbol view from the schematic view:
To make a symbol from a schematic view, select design -> create cellview -> from
cellview in the Virtuoso schematic editor with your schematic of the circuit opened.
Click Ok after the “cellview from cellview” dialog box appears. Rearrange pins in the
“symbol generation options” dialog box as follow and click Ok.

Pin position of the schematic as an example

Fig 3.3

A symbol of the circuit will be created.

18
 CHAPTER 4
METHODOLOGY

4.1 HYBRID ADDER:

When an adder is constructed by implementing one or more logic is called a Hybrid
Adder.
In the above figure, the circuit can be of different or same type to get sum and carry
circuit.
The idea of combining designs to form hybrid structure brings the High performance
and low cost products.The circuits are selected in such a way that the circuit is
suitable for desired manufacture process within the limitations.
There are two types of architectures of forming Hybrid Adder:
1. Homogeneous
2. Heterogeneous

Homogeneous:
The merger of same type of two or more adders forms Homogeneous Architecture.
Example:1. Carry Select Adder(CSLA).
2. Homogeneous CCLA

Heterogeneous:
The merger of different type of two or more adder forms Heterogeneous Architecture.
Example:
1.Heterogeneous CCLA -combination of Homogeneous Adder and Full Adder.
2. Heterogeneous Carry Select Adder.

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4.2 BLOCK DIAGRAM OF A FULL ADDER:

S1

A MODULE 2
MODULE 1
B

C1 Cin

MODULE 3

S1=sum of the circuit

C1=carry of the circuit

Fig 4.1

4.3 THE CIRCUIT DESIGN:

The rough circuit design of the proposed Hybrid Adder is the fig(1).

4.3.1 MODULES:
MODULE-1:
Initially an input circuit “A” is designed and made as first circuit. A circuit adjacent to
the circuit “A” is designed and that circuit is “B”. In the similar fashion circuit “C” is
designed. All these circuits are placed in the same row and are fed with the voltage
source.

MODULE-2:
Output of these circuits “A”, “B” and “C” are connected to the sum circuit and the
respective results are observed using simulation waveform. Also the proper care is

20
taken to avoid the much overlapping of wires during connections in the circuit for the
better visual of the circuit and to be easily understood just by having glance on it.

MODULE-3:
Output of these circuits “A”, “B” and “C” are connected to the carry circuit and the
respective results are observed using simulation waveform. Also the proper care is
taken to avoid the much overlapping of wires during connections in the circuit for the
better visual of the circuit and to be easily understood just by having glance on it.
Simulation is performed to calculate delay of the circuit and also to have a proper
visual of the respective input and output sub-circuits.

fig-4.2

21
4.3.2 COMPONENTS USED IN THE CIRCUIT:
NMOS transistor
PMOS transistor
Voltage source
Ground

NMOS Transistor:
NMOS stands for n-type metal oxide semi conductor transistor which has major
elements are electrons .
N-type logic uses n-type (-) MOSFETs (metal-oxide-semiconductor field-effect
transistors) to implement logic gates and other digital circuits.These nMOS
transistors operate by creating an inversion layer in a p-type transistor body. This
inversion layer, called the n-channel, can conduct electrons between n-type "source"
and "drain" terminals. The n-channel is created by applying voltage to the third
terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of
operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and
velocity saturation.

PMOS Transistor:
A PMOS transistor is made up of p-type source and drain and a n-type substrate.
When a positive voltage is applied between the source and the gate (negative voltage
between gate and source), a p-type channel is formed between the source and the
drain with opposite polarities. A current is carried by holes from source to the drain
through an induced p-type channel. A high voltage on the gate will cause a PMOS
not to conduct, while a low voltage on the gate will cause it to conduct. Logic gates
and other digital devices implemented using PMOS are said have PMOS logic.
PMOS technology is low cost and has a good noise immunity.

Figure 4.3
Voltage Source:

22
A voltage source is a two-terminal device which can maintain a fixed voltage. An
ideal voltage source can maintain the fixed voltage independent of the load resistance
or the output current. However, a real-world voltage source cannot supply unlimited
current. A voltage source is the dual of a current source.

Figure 4.4
Ground:
Ground or earth is a reference point in an electrical circuit from which voltages are
measured, a common return path for electric current, or a direct physical connection
to the earth.

Figure 4.5
The circuit design is as follows:
 Initially circuit A is implemented in the cadence tool.This circuit describes that it
represents input A. After successful placing of the components required to build
the circuit A this circuit is checked by clicking on check and save which is
provided by the tool.
 When this mode is on, the tool scans the connections of all the components of the
circuit that is wiring is properly done, circuit is placed properly on the sheet
provided by the tool etc..
 If the connections are correct, the tool will save the circuit, if there are any wrong
corrections the tool points out the place where the connections are wrong.
 After successful saving of the circuit, circuit B is placed on the sheet and the
process is repeated.Second Circuit represents input B.
 As mentioned above, all the circuits are placed and finally once again checked
and saved the circuit.

23
 Then the simulation part comes. To simulate the circuit in the tool, choose
analysis in the tool and select input connection and output connections from the
circuit and save it.
 Then simulation has to run to obtain simulation waveforms.
 To calculate delay, calculator can be used which is provided in the tool itself.
 By selecting the required values to calculate delay on the calculator, delay can be
calculated.
 The alternate method to calculate delay is plotting the delay simulation using
simulation process.

By following above steps, circuit is designed, simulation is obtained.

All the results are saved and a comparison table is plotted.

24
 CHAPTER-5

RESULTS AND DISCUSSION

The major aim of this hybrid full adder circuit is to decrease the propagation delay of
the circuit. The actual design of the circuit using Cadence tool is as follows:

This circuit consists of 18 transistors.

Schematic Diagram:

Figure 5.1

25
Initial circuit is the input “A” circuit.

The second circuit is the input “B” circuit.

Input “C” circuit is the third circuit.

Below initial circuit is the “Sum” circuit.

Followed by circuit is the “Carry” circuit.

Netlist of the Circuit:

Figure 5.2

26
 Netlist is the process which can be generated using cadence tool in order to get
the details of all the components used in the circuit.

 Circuit A is designed by placing an NMOS transistor and PMOS transistor in the

form of cmos connection and an input voltage is applied at the input terminal and
the input is in pulse form.

 Output of the A and B is added.

 Circuit B is designed by placing NMOS transistor and PMOS transistor in the

form of cmos connection and an input voltage is applied at the input terminal and
the input is in pulse form.

 Addition of A and B is obtained by applying XOR operation.

 Similarly circuit C is constructed by using an NMOS and PMOS transistor and an

input is provided to this circuit also.Input is of the pulse form.

 Now a circuit is to be constructed by using output of xor operation between A and

B and C as inputs to this circuit.This circuit is also constructed to perform XOR
operation so that the sum of the entire inputs will be obtained at the output.

 Another circuit is constructed to compute carry of the designed circuit.It can be

computed by applying AND operation on the given inputs.

 Output of the last circuit gives carry of the inputs.

27
The simulation waveforms of the “sum” and “carry” circuits are as follows :

Figure 5.3

Initial Waveform indicates input A, a pulse wave- when voltage source is applied.

Waveform II indicates input B ,a pulse wave-when voltage source is applied .

Waveform III indicates input C, a pulse wave- when voltage source is applied.

Waveform IV indicates output of Sum Circuit, which is generated when sum of three
inputs is performed

Waveform V indicates output of Carry Circuit, which is generated when Carry of the
circuit is generated.

28
Delay simulation waveform is as follows:

Figure 5.4

29
Delay of the circuit is calculated by plotting the graph as shown in the figure.

The difference between input time period and output time period gives the
propagation delay.

Output time period = 100.95578 ns.

Input time period = 100.948 ns.

Delay of the circuit = output time period - input time period

= (100.95578 - 100.948) ns

= 0.00778 ns

= 7.78 ps.

Delay of the circuit = 7.78 ps

Delay comparison with few existing circuits:

Project titles Propagation Delay Transistor Count

1.
Hasan,M.,et al,:Design of a 65.7ps 23
scalable low power 1-bit hybrid
full adder for fast computation.

2.
Partha.Bhattacharyya-Performance 252.3ps 16
Analysis of a Low-Power
High-Speed Hybrid 1-bit Full
Adder Circuit.

3.Proposed project-DESIGN OF 7.78ps 18

HIGH PERFORMANCE 1-BIT
HYBRID ADDER

Table 5.5

30
ADVANTAGES:

REDUCES TIME DELAY.

LESS TRANSISTOR COUNT.

SMALLER AREA CAN BE ACHIEVED.

IT IS FASTER.

APPLICATIONS:

It can be used in electronics in embedded applications like smart watches etc.

It is used in high performance processors.

It can be used in ALU.

31
 CHAPTER 6

CONCLUSION AND FUTURE SCOPE

Hybrid Adder using 18 transistors which are of pass transistors, transmission gates
and cmos transistors is successfully designed using cadence tool. The respective sum
and carry waves are also simulated using cadence tool. Propagation delay is also
calculated and the result is compared with few existing designs and the results are
tabulated.

FUTURE SCOPE:

This Hybrid circuit can be used in any logic circuit which mostly concentrates on less
propagation delay which results in high performance of the circuit.

32
 REFERENCES

1.Parameshwara, M.C., Srinivasaiah, H.C.: Low‐power hybrid 1‐bit fulladder circuit

for energy efficient arithmetic applications. J. Circ. Syst.Comput. 26(1), 1–15 (2017).

2.Bhattacharyya, P., et al.: Performance analysis of a low‐power high‐speed hybrid

1‐bit full adder circuit. IEEE Trans. Very Large Scale Integr. Syst.23(10), 2001–2008
(2015).

3.Hasan, M., et al.: Comprehensive study of 1‐bit full adder cells: review,performance
comparison and scalability analysis. SN Applied Sciences.3(6), 644 (2021).

4.Kandpal, J., et al.: High‐speed hybrid‐logic full adder using high‐performance 10‐T
XOR–XNOR cell. IEEE Trans. Very Large ScaleIntegr. Syst. 28(6), 1413–1422
(2020).

5.Sharma, A., Sohal, A., Kaur, H.J.: Sleepy CMOS‐sleepy stack (SC‐SS): a novel
high speed, area and power efficient technique for VLSI circuit design. J. Circ.
Syst.Comput. 28(12) (2019).

6.Hasan, M., et al.: Gate diffusion input technique based full swing and scalable 1‐bit
hybrid full adder for high performance applications. Eng.Sci. Technol. An Int. J. 23(6),
1364–1373 (2020).

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