MAX1232 Microprocessor Monitor

General Description Features

The MAX1232 microprocessor (μP) supervisory circuit ●● Consumes 1/10th the Power of the DS1232
provides μP housekeeping and power-supply supervision ●● Precision Voltage Monitor—Adjustable +4.5V or
functions while consuming only 1/10th the power of the +4.75V
DS1232. The MAX1232 enhances circuit reliability in μP
systems by monitoring the power supply, monitoring the ●● Power-OK/Reset Pulse Width—250ms Min
software execution, and providing a debounced manual ●● No External Components
reset input. The MAX1232 is a plug-in upgrade of the ●● Adjustable Watchdog Timer—150ms, 600ms, or 1.2s
Dallas DS1232.
●● Debounced Manual Reset Input for External Override
A reset pulse of at least 250ms duration is supplied on
●● Available in 8-Pin PDIP/SO and 16-Pin Wide SO
power-up, power-down, and low-voltage brownout con-
Packages
ditions (5% or 10% supply tolerances can be selected
digitally). Also featured is a debounced manual reset
input that forces the reset outputs to their active states
Ordering Information
for a minimum of 250ms. A digitally programmable watch- PART TEMP RANGE PIN-PACKAGE
dog timer monitors software execution and can be pro- MAX1232C/D 0°C to +70°C Dice*
grammed for timeout settings of 150ms, 600ms, or 1.2s.
The MAX1232 requires no external components. MAX1232CPA 0°C to +70°C 8 PDIP
MAX1232CSA 0°C to +70°C 8 SO
Applications Ordering Information continued at end of data sheet.
●● Computers *Contact factory for dice specifications.
●● Controllers Note: Devices in PDIP and SO packages are available in both
●● Intelligent Instruments leaded(Pb) and lead(Pb)-free packaging. Specify lead(Pb)-free by
●● Critical μP Power Monitoring adding the “+” symbol at the end of the part number when order-
ing. Lead-free not available for CERDIP package.

Typical Operating Circuit Pin Configurations

TOP VIEW
PB RST 1 8 VCC
RST
VCC TD 2 7 ST
5%/10% MAX1232
TOLERANCE RESET TOL 3 6 RST
TOL SELECT GENERATOR
GND 4 5 RST
REF
RST DIP/SO

PB RST MAX1232
DEBOUNCE N.C. 1 16 N.C.

PB RST 2 15 VCC

N.C. 3 14 N.C.

TD 4 MAX1232 13 ST
TD WATCHDOG WATCHDOG ST
TIMEBASE TIMER N.C. 5 12 N.C.
SELECT
TOL 6 11 RST
N.C. 7 10 N.C.
GND
GND 8 9 RST

WIDE SO

19-3899; Rev 2; 9/14

MAX1232 Microprocessor Monitor

Absolute Maximum Ratings

Voltage Range on Any Pin (with respect to GND)......-1V to +7V Storage Temperature Range............................. -65°C to +160°C
Operating Temperature Range Lead Temperature (soldering, 10s).................................. +300°C
C Suffix................................................................0°C to +70°C
E Suffix............................................................ -40°C to +85°C
M Suffix.......................................................... -55°C to +125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Recommended DC Operating Conditions

(TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC 4.5 5.0 5.5 V
ST and PBRST Input High Level
VIH 2.0 VCC + 0.3 V
(Note 1)
ST and PBRST Input Low Level VIL -0.3 +0.8 V

DC Electrical Characteristics
(VCC = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ST, TOL IIL -1.0 +1.0 µA
Output Current RST IOH VOH = 2.4V -1.0 -12 mA
Output Current RST, RST IOL VOL = 0.4V 2.0 10 mA
Operating Current (Note 2) ICC 50 200 µA
VCC 5% Trip Point (Note 3) VCCTP TOL = GND 4.50 4.62 4.74 V
VCC 10% Trip Point (Note 3) VCCTP TOL = VCC 4.25 4.37 4.49 V

Capacitance (Note 4)
(TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Capacitance ST, TOL CIN 5 pF
Output Capacitance RST, RST COUT 7 pF

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MAX1232 Microprocessor Monitor

AC Electrical Characteristics
(VCC = +5V ±10%, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PBRST (Note 5) tPB Figure 3 20 ms
PBRST Delay tPBD Figure 3 1 4 20 ms
Reset Active Time tRST 250 610 1000 ms
ST Pulse Width tST Figure 4 75 ns
Figure 4, TD pin = 0V 62.5 150 250
ST Timeout Period tTD TD pin = open 250 600 1000 ms
TD pin = VCC 500 1200 2000
VCC Fall Time (Note 4) tF Figure 5 10 µs
VCC Rise Time (Note 4) tB Figure 6 0 µs
VCC Detect to RST High and
tBPD Figure 7, VCC falling 100 ns
RST Low
VCC Detect to RST Low and RST
tBPU Figure 8, VCC rising 250 610 1000 ms
Open (Note 6)
Note 1: PBRST is internally pulled up to VCC with an internal impedance of typically 40kΩ.
Note 2: Measured with outputs open.
Note 3: All voltages referenced to GND.
Note 4: Guaranteed by design.
Note 5: PBRST must be held low for a minimum of 20ms to guarantee a reset.
Note 6: tR = 5μs.

Pin Description
PIN
NAME FUNCTION
WIDE SO DIP/SO
1, 3, 5, 7, 10,
— N.C. No Connection
12, 14, 16
Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms
2 1 PBRST
in duration and is guaranteed to recognize inputs of 20ms or greater.
Time Delay Set. The watchdog timebase select input (tTD = 150ms for TD = 0V,
4 2 TD
tTD = 600ms for TD = open, tTD = 1.2s for TD = VCC).
6 3 TOL Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance.
8 4 GND Ground
Reset Output (Active High). Goes active:
(1) If VCC falls below the selected reset voltage threshold.
9 5 RST (2) If PBRST is forced low.
(3) If ST is not strobed within the minimum timeout period.
(4) During power-up.
11 6 RST Reset Output (Active Low, Open Drain). See RST.
13 7 ST Strobe Input. Input for watchdog timer.
15 8 VCC +5V Power-Supply Input

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MAX1232 Microprocessor Monitor

Detailed Description Watchdog Timer

Power Monitor The microprocessor drives the ST input with an input/
output (I/O) line. The microprocessor must toggle the ST
A voltage detector monitors VCC and holds the reset input within a set period (as determined by TD) to verify
outputs (RST and RST) in their active states whenever proper software execution. If a hardware or software fail-
VCC is below the selected 5% or 10% tolerance (4.62V ure keeps ST from toggling within the minimum timeout
or 4.37V, typically). To select the 5% level, connect TOL period—ST is activated only by falling edges (a high-to-
to ground. To select the 10% level, connect TOL to VCC. low transition)—the MAX1232 reset outputs are forced to
The reset outputs will remain in their active states until their active states for 250ms (Figure 2). This typically initi-
VCC has been continuously in-tolerance for a minimum of ates the microprocessor’s power-up routine. If the inter-
250ms (the reset active time) to allow the power supply ruption continues, new reset pulses are generated each
and μP to stabilize. timeout period until ST is strobed. The timeout period is
The RST output both sinks and sources current, while the determined by the TD input connection. This timeout peri-
RST output, an open-drain MOSFET, sinks current only od is typically 150ms with TD connected to GND, 600ms
and must be pulled high. with TD floating, or 1200ms with TD connected to VCC.
Pushbutton Reset Input The software routine that strobes ST is critical. The code
The MAX1232’s debounced manual reset input (PBRST) must be in a section of software that executes frequently
manually forces the reset outputs into their active states. enough so the time between toggles is less than the
The reset outputs go active after PBRST has been held watchdog timeout period. One common technique con-
low for a time tPBD, the pushbutton reset delay time. The trols the microprocessor I/O line from two sections of the
reset outputs remain in their active states for a minimum program. The software might set the I/O line high while
of 250ms after PBRST rises above VIH (Figure 3). operating in the foreground mode, and set it low while in
the background or interrupt mode. If both modes do not
A mechanical pushbutton or an active logic signal can execute correctly, the watchdog timer issues reset pulses.
drive the PBRST input. The debounced input ignores
input pulses less than 1ms and is guaranteed to recog-
nize pulses of 20ms or greater. The PBRST input has
an internal pullup to VCC of about 100μA; therefore, an
external pullup resistor is not necessary.

+5V
+5V

10kΩ

VCC TD

PB RST ST I/O 7805

+8V +5V
3-TERMINAL VCC RST RESET
MAX1232 MICROPROCESSOR REGULATOR
RST RESET 0.10µF MAX1232 MICROPROCESSOR

ST I/O
GND TOL
TD TOL GND

Figure 1. Pushbutton Reset Figure 2. Watchdog Timer

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MAX1232 Microprocessor Monitor

tST

ST
tPB

PB RST tPBD

tTD
VIH

VIL NOTE: tSD IS THE MAXIMUM ELAPSED TIME BETWEEN ST HIGH-TO-LOW

TRANSITIONS (ST IS ACTIVATED BY FALLING EDGES ONLY) WHICH WILL
tRST KEEP THE WATCHDOG TIMER FROM FORCING THE RESET OUTPUTS
ACTIVE FOR A TIME OF tRST. tTD IS A FUNCTION OF THE VOLTAGE AT
RST THE TD PIN, AS TABULATED BELOW.

tTD
CONDITION MIN TYP MAX
RST
TD pin = 0V 62.5ms 150ms 250ms
TD pin = open 250ms 250ms 1000ms
TD pin = VCC 500ms 1200ms 2000ms

Figure 3. Pushbutton Reset. The debounced PBRST input Figure 4. Watchdog Strobe Input
ignores input pulses less than 1ms and is guaranteed to
recognize pulses of 20ms or greater.

tF tR

VCC

+4.75V +4.75V

+4.25V +4.25V

VCC

Figure 5. Power-Down Slew Rate Figure 6. Power-Up Slew Rate

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MAX1232 Microprocessor Monitor

VCC

+4.5V (5% TRIP POINT)

+4.75V (5% TRIP POINT)
+4.25V (10% TRIP POINT)
+4.5V (10% TRIP POINT)

VCC

tRPD
tRPU
RST
RST
VOH
VOH

VOL
RST VOL
RST

VCC SLEW RATE = 1.66mV/sec (0.5V/300µsec)

Figure 7. VCC Detect Reset Output Delay (Power-Down) Figure 8. VCC Detect Reset Output Delay (Power-Up)

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MAX1232 Microprocessor Monitor

Chip Topography Ordering Information

PART TEMP RANGE PIN-PACKAGE
PB RST VCC
MAX1232CWE 0°C to +70°C 16 Wide SO
MAX1232EPA -40°C to +85°C 8 PDIP
MAX1232ESA -40°C to +85°C 8 SO
MAX1232EWE -40°C to +85°C 16 Wide SO
MAX1232MJA -55°C to +125°C 8 CERDIP
*Contact factory for dice specifications.
Note: Devices in PDIP and SO packages are available in both
TD leaded(Pb) and lead(Pb)-free packaging. Specify lead(Pb)-free by
0.099" adding the “+” symbol at the end of the part number when order-
(2.51 mm) ing. Lead-free not available for CERDIP package.
ST
TOL

Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
RST only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.

LAND
PACKAGE PACKAGE OUTLINE
GND RST PATTERN
0.070" TYPE CODE NO.
NO.
(1.78 mm)
8 CERDIP J8-2 21-0045 —
8 PDIP P8+2 21-0043 —
8 SO S8+4 21-0041 90-0096
16 Wide SO W16+1 21-0042 90-0107

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MAX1232 Microprocessor Monitor

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
1 11/05 Added lead-free information to the Ordering Information table 1, 6
2 9/14 Removed reference to automotive systems in the Applications 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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