Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control
Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control
Wilhelmsson, Carl
2007
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LUNDUNI
VERSI
TY
PO Box117
22100L und
+4646-2220000
Carl Wilhelmsson
ISSN 0282-1990
Carl Wilhelmsson
Carl Wilhelmsson
ISSN 0282–1990
ISRN LUTMDN/TMHP--07/7050--SE
The first person I would like to thank for his support and understanding
is Per Tunestål. Per has as my supervisor been an excellent mentor for me
in the process of ’maturing’ academically. I want to thank my love Ella for
sharing her life with me, Ella has patience with me, my stubbornness, cu-
riosity and restlessness in a way which I never hoped to find before I meet
her. My brothers and parents, supporting me now and before are very im-
portant persons in my life, have always been and will always be. The rest of
my family are also precious to me. Friends are important to have, in good
times and in bad, I have good friends which deserves appreciation, you
know who you are. The department has a lot of young employees and the
atmosphere is open minded and good. I especially want to thank Thomas
for good friendship on and off work, sharing a great interest in motorbikes.
Andreas, Håkan, Leif and Jari have been very good friends at work before
they moved on to new challenges. Professor Bengt Johansson deserves an
acknowledgement for setting up an adequately founded and creative re-
search environment, it is inspiring to work in collaboration with large and
market leading companies. I also want to thank professor Rolf Johansson
and professor Anders Rantzer for providing a lot of important automatic-
control ideas and support. The help of Leif Andersson has been valuable
while typesetting this thesis. The technicians have helped me a lot in the
workshop keeping up my interest in workshop work in different ways. I
want to thank my friends at Toyota, especially Moriya Hidenori for tutoring
me both on and off work in Japan 2004, putting his own life in second hand
sharing a fantastic half year with me in Susono. Yanagihara Hiromichi, also
with Toyota, helped me to get to Japan and has maintained contact with me
since, keeping an eye on me and my research. Finally to those not mentioned
here I am not less grateful.
Carl
i
Acknowledgements
ii
Preface
Publications
Poster presented by the first author and Per Tunestål at the New Trends
in Engine Control, Simulation and modeling, Rueil-Malmaison, France, Oc-
tober 2006
Presented by the first author at the 31st FISITA World Automotive Congress,
Yokohama, Japan, October 2006
iii
Preface
Peripheral Publications
Presented by the first author at the Power train & Fluid Systems Conference
& Exhibition, San Antonio, TX, USA, October 2005
Presented by Bengt Johansson at the SAE 2006 World Congress & Exhibi-
tion, Detroit, MI, USA, April 2006
iv
Outline
Presented by the first author at the JSAE/SAE International Fuels & Lu-
bricants Meeting, Kyoto, Japan, July 2007
Outline
This thesis has the form of a monograph meaning that no papers are in-
cluded in the end. Never the less material from previous publications are
covered by it, the covered publications are the ones listed under the title
‘publications’ above. The first section encountered by the reader would be
the introduction, covering the motivation of this work, putting the work
into its context and setting the focus of the thesis. Following the motivation
are two sections which, very briefly, touch internal combustion engines as
such and, a bit more in detail, how to carry out combustion engine feedback
control.
The second chapter describes, in detail, the Field Programmable Gate Ar-
ray (FPGA), the first section generally, the second it’s history. The third sec-
tion of the chapter describes architectural and design considerations, both
the architecture of the actual device as well as different architectural con-
siderations on the design level are discussed. Tools and design methods are
described in the fourth section, covering topics as the basic steps carried out
by a design tool, low level design, different high level design tools and their
corresponding pros and cons. Second to last, to illustrate the power and ap-
plicability of the FPGA technology, a flavor of FPGA applications are offered
the reader. The chapter is ended with a summary.
Implementing feedback-controllers in an FPGA environment takes spe-
cial considerations devoted one chapter, Chapter three. Giving an introduc-
tion to the topic of FPGA implemented controllers, compared with micro-
controller implemented ones. Continuing on to the second section present-
ing considerations to be made generally implementing digital control, in-
cluding special considerations for the FPGA environment. Section three dis-
cusses the practical issue of internal word-length optimization, Section four
handles the issues arising when implementing highly over-sampled control
systems and Section five describes considerations which have to be made
regarding parallelization and re-formulation of control algorithms in order
to make them efficient in a FPGA implementation. A flavor of control appli-
cations implemented in FPGAs follows with the intention to give the topic
legitimacy and engage the reader, lastly this chapter is ended with a chapter
v
Preface
summary.
Chapter four deals with the work presented in the first and second pa-
per covered by this thesis, namely an FPGA implementation of a heat re-
lease analysis algorithm. The chapter describes the experimental setup, the
design tools used, the test environment as well as the algorithm used and its
actual implementation on the FPGA. Finally, of course, the outcome mean-
ing performance of the final system. This work was intended as a ‘proof of
concept’.
Approaching the end of this thesis, second to last, a chapter describing
an intended ‘rapid prototype’ system, featuring FPGA hardware and with
the capabilities of implementing controllers dealing with very fast feedback
control loops. This system is mainly intended for combustion engine feed-
back control experiments, but the ideas can be reused for similar problems.
Some concluding remarks ends the thesis.
vi
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Application, the Internal Combustion Engine . . . . 2
1.3 Combustion Engine Feedback Control . . . . . . . . . . . 3
2. The Field Programmable Gate Array (FPGA) . . . . . . . . . . . 9
2.1 FPGA Fundamental Description and its Processor Com-
parison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 FPGA history . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 FPGA Architecture and Design Considerations . . . . . . 11
2.4 FPGA Design Tools and Methods . . . . . . . . . . . . . . 16
2.5 A Flavor of Application . . . . . . . . . . . . . . . . . . . 24
2.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . 24
3. FPGAs in Feedback Control Applications . . . . . . . . . . . . . 27
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Implementation of Digital Controllers . . . . . . . . . . . 29
3.3 Word-length Optimization, Internal Number Representa-
tion and Parameter Conditioning . . . . . . . . . . . . . . 32
3.4 Over-Sampling and Limited Precision, Digital Control us-
ing the δ-transform . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Parallelization and Algorithm Reformulation . . . . . . . 39
3.6 A Flavor of Application . . . . . . . . . . . . . . . . . . . 42
3.7 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . 46
4. An FPGA Implemented Heat Release Model . . . . . . . . . . . 51
4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . 52
4.2 FPGA Layout . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 58
4.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . 62
5. FPGA Based Rapid Prototype System – a Suggestion . . . . . . 63
vii
Contents
viii
1
Introduction
1.1 Motivation
As the reader may know internal combustion engines have been the main
energy source in mobile applications for something like a century. The reader
is probably also familiar with the great threat to the environment of our
planet which are posed by mankind’s wasteful use of energy. Internal com-
bustion engines are a part of this energy waste and their contribution to
the environmental harm is worsened by the fact that most normal types
of combustion engines emit both carbon-dioxide (CO2 ) and other harmful
compounds like oxides of nitrogen(NOx ), hydrocarbon (HC), and carbon-
monoxide (CO). Due to environmental issues, the green house effect and
increasing fuel prices, there is of course a strong urge to improve the inter-
nal combustion engine. One part which is regarded as an important factor
for improving the environmental and economical performance of engines is
feedback control of various engine parameters.
The author makes no claims of writing an exhaustive description of com-
bustion engines as such. Even so they have to be briefly discussed in order
to give the reader an idea of the frame within which this work has been un-
dertaken. It is also important to introduce the reader to the topic, enabling
understanding of the relevance of this work.
Instead of an exhaustive description of combustion engines the Field
Programmable Gate Array (FPGA) is described. FPGA internals, design,
benefits and drawbacks are described, with a feedback-control perspective
in mind. The topic targeted with this thesis is how to use the FPGA as a
potentially powerful tool for feedback control, both generally speaking and
regarding its application in the combustion engine feedback control field.
For most feedback control solutions the capabilities of ‘normal’ processor
systems are more than enough and the price performance ratio of processors
1
Chapter 1. Introduction
Traditionally there have been two different kinds of engines, the Otto en-
gine (the normal gasoline engine) and the Diesel engine. Obviously there
are enormous amounts of results and written publications regarding these
two engine types and the best place in literature to start for the interested
reader would be [Heywood, 1988]. Instead of the Otto or Diesel engine a
third type of internal combustion engine principle will be discussed below.
This third engine type is called Homogeneous Charge Compression Ignition
(HCCI) and was first suggested by [Onishi et al., 1979]. The HCCI engine
can best be understood as a hybrid between the traditional Otto and Diesel
engines. Pure HCCI engines are operated with a homogeneous mixture of
fuel and air, as an Otto engine. However as opposed to Otto engines, there
is no throttling of the intake air, and there are no spark plugs. The fuel mix-
ture is instead ignited by the increased temperature originating from com-
pression of the intake charge, as in a Diesel engine. In theory this operation
principle combines the high efficiency originating from Diesel engines with
the low emissions originating from Otto engines. In practice HCCI combus-
tion can be obtained in a large number of ways, each with different bene-
fits/drawbacks compared to traditional Otto and Diesel engines.
2
1.3 Combustion Engine Feedback Control
when they did the publication rate increased. Important early publications
are for example [Najt and Foster, 1983], [Thring, 1989] and [Stockinger et al.,
1992].
The operation principle of the HCCI engine makes it possible to increase
the efficiency compared to the Otto engine due to the avoidance of throttling
losses. At the same time the high soot and nitrogen oxide emissions of the
diesel engine are avoided. Soot emission is avoided because of the homo-
geneity of the mixture and the absence of locally rich combustion zones. Ni-
trogen oxide emission is avoided because of the decreased peak in-cylinder
temperature due to the diluted operation of the engine and the absence of
stoichiometric undiluted zones.
HCCI combustion can be achieved in numerous ways, both in two and
four stroke engines. High compression ratio can be applied [Haraldsson
et al., 2002], the inlet air can be pre heated [Martinez-Frias et al., 2000]. HCCI
combustion can be induced by unconventional valve strategies that retain
hot residuals [Milovanovic et al., 2004] and the octane number of the fuel
can be altered [Olsson et al., 2001] to modulate the ignition temperature.
Since the HCCI combustion process in many operating points is unstable,
feedback combustion control is needed to operate an HCCI engine in parts
of its operating range. Such combustion control can be performed in numer-
ous ways using different actuators and sensors.
Even though it has many good features, the HCCI engine also has some
limitations besides the, just described, need for feedback combustion con-
trol. The operational principle unfortunately suffers from very high com-
bustion rates, causing noise as well as wear of engine hardware. Another
issue with the HCCI principle is low combustion efficiency at low load. This
causes high emissions of unburned hydrocarbons and carbon monoxide.
Internal combustion engines have, every since they were first developed
been under control/feedback-control. In fact control/feedback-control of com-
bustion engines is an ‘enabler’ for the success of the entire engine technique.
An engine which can not deliver a controlled amount of energy at a con-
trolled engine speed is of no use. The control tasks to be carried out by the
engine controller depends greatly on the engine type and the performance
requirements of the engine. This very brief section will mainly be devoted
to what is considered state-of-the art control technology in the HCCI field,
being a more challenging control task than state-of-the art gasoline or Diesel
engine control. An early view of state-of-the art gasoline engine control was
provided by [Powell, 1993]. For the Diesel engine however similar publi-
cations are sparse or completely lacking, such work has just recently been
3
Chapter 1. Introduction
4
1.3 Combustion Engine Feedback Control
35
Stable
30 Unstable
25
CA50 [°ATDC]
20
15
10
0
0 100 200 300 400
Cycle Index
5
Chapter 1. Introduction
• The cylinder pressure at bottom dead center of the intake stroke of the
engine equals the pressure of the intake manifold.
• The average cylinder pressure during the exhaust stroke is equal to the
back pressure in the exhaust system.
• The compression is poly-tropic and the poly tropic exponent is known
and fixed.
Tunestål offers a far more detailed explanation of how to treat the signal
from a cylinder pressure transducer, both in general and specifically using
the third method above. In [Tunestål, 2007] the same author shows a heuris-
tic approach which, using non linear least-squares estimation, finds both the
poly tropic exponent and the DC level of the pressure signal simultaneously.
dQ γ dV 1 dp
= p + V (1.1)
dθ γ − 1 dθ γ − 1 dθ
Furthermore [Tunestål, 2007] has recently expanded his work, as previ-
ously noted.The benefit from Tunestål is that the explicit heat transfer model
and model for losses over the piston rings used by Gatowski et al. no longer
are needed since the method of Tunestål includes these effects implicitly.
The main drawback with the approach taken by Gatowski et al., which is
parameter tuning, is in this way avoided. The models included in Gatowski
et al. and Woschni need to be parametrically tuned to fit every specific appli-
cation. Using the method of Tunestål it is possible to avoid the non-heuristic
6
1.3 Combustion Engine Feedback Control
2500
max Qch
HRD = CA 90% − CA 10%
2000 90%
Cumulative Heat Release [J]
50%
1000
500
10%
0
min Q
CA 10% CA 90% ch
−500
−20 −15 −10 −5 0 5 10 15 20
CA 50%
Figure 1.2 A typical heat-release curve (the integration of Equation 1.1) with the im-
portant combustion phasing, defined as the instance when half of the total heat has
been released (half of the combustion has taken place), indicated (CA50%). Bottom
axis in the figure has the unit Crank Angle Degree meaning that CA50% has the same
unit. Figure found in [Tunestål, 2000].
7
Chapter 1. Introduction
8
2
The Field Programmable
Gate Array (FPGA)
9
Chapter 2. The Field Programmable Gate Array (FPGA)
10
2.3 FPGA Architecture and Design Considerations
differ as well. FPGAs have a more flexible architecture than CPLDs. FPGAs
often feature a more complex interconnect between the internal units than
CPLDs. Another difference might be that FPGAs often contain other com-
ponents than pure logic functions e.g. distributed memory, adders, multi-
pliers or other similar components, in many cases increasing the perfor-
mance of the FPGA compared to the CPLD. FPGAs have evolved rapidly
since the first ones. Modern FPGAs can host designs with an ‘equivalent
gate count’ of many million gates. They now a days contain more and more
complex peripheral devices, e.g. processor cores, Digital Signal Processing
(DSP) blocks, even ‘mixed-mode’ FPGAs exist containing analog and partly
analog parts for example Analog-to-Digital Converters (ADC) or analog fil-
ters. The FPGA have evolved to become a flexible, cost effective and high
power device suitable for a wide variety of applications.
11
Chapter 2. The Field Programmable Gate Array (FPGA)
12
2.3 FPGA Architecture and Design Considerations
13
Chapter 2. The Field Programmable Gate Array (FPGA)
Figure 2.3 Coarse-grained versus fine-grained routing structures, also found in [Tod-
man et al., 2005]. In coarse-grained structures, shown right, a number of signal-lines
are controlled as a unit. In a fine-grained structure on the other hand a smaller number
or even a single signal is configured individually as shown left.
Figure 2.4 A typical generic reconfigurable fabric with switching units and
functional-units or logic blocks. Figure found in [Compton and Hauck, 2002].
14
2.3 FPGA Architecture and Design Considerations
15
Chapter 2. The Field Programmable Gate Array (FPGA)
[Compton and Hauck, 2002] has written an excellent section about config-
uration of FPGA devices, Compton and Hauck explains the three design
flows visible in Figure 2.6. Added to this [Todman et al., 2005] covers more
in detail a number of tools implementing the fully automated approach and
describes some tools based on data flow graphs (e.g. Simulink). Selecting
16
2.4 FPGA Design Tools and Methods
17
Chapter 2. The Field Programmable Gate Array (FPGA)
18
2.4 FPGA Design Tools and Methods
ystems,
ommu-
ermin-
rocess.
m archi-
rdware
Figure 2.6 Three different FPGA design-flows, implementing an algorithm using dif-
ferent levels of automation. Different tools and implementation approaches demand
different amounts of manual intervention by the designer/user, grey denotes manual
efforts of some sort in the corresponding step. Figure found in [Compton and Hauck,
2002].
to communicate frequently with each other. Such sub functions are grouped
together in clusters enabling a higher intercommunication rate within these
clusters. When floor-planning is finished (deciding the global placement) a
more detailed placement is carried out by the placement tool. In the last
step the different components positioned in different parts of the FPGA are
interconnected by the routing tool. As is the case with placement and floor-
planning, routing is a very difficult trade-off. Maximum FPGA clock-speed
is decided by the longest signal path within the design (since all signals
need to arrive within one clock cycle). It is not only important to the keep
the longest route within the FPGA as short as possible. Routing resources
(signal lines within the FPGA) are limited and care must be taken to opti-
mize the usage of this resource. On top of it all, to be able to route a design in
a good manner, it is essential that the placement tool has made a reasonably
good placement.
19
Chapter 2. The Field Programmable Gate Array (FPGA)
20
2.4 FPGA Design Tools and Methods
approach. A fully automated approach is, compared to the fully manual de-
sign method, much more convenient to use and even not so experienced
engineers can complete an FPGA design using one of the tools implement-
ing a fully automatic approach. The drawback is as noted previously that the
designs may be less efficient than a design which is made completely man-
ually. Semi automated approaches are, simply put, any mix between fully
automated and fully manual designs, an example could be where smaller
interface or control parts are made manually while a larger or more com-
plex algorithmic part is designed using an automated tool.
21
Chapter 2. The Field Programmable Gate Array (FPGA)
been developed and examples are given both in Todman et al. and [Comp-
ton and Hauck, 2002]. These compilers often use the possibility of co-design
and automatic partitioning, making partitioning and hardware design more
‘transparent’ for the developer (who probably is more familiar with the mi-
cro processor environment). Using for example annotation-free compilers
the developer can either choose to let the compiler decide the partitioning,
or the developer can decide how to partition the code between the micro-
processor and the hardware.
It should also be said that hardware/software partitioning is tightly cou-
pled both to parallelization and to the hardware compiler in use. Hardware
compilers in some cases co-optimize or co-decide both the parallelization
and the hardware software partitioning. Many parallelization tools by na-
ture also implicitly decide the hardware/software partitioning during the
process of deciding which parts of the code is suitable to pipeline and make
parallel for putting in hardware, in order to off-load the microprocessor.
Data Flow Graph Tools Another type of high level design tools are those
based on Data Flow Graphs. Data Flow Graphs (DFG) are typically used
within the automatic control (technical computing) and DSP communities.
There exist a number of DFG based FPGA tools which are specialized to
22
2.4 FPGA Design Tools and Methods
suit development of DSP like systems, they are of course suitable for other
design purpose tools as well. One tool which has to be mentioned here
is Simulink (Simulink is an extensive plug-in tool for Matlab), Simulink is
based on the idea of DFGs and is hence very well suited for development of
DSP and automatic control systems. Since Simulink is a tool which already
is very well established within the technical computing and DSP commu-
nity and extensively used for other purposes than FPGA development many
of the large FPGA manufactures have made plug-in versions of their tool-
chain adapted for use in Simulink, enabling hardware design within the well
known and easy to use Simulink environment. Besides Simulink there are
other tools which are based on the DFG principle which are specialized in
or adapted to DSP design for FPGAs.
Using FPGAs for DSPs or other similar technical computing applications
has a lot of nice features regarding for example speed, jitter and accuracy.
One distinct feature with DSP like implementations in FPGAs is the non-
fixed word-length of the internal number representation, something that can
be a strength if handled correctly and a barrier of implementation if not.
A DSP is normally a processor based device and has hence fixed internal
word-length as processors do. When implementing DSP-like applications in
an FPGA however this limitation of the internal number representation no
longer exist It is possible for the designer to decide how many bits to use for
internal number representation in each step of the algorithm. There is an op-
timal internal number representation for each step of a given algorithm, this
optimal representation will give the system best accuracy and noise reduc-
tion, even more accuracy than possible with a fixed word-length DSP. Those
word-lengths can be found through-out the design, it is however difficult
to find them, this is in fact an NP-hard optimisation problem. [Cantin et al.,
2002] has written a survey of ways to automate the search for the optimal in-
ternal number representation and Todman et al. also discuss this subject, not
all DFG based FPGA development tools support automated approaches on
the word-length optimization problem. For example the Simulink based tool
for Xilinx devices does not, as stated by Todman et al. and as experienced
by the author and described in Chapter 4. Algorithmic settings must in the
Xilinx case be selected by the designer in every calculation step, making
work in this environment much more difficult for the designer. It is strongly
recommended that a tool with automated word-length optimization is used
since it makes implementation significantly easier and more efficient, espe-
cially if the designer is less experienced with working in the FPGA domain.
23
Chapter 2. The Field Programmable Gate Array (FPGA)
Since FPGAs have been around for quite some time there exists a variety
of scientific results on FPGA applications and design. This brief section is
intended as a flavor (not a complete description) of applications and areas
where reconfigurable computing technology has been applied successfully,
in order to highlight the potential power of reconfigurable hardware. En-
hancing feedback control system performance is, being the topic of this the-
sis, devoted a complete chapter (Chapter 3) and is hence not accounted for
in this section.
A large application area for these systems is applications treating images
or image streams (video). A good reason for using reconfigurable hardware
in this kind of applications is that they are extremely computationally ex-
pensive. Heavy computations combined with the fact that many tasks have
to be performed on-line puts very high demands on computational power
of such systems. Examples of results in this area are [Djemal et al., 2005],
[Jörg et al., 2004] and [Tao et al., 2005] who all have implemented different
FPGA or mixed FPGA processor systems in the domain.
Another very interesting application area is FPGA based super comput-
ers, meaning computers consisting of one or many FPGAs connected to-
gether in a matrix. The design within the FPGAs is totally customized to
one specific calculation or simulation task and the FPGAs are able to, in
a very rapid manner, solve the special problem which they are designed
for. The ‘secret’ is of course heavy parallelization and pipelineing achiev-
ing outstanding performance and even price/performance. Very interest-
ing results are published by among others [Jones et al., 2006] and [Belletti
et al., 2006]. Such computers clusters are emerging as a serious competition
to traditional processor based super computing clusters. The possibility also
exists to make systems with one or more FPGAs to accelerate frequent or in-
tensive tasks in a normal PC.
Different types of DSP applications are also common. Implementing DSPs
and DSP-like systems in FPGAs are a very promising idea which is covered
in an survey by [Tessier and W., 2000].
This chapter has covered the FPGA and reconfigurable hardware technol-
ogy. Strengths, issues, design considerations and design tools have been dis-
cussed. The chapter started with a brief history about the FPGA which was
invented by Ross Freeman in the mid 1980s and originating from similar
devices such as the CPLD and PAL. An FPGA is a reconfigurable hardware
device and works in the same manner as any digital/electric circuit. Com-
24
2.6 Chapter Summary
25
Chapter 2. The Field Programmable Gate Array (FPGA)
26
3
FPGAs in Feedback Control
Applications
3.1 Introduction
Very promising results are shown applying FPGAs in the field of automatic
control, as a platform for implementing automatic-control systems. Results
are emerging dealing specifically with implementation of different controllers
using FPGAs as well as general ideas regarding implementation of control
systems using FPGAs, [Monmasson and Cirstea, 2007] deals with design
of industrial control systems using FPGA techniques and also very briefly
compares it with control implementation using micro-controllers. Further-
more extensive work has been carried out by many different authors ad-
dressing the task of implementing well-known control algorithms in the
new FPGA environment, evaluating methods, gains and drawbacks in do-
ing so. An FPGA has properties which in many ways makes it the ideal com-
ponent for control system implementation, some of them are mentioned in
Monmasson and Cirstea. Three main reasons can be identified as particular
strengths of FPGAs for feedback-control implementation;
The main benefit using FPGAs is the enormous increase in speed com-
pared to conventional techniques, Figure 3.1, from Monmasson and Cirstea,
illustrates a typical situation using FPGA for control compared to either DSP
27
Chapter 3. FPGAs in Feedback Control Applications
28
3.2 Implementation of Digital Controllers
29
Chapter 3. FPGAs in Feedback Control Applications
• Control-system sampling-speed
• Parameter conditioning
30
3.2 Implementation of Digital Controllers
Starting from the top it is important that the bandwidth of the controller
is high enough to guarantee stability in the closed-loop system. The sam-
pling speed must be selected so that the desired controller bandwidth can
be maintained (in the range of 10-30 times the bandwidth of the closed-loop
system). The limit of controller sampling speed is in many cases the cal-
culation capacity of the device used for implementation. If the sampling-
speed is much higher than the bandwidth of the controller, special consid-
erations have to be made to avoid for example noise issues. Maintaining
controller stability when using limited-word-length arithmetics (which al-
ways is done in the real-world case) is another issue which needs to be han-
dled to guarantee performance of the closed-loop system. Another thing to
keep in mind implementing digital controllers is that it is important to use
well-conditioned parameters, avoiding excessively large or small parame-
ters especially in combination with ‘normal’ sized ones. There are mainly
two reasons for avoiding ill-conditioned parameters, over/under-flow in
the algorithms and noise sensitivity.
31
Chapter 3. FPGAs in Feedback Control Applications
32
3.3 Word-length Optimization, Internal Number. . .
mization automatically are for example shown in Cantin et al. and Cantin
et al., although mainly intended for the DSP environment these results can
be translated to FPGA based applications. Normally the integer part word-
length of the fixed-point representation is decided based on the dynamic
range needed, to decide the fractional word-length however takes more con-
sideration. Three different approaches can be used to select the fractional
word-length, the fractional word-length can be decided based on analysis
of DFGs, it can be decided based partly on analytical methods and partly
based on simulations and it can be selected based on methods relying only
on simulations. Cantin et al. used word-length determination based on sim-
ulations. An algorithm was first simulated using floating-point number-
representation. Fractional word-length was then decided based on a min-
imization procedure, a fixed-point simulation was run and the outcome
evaluated using a error function. The result from the evaluation function
was used by the minimization procedure, updating the decision on which
fractional-length to use, nine different minimization procedures were tested.
The process of deciding the fractional word-length, performing the fixed-
point simulation and evaluation of the outcome was iterated until system
specifications were met. The criterion for stopping the iteration could either
be expressed in an error function value or as a limit on the difference be-
tween the fixed-point and floating-point simulation. Cantin et al. evaluates
these heuristics on twelve different algorithms commonly used for digital
signal processing. For the purpose nine different minimization procedures
were used. Being a simulation and evaluation-function based method the
suggested heuristics shares one drawback with other cost-function based
methods, the sensitivity for a well formulated cost/minimization-function.
Cost-function based heuristics (for example neural-networks or genetic al-
gorithms) are generally not able to perform better optimizations than the
evaluation function enables them to do. Other drawbacks with the simu-
lation based methodology as described later by Cantin et al. is that this
method does not guarantee that no overflow will occur or that the speci-
fication will be full filled for any other case than the one reflected by the
‘test-bench’ used. The reason is that the test-bench in many cases can not
reflect all possible inputs to the system encountered during the complete
lifetime. Performing simulations using a test-bench covering the complete
possible set of inputs would be too time consuming. There are a few ways
to improve the performance of the test-bench in order to make it more likely
that most of the input dynamics are taken into account during the simula-
tions. Pseudo-random inputs can be used in the test-bench. In some cases
it might be possible to calculate the mean and standard deviation of each
operand and based on the results add bits to the data-path to avoid possi-
ble overflow. It is possible to increase the constraint more than necessary to
gain some ‘margin’ for overflow. And one way could be to perform ‘cascade
33
Chapter 3. FPGAs in Feedback Control Applications
y = Au + Bu′ , A = B (3.1)
B
u = Au + ( 1 − q −1 ) u (3.2)
∆
34
3.4 Over-Sampling and Limited Precision, Digital Control using the δ-transform
35
Chapter 3. FPGAs in Feedback Control Applications
y = Au + Bδu (3.3)
36
3.4 Over-Sampling and Limited Precision, Digital Control using the δ-transform
q = 1 + ∆δ (3.5)
Which are then the benefits from using the δ-transform/operator? One
obvious benefit is that δ converges towards a continuous time derivative,
d
dt , as sampling-time, ∆, is decreased, as ∆ → 0, enabling a ‘smooth tran-
sition’ between continuous and discrete time as δ is a discrete-time Euler-
estimate of a derivative. The discrete-time sampled system hence, using the
δ-transform, converges to the underlying continuous-time system as ∆ →
0. Many issues related to highly over-sampled control-systems are solved
through this fact. The higher the sample rate, the more ‘like continuous-
time’ the corresponding discrete-time system representation will be. One
easy way to explain the reason for this is that δ is a version of q which is
‘weighted’ against sampling-time and hence is equally large and precise re-
gardless of sampling time.
d
Related to the fact that δ converges towards dt is the fact that controller
stability increases with sampling speed. Closed-loop pole assignment for
example will, according to Goodwin et al., be better conditioned using δ.
Using the shift-operator and z-transform the poles and zeros will converge
to the (unstable) point 1 − 0j as ∆ → 0. However using δ the poles and zeros
37
Chapter 3. FPGAs in Feedback Control Applications
38
3.5 Parallelization and Algorithm Reformulation
performs well in practise. For example Goodall and Donoghue have imple-
mented a digital filter (low-pass) using the δ-transform/operator. Goodall
and Donoghue state that when using the common z-transform and shift op-
erator the numerical problems start as noted when sampling at ten times
the filter cut-off frequency and they become severe when sampling at about
100 times the filter frequency. Using the δ-operator Goodall and Donoghue
were however able to successfully implement a filter which samples at a rate
32000 times the cut-off frequency of the filter. [Chen et al., 2000b] use the
heuristics developed in Wu et al. and deploys it on a PID controller com-
paring a δ approach with a shift-operator approach for a span of different
sampling rates. Chen et al. find that the δ implementation in most cases,
as expected, needs less bits for the number representation maintaining the
same performance and it is at the same time superior to the shift-based im-
plementation at high sampling frequencies.
Which are then the drawbacks with the δ-transform/operator compared
to the shift-operator. One obvious drawback is that a δ implementation is a
bit more difficult to implement, the shift-operator is very simple to imple-
ment (just a delay of one sample and a subtraction). Consequently there is,
as noted by Goodwin et al., a computational overhead coming from using
the δ-operator instead of the shift operator. This overhead is by Goodwin et
al. regarded as small compared to the total number of computations needed
in these contexts. The major drawback of the δ approach would probably
be the fact that the shift-operator is well established, commonly used in dis-
crete time implementations. The δ-operator is not. Maybe the need for high
frequency performance will renew the interest in the δ-transform in the fu-
ture.
It is, as the reader for sure has understood by now, the parallelization which
makes the FPGA truly more powerful than a micro-controller. If parallel
structures are not utilised the great gain in performance is not obtained ei-
ther. This is important to keep in mind when developing algorithms con-
sidered for FPGA implementation, for control as well as for other purposes.
As an example Equation 3.2 can, according to Figure 3.2, be implemented in
two ways, sequentially as described by I or parallel as described by II. It is
obvious even in this small example that the parallel implementation in II is
much faster than the sequential one in I and even more so since multiplica-
tion in many cases is more demanding than addition. This effect gets more
pronounced if the problem is larger and contains more parallel branches.
Not all problems can be parallelized. If for example B would depend on
Au(t), B = f ( Au(t)), then B(u(t) − u(t − 1)) can not be calculated before
39
Chapter 3. FPGAs in Feedback Control Applications
the calculation of Au(t) is finished and the complete equation would have
to be calculated sequentially reducing the maximum possible performance
(∆ is here assumed to be one). It is important to exploit such parallelism
when found in algorithms. Studying for example Figure 4.2, which describes
the DFG implementation of the algorithm performing the high-bandwidth
heat-release analysis described in Chapter 4, it is found that it contains two
different calculation paths which are summed together before obtaining the
final result (this is the case even though it is not completely obvious from
the figure). The high-speed heat-release analysis hence uses a parallel struc-
ture, similar to the one described by the example, in order to obtain its high
performance.
Parallelization is touched earlier in 2.4, more from an programming and
FPGA design point of view. Using high-level FPGA design languages paral-
lel structures will be extracted implicitly with the risk of missing structures
existing on the algorithm level. The designer has to make sure that algo-
rithm paths which are truly parallel are implemented in a way so that they
end up as parallel paths on the FPGA. How to do this is difficult to state
generally since it would depend greatly on which tool is used. It would for
example come ‘almost automatically’ when implementing algorithms using
Simulink since the DFG structure of Simulink promotes parallel calculation
paths. Using a programming-language based tool, for example Handel-C
or VHDL, it would probably require some more attention since the imple-
mentation format is more sequential in its nature as opposed to DFG based
tools. In either case the designer should be aware of which parallel paths
that exist in the algorithm and if it is desirable to implement them parallel
or sequentially.
It is not in every case desirable to use the ‘full-parallelism’ available in an
algorithm for a number of different reasons. Parallelization is in some cases
a trade-off between speed, chip-area and power-consumption as indicated
by for example [Zhao et al., 2005], attempting PID control (which also is de-
scribed subsequently in this chapter) using different degrees of paralleliza-
tion of the algorithm. For a single-channel loop both a fully parallel design
and a design which only uses one adder and one multiplier, performing all
the calculations needed in a time-multiplexed manner is attempted. Using
multiple-channels Zhao et al. attempts both channel-level serial design (all
loops share one controller), multi-channel serial (all loops share one con-
troller which in turn share only one adder and one multiplier) and a fully
parallel design. The objective is of course to save area and power. Zhao et
al. finds that due to the large over-head introduced by the control logics
performing ‘context-switching’ parallel designs are to prefer when imple-
menting a more moderate number of loops. Having a large number of loops
however some sort of serial design would save both power and chip-area at
the expense of speed, the results of Zhao et al. indicate the trade-off between
40
3.5 Parallelization and Algorithm Reformulation
41
Chapter 3. FPGAs in Feedback Control Applications
Figure 3.2 Flow diagrams describing two different possible ways to implement and
parallelize Equation 3.2. Method I is the fully serial one, the one that would be run
upon a processor. It is clearly the case that method II would compute faster given that
the different operations takes equal time since II is implemented parallel.
block), hence for example a large multiplication does not have to be time
and chip consuming by default.
With the intention to illustrate the potential power of FPGAs in control ap-
plications and to highlight some interesting implementation attempts, this
section briefly describes a few different examples of feedback-control algo-
rithms implemented on FPGAs. Three different control algorithms, using
different design considerations and methodology, implementation of PID
(Proportional-Integral-Derivative) control, implementation of MPC and im-
plementation of Neural Networks (NN) are presented. Typically controllers
which needs a lot of on-line computational power and/or which are in-
tended to be run at extra ordinary bandwidths are considered for FPGA
implementation.
PID controllers
PID controllers and variants of them (P, PI, and PD controllers) are the most
important controllers and it is the most commonly used control strategy. In
control problems where the open-loop system is at least reasonably linear
and where no feed-forward is needed PID controllers may often be good
enough. The possibility of implementing PID controllers using FPGAs has
been investigated for example by [Chen et al., 2000a] and as earlier men-
tioned by [Zhao et al., 2005]. The motivations for and gains with imple-
menting PID controllers using FPGAs vary. Generally speaking since PID
42
3.6 A Flavor of Application
43
Chapter 3. FPGAs in Feedback Control Applications
44
3.6 A Flavor of Application
45
Chapter 3. FPGAs in Feedback Control Applications
Input
Output
Figure 3.3 A typical outline of a Neural Network. The circles denotes the process-
ing elements and the arrows the interconnects. The number of layers, units and the
connection pattern can be varied giving the network different properties.
of computational units) are stored globally rather than in local RAM mem-
ory. The numeric precision needed for NNs are further discussed. Li et al.
cites [Holt and Hwang, 1991] who finds that NNs should be implemented
using at least 16-bit fixed point numbers to avoid decreased performance of
the NN. The results of Gironés et al. and Li et al. indicate that there are large
gains implementing NNs on FPGAs and it is safe to say that very interesting
results will continue to emerge in this field.
46
3.7 Chapter Summary
47
Chapter 3. FPGAs in Feedback Control Applications
48
3.7 Chapter Summary
within the data-path. Racing occurs when a sub-result belonging to one time
instance is used in calculations together with a sub-result belonging to a
completely different time instance, the corresponding result will then ‘not
belong in time’. Racing is less severe in control applications than in many
other applications due to continuity of the underlying system but should
never the less be strictly avoided.
Besides to consider algorithm parallelization it is important to avoid dif-
ficult operators such as trigonometry and exponentials implementing con-
trollers in an FPGA environment, as well as in a micro-controller environ-
ment. Having to implement difficult operators it is advisable to use some
method to approximate these functions in a way that saves chip area and
time, the CORDIC is one approach discussed.
Lastly three different application examples were presented and discussed
from the views of a number of different researchers. PID control, MPC con-
trol and Neural Networks all implemented in FPGAs were shown indicating
possibilities, powers and special considerations using FPGAs in practical
control applications.
49
Chapter 3. FPGAs in Feedback Control Applications
50
4
An FPGA Implemented Heat
Release Model
51
Chapter 4. An FPGA Implemented Heat Release Model
FPGA System
The main part of the setup is the experimental card fitted with the FPGA.
The card is a Commercial Off-The-Shelf (COTS) product supplied by ‘Avnet’,
the (rather long) name of the card is ‘Memec Xilinx Virtex-4 LX XC4VLX25-
SF363 LC Kit’. As understood the card holds a ‘Xilinx Virtex-4 LX XC4VLX25-
SF363 LC’ FPGA, which holds 24,192 logic cells, 168 Kb distributed RAM
memory and 448 user I/O ports. The board holds support circuitry to de-
velop a complete system. Maximum clock speed of the FPGA is 100 MHz
and the clock signal is supplied by an oscillator present on the board, al-
though there is also a possibility to provide a custom oscillator. Besides the
above mentioned equipment the card holds a number of peripheral devices;
16 Mb Serial Flash for FPGA configuration, 64 Mb DDR SRAM, on-board os-
cillators, ‘P160’ expansion header, JTAG programming/configuration port,
10/100 Ethernet, Alpha numeric LCD panel, RS232 port, LEDs, pushbut-
tons, DIL switches and General Purpose I/O pinout.
Desired FPGA configuration is either loaded directly onto the FPGA or
stored in a serial flash memory produced by Atmel. If the configuration is
loaded on to the serial flash it is automatically reloaded onto the FPGA on
power-up with the help of a CPLD. There exist of course other solutions for
the FPGA re configuration that might be more suitable in automotive ap-
plications, this approach is however flexible in a development environment.
Configuration both of the serial flash and directly of the FPGA are carried
out through the JTAG interface with the help of a Xilinx ‘Parallel Cable 4’.
Not included on the basic FPGA board is the ADC and DAC converters.
To gain access to the analogue world, a ‘bolt-on’ circuit board that fits in the
‘P160’ expansion header was used. This board is, as the FPGA board sup-
plied by ‘Memec/Avnet’ and is named ‘160-Analogue-Kit’. The board fea-
tures dual AD and DA channels. Both AD and DA converters are made by
52
4.1 Experimental Setup
Design Tools
As briefly mentioned earlier the design of the FPGA HR algorithm is car-
ried out in MATLAB/Simulink with the help of SGDSP. SGDSP contains a
number of Simulink blocks that are already implemented in VHDL, and us-
ing these blocks it is possible to generate VHDL from a Simulink diagram.
FPGA layout with the help of Simulink in DSP applications is discussed
by [Todman et al., 2005]. Please note that it is not possible to implement
‘standard’ Simulink blocks in the FPGA, it is necessary to possess a VHDL
implementation of the blocks to implement (a number of such blocks comes
with SGDSP). This is somewhat limiting. When running the ‘hardware co-
simulation’ (compare Hardware-In-the-Loop simulation ‘HIL’) during the
debug process, it is however possible to implement ‘standard’ Simulink sys-
tems on the PC communicating data with the FPGA through the JTAG in-
terface, this is a handy feature during the debugging process. Note that it
is necessary to possess a copy of the Xilinx ISE design suite in order to use
SGDSP since SGDSP uses the underlying ISE tools to generate the design
files. After co-simulation of the system, generic VHDL files are created from
Simulink, processed by the relevant FPGA design tools and downloaded to
the serial flash. When the design finally resides on the serial flash the FPGA
system is ‘stand alone’ from the computer.
Test Environment
Desktop tests were carried out during the development. The ‘interface’ to
the simulated/real engine consists of three signals, Crank Angle Degree
Pulses (CADP), Top Dead Center Pulses (TDCP) and analogue cylinder pres-
sure Pcyl . Current engine position is assumed to be measured with 0.2 Crank
Angle Degree (CAD) accuracy, the engine hence produces 5 CADP every
physical CAD. Besides CADP the angle sensor is assumed to give one TDCP
53
Chapter 4. An FPGA Implemented Heat Release Model
ncy
Simulated
engine
Oscilloscope
Signal
conditioning
Figure 4.1 FPGA experimental system overview, from [Wilhelmsson et al., 2006].
every time the engine has revolved two complete revolutions. Figure 4.1
provides an overview of the experimental setup, this engine ‘interface’ con-
curs with the setups in [Olsson et al., 2001], [Bengtsson et al., 2004] and
[Bengtsson et al., 2006].
During the development and testing Pcyl was simulated by recorded
cylinder pressure traces, both a motored and a fired trace were recorded. The
basis for Pcyl are pressure traces recorded from the 12 l Scania engine used
by Olsson et al., geometric data of this engine is noted in Table 4.1. A ‘in
house’ developed device simulating CADP, TDCP and Pcyl synchronously
at an engine speed of 1200 rpm was used for system tests during the de-
velopment. Pcyl was simulated with a vertical resolution of 8 bit, horizontal
resolution was 720 samples, that is one sample each CAD. DA conversion
was carried out with the help of a R/2R ladder and the output of the device
was buffered. The original pressure curve was somewhat distorted due to
the limitations of the engine simulator.
The design that was implemented in the FPGA can be viewed as a DSP
design, no processor core was present in the system. It would however of
course be possible to implement the HR algorithm on the reconfigurable
fabric of a mixed processor/hardware system, see Chapter 2 for properties
of a mixed system. The DSP design approach was selected due to the relative
simplicity of the calculations and the system. If the system is expanded to a
complete engine control system a processor core might be added.
54
4.2 FPGA Layout
Algorithm
A net HR (Qnet HR ) calculation was implemented in the FPGA, that is the HR
calculation disregards heat transfer losses and crevice losses. Heat trans-
fer losses are caused by convective energy loss to the combustion chamber
walls. Crevice losses are caused by trapping fuel-air mixture in the crevices
between the piston and the cylinder wall, thus avoiding combustion. The
reason for neglecting crevice and heat transfer losses in this work was to
somewhat simplify the implementation. Since [Bengtsson et al., 2004] finds
that Qnet
HR is sufficient for feedback purposes this simplification is regarded
as legitimate.
The calculation of Qnet
HR is carried out in a non-conventional manner. The
conventional way to calculate Qnet HR is through the integration of Equation 1.1
as described by [Gatowski et al., 1984]. For signal processing applications
it is however inconvenient to include the pressure derivative in the calcu-
lation since the process of differentiating a measured signal infers severe
noise issues, especially in combination with a very high ‘over-sampling’
rate. Instead of using Equation 1.1 it is possible to calculate Qnet HR through
Equation 4.5. Equation 4.5 origins from the conservation of energy and is
motivated through Equation 4.1-4.4. This is a promising optional method to
calculate the HR are showed in [Tunestål, 2000].
dU = dQ − dW
dU = nCv dT =⇒ nCv dT = dQ − dW =⇒ dQ = nCv dT + pdV (4.1)
dW = pdV
1
pV = nRT =⇒ d( pV ) = dT (4.2)
nR
R nR (4.2) 1
Cv = =⇒ nCv dT = dT =⇒ nCv dT = d( pV ) (4.3)
γ−1 γ−1 γ−1
1
dQ = d( pV ) + pdV (4.4)
γ−1
Z θ Z θ
1
Q= d( pV ) + pdV =
γ−1 θstart θstart
θZ
1 dV
= ( p(θ )V (θ ) − p(θstart )V (θstart )) + p(θ ) dθ =
γ−1 θstart dθ
Z θ
1 dV 1
= p ( θ )V ( θ ) + p(θ ) dθ − ( p(θstart )V (θstart )) (4.5)
γ−1 θ dθ γ−1
| {z start } | {z }
Calculated on-line Estimated constant, added off-line
55
Chapter 4. An FPGA Implemented Heat Release Model
Implementation
Fixed point arithmetics was used throughout the implementation of the HR
calculation although no automatic word-length determination was used (or
available in Simulink). To avoid racing-phenomena the different internal
computational branches were synchronized by the addition of unit-delays
and Simulink-specific synchronization blocks in the data-path. Keeping Eq-
uation 4.5 in mind, two multiply operations, p(θ )V (θ ) and p(θ ) dV dθ , were
computed in parallel within the FPGA. The integration (summation) acting
on p(θ ) dV
dθ was by necessity computed subsequently and p ( θ )V ( θ ) had to be
delayed one sample to make up for the time it takes to update the summa-
tion, all to avoid racing. Finally, the two parts of Equation 4.5 are added to
obtain the part of the result which is calculated on-line.
When Equation 4.5 was implemented the parts of the equation that were
known in advance were not calculated on-line in order to simplify the equa-
tion as much as possible, thus gaining speed. Instead they were mapped as
a function of current engine CAD in the distributed RAM of the FPGA, this
goes for V and dV. As basis for the volume maps the geometry listed in Ta-
ble 4.1 was used (since this engine is the basis for the pressure traces used in
the test environment).
The time resolution is also of high algorithmic interest and it has to be
noted. The described setup had the properties of an asynchronous system
since the engine delivers CADP:s at one ‘clock speed’ (which varies with the
engine speed) and the FPGA board ran at a totally different one, meaning
that the FPGA clock was non-synchronous with the CADP. This is an uncon-
ventional approach in an engine control system. The described calculation
of Qnet
HR demands, as understood from Equation 4.5, some synchronization
between the calculation of QnetHR and the engine position (in order to retrieve
the correct V and dV). This synchronization was provided through a CADP
counter, a simple incremental counter which was reset on the rising edge of
TDCP. Overrun detection was also provided on this CADP counter in order
to detect issues with the CADP and TDCP. The output of the CADP counter
indicated the current position of the engine and it was used as index for the
tabulated values of V and dV which were kept in the RAM memory. In this
manner the FPGA system had all the information needed for the calculation
of Qnet
HR without synchronizing FPGA clock pulses with the CADP.
The clock-speed of the AD converter was, as previously noted 50 MHz,
this was hence the sampling rate of Pcyl . This is by far a higher sampling
rate than the update speed of V and dV, meaning that a number of Qnet HR
samples were calculated ‘in vain’. The outcome was a system that calcu-
lates Qnet
HR based on the same P, V and dV values several times, a system
with very high rate of over-sampling. The parallel nature of the FPGA how-
ever still made this the preferred way to perform the design. The FPGA
56
4.2 FPGA Layout
fpt dbl
Q
Data P
PdV
dV CADCNT
ADC OF PV PV Qout In1 Out1 Data
V
Q Qin
ADC2 Multiplication
cumSum PdV sX->u1
Windowing DAC1
PV+cumSum PdV
PdV
CAD
Vout
cumSum PdV
GPIO_0 TDC dVout
nmm CADCNTout
OFerror
CADout
GPIO_1 CAD
nmm TDCout
Engine syc
k =0
In1
In2
k =14
In3
In4
a
clr Configurable Subsystem System
xlrelational
a=b
Manager Generator
PushButtons b z-1
nmm ErrHandle
Figure 4.2 The DFG implementing the HR, from [Wilhelmsson et al., 2006]. The figure
describes the ‘top-level’ of the implemented algorithm/system, it is important to note
that each block at this level contains a lot of logics. The two different parallel branches
making up the computation are not obvious from the top-view.
Number of Cylinders 6
Swept Volume 11705 cm3
Compression Ratio 18 : 1
Bore 127 mm
Stroke 154 mm
Connection Rod 255 mm
simply outputs QnetHR samples at 50 MHz no matter what, meaning that the
inferred latency, counted in number of FPGA cycles was constant regard-
less of the engine speed. The commonly used method to synchronize the
engine and the control electronics by clocking the control electronics from
engine driven pulses (i.e., CADP) was not used here since it would totally
destroy the largest benefit of using the FPGA, i.e. low computational latency.
It was not at all necessary to synchronize the clock of the FPGA with the
CADP since it was possible to maintain sync with the engine with help of the
CADP counter. Disregarding the synchronous thinking between the engine
and FPGA board enables very low latencies without any major drawback.
57
Chapter 4. An FPGA Implemented Heat Release Model
58
4.3 Experimental Results
6 Measured emulated P
cyl
x 10
8
6
Pcyl [Pa]
0
400 500 600 700 800 900 1000 1100
CAD [°]
Corresponding Q measured from FPGA
1500
1000
Q [J]
500
−500
400 500 600 700 800 900 1000 1100
CAD [°]
Figure 4.3 Output from the FPGA system when the ‘combustion’ is suddenly
switched on, showing true ‘in-cycle’ performance. From [Wilhelmsson et al., 2006].
ber of disregarded cycles are in the range of 20-30 cycles depending on the
‘mood’ of the simulated engine. Figure 4.4 shows all the sampled cycles that
are non damaged, as understood from the figure most of the calculated cy-
cles holds a high enough signal quality to use in a feedback control loop.
Figure 4.5 shows the average of the cycles shown in Figure 4.4. It also shows
the ‘corrected’ values calculated off-line by the PC and Matlab. As under-
stood from the figure the FPGA implemented algorithm is able to calculate
Qnet
HR accurately enough. If the FPGA output and off-line Matlab calculated
Qnet net
HR are compared to a Q HR calculated from Equation 1.1 consistency is
net
again found. Q HR according to Equation 1.1, is however not shown in order
not to blur the figure.
59
Chapter 4. An FPGA Implemented Heat Release Model
6
[Pa]
4
cyl
P
0
320 330 340 350 360 370 380 390 400
CAD [°]
Corresponding Q measured from FPGA
2000
1500
1000
Q [J]
500
−500
320 330 340 350 360 370 380 390 400
CAD [°]
Figure 4.4 Non average results corresponding to figure 4.5, from [Wilhelmsson et al.,
2006].
4.4 Discussion
The results in Figure 4.3 - Figure 4.5 show that implementation of Equa-
tion 4.5 was successful. As previously noted some cycles are removed from
the results before presentation. The intention of the final system is of course
that every cycle will be calculated perfectly, this is also achievable, better
edge detection logics in combination with better quality of the position-
ing pulses will do the trick. The reason for the erroneous cycles are mainly
thought to be issues with the simulated engine. As it was difficult to find
a suitable signal simulator, the simulated engine had to be developed in
house, and even though it performs well on average some cycles are not
true to the real engine and it is these cycles that were removed. The cycles
were removed based on a derivative threshold of the measured Qnet HR . As
visible in Figure 4.4 some ‘bad’ cycles do however still persist (bad cycles
meaning cycles that have a sudden ‘jump’ in the middle of the signal).
Besides the issue with ‘bad cycles’ there appears to be an offset prob-
60
4.4 Discussion
0
320 330 340 360 350
370 380 390 400
CAD [°]
Corresponding average Q measured from FPGA and off−line calculated by PC
1500
PC QComb
1000 FPGA Q
Comb
PC Qno Comb
Q [J]
500
FPGA Q
no Comb
0
−500
320 330 340 350 360 370 380 390 400
CAD [°]
Figure 4.5 Average output from the FPGA system compared to the corresponding
values corrected in the PC, from [Wilhelmsson et al., 2006].
lem, in Figure 4.4 there appears to be different bias in the different cycles of
Qnet
HR . This offset problem is explained by the nature of the AD converter con-
nected to the FPGA. The AD converter was purchased as an expansion card
suitable for the expansion header on the FPGA board, the case was however
that the input circuitry on the AD converter card was intended for usage
in very high frequency systems and the signal paths to the AD converter
hence blocked the very low frequency cylinder pressure signal. The input
circuitry hence had to be replaced by an ‘in house’ alternative which unfor-
tunately suffered from a slight problem with the input bias which explains
the ‘cycle-to-cycle’ variation of Qnet
HR in Figure 4.4.
The two noted issues are unfortunate and an effort will be made to cor-
rect them for future versions of the system. When the erroneous data was
removed as described and the remaining cycles were averaged Figure 4.5
emerged. Figure 4.5 shows that the FPGA system despite the noted issues
on average performs well. The difference between Qnet HR calculated by the
PC off-line and QnetHR calculated by the FPGA is not large, at least not in the
case with ‘combustion’. QnetHR in the ‘motored’ case is less consistent between
61
Chapter 4. An FPGA Implemented Heat Release Model
the PC calculations and the FPGA, the explanation for this is thought to be
the bias issues on the input of the AD converter. This bias issue will strike
differently depending on the signal level. Since the signal level is lower in
the ‘motored’ case the error will also be larger.
The difference between the corrected Qnet net
HR and the FPGA Q HR is mainly
thought to be explained by the above noted problem. The fact that fixed
point numbers had to be used in the implementation is not thought to ac-
count for any large error in the signal as motivated by Table 4.2. In the table
it is clearly visible that despite the limited input word-length of only 12 bit
the resolution (known by the value of the Least Significant Bit (LSB)) is, by
far, enough (Plsb is calculated on a 60 bar Pmax assumption, if Pmax = 200 bar
are used Plsb ≈ 0.05 bar).
Even though the resolution is regarded as accurate enough the FPGA
environment still caused some problems during the implementation phase.
System generator DSP is a tool that should be used with care; both the FPGA
internal number representation and the internal timing of the FPGA are very
difficult to manage. The transparency of the tool is simply not good enough
to enable the designer to design the FPGA layout in a controlled manner.
Many issues had to be solved ‘ad-hoc’ causing delays in the design work,
FPGA design is very sensitive to the available tools regardless of its appli-
cation.
62
5
FPGA Based Rapid
Prototype System –
a Suggestion
63
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
64
5.2 The Setup
in the figure would be present in most setups in one form or another. The
center of the setup is of course the actual engine, which also is the actual
plant for the control engineer. The engine generates energy during opera-
tion, this energy needs to be taken care of, a device capable of maintaining
the rotational speed is hence necessary, i.e. an engine dynamometer. In this
case the dynamometer consists of an electric motor in combination with con-
trol electronics. The EDC system would need the capability to demand an
engine speed setpoint from the dynamometer in order to carry out tran-
sient identification and validation experiments. Preferably control data for
the dynamometer would be transferred through MODBUS to the control
electronics of the electric motor, RS-485 will be used as the physical layer for
the MODBUS communication.
In each cylinder of the engine a piezoelectric cylinder pressure trans-
ducer will be present. The pressure transducers would be connected to charge
amplifiers which convert the electronic charges originating from the trans-
ducers to voltages. Besides analog outputs for pressure, the charge ampli-
fiers have the possibility of control related communication. In reality how-
ever the control parameters of the charge amplifier is very seldom changed,
and this communication path will hence not be implemented. Each analog
output of the charge amplifier is connected to two different analogue I/O
inputs of the EDC.
A vast variety of other devices might also be connected to the engine
setup to perform different measurements, for example thermocouples, air/-
fuel ratio sensor(s), emission measurement devices, non-cylinder pressure
transducers and the crank angle counter (angular positions sensor). These
devices are typically sampled by the EDC (apart from the crank angle counter)
either by an analogue I/O device (preferable) or in some cases by digital
communication (GPIB, RS-XXX, or ethernet). The crank angle counter com-
municates through parallel digital channels physically carried on fiber op-
tics. Based on the inputs from the sensors the control engineer wants to per-
form two tasks:
65
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
The main idea with the described system is to have the possibility of two
control loops with significantly different bandwidths as indicated in Fig-
ure 5.1. Color marking distinguishes the two different loops in the figure,
the loop marked in black would be the high bandwidth loop carrying out
control tasks with high bandwidth requirements e.g. injection control. It can
also assist the low bandwidth loop (marked in grey) with the cycle-to-cycle
control of, for example, engine load. The high bandwidth loop, indicated
in Figure 5.2, is found to consist of; the engine, cylinder pressure sensor
(CPS), charge amplifier (CAMP), high frequency AD converter (HFADC),
the FPGA board and last but not least the injection system (communication
protocol between the components vary). The low bandwidth loop, noted in
grey in Figure 5.1 and still with Figure 5.2 in mind, would consist of; the en-
gine, the cylinder CPS, the CAMP, the framed ADC (FADC), the x86-PC and
the FPGA. A FADC is a ADC which stores a defined number of samples,
one frame, in local memory before handling the complete frame at the same
time to the PC. Also note that the FPGA board is the master controller of the
injection system and the output of the low bandwidth combustion control
loop hence has to pass through it. Pressure sampling in the high bandwidth
loop is asynchronous to the engine revolution which means that some syn-
chronisation algorithm is needed in order to implement the injection control
and other algorithms based on the engine crank angle. The low bandwidth
loop on the other hand is clocked synchronously with the engine revolutions
and synchronisation is hence built-in.
The high bandwidth loop is complemented by the x86-PC running xPC-
Target environment. Implementation of controllers in the high bandwidth
loop is time consuming but controller implementation in xPC target is not.
The existence of the PC hence enables the designer to, in a very rapid man-
ner, implement controllers with the support of a large amount of plug in
modules for I/O. The xPC-Target environment will be used for implemen-
tation of user interface, implementation of the low-bandwidth control of the
66
5.4 Loop Bandwidth
Figure 5.1 Overview of the two different loops intended to have two significantly
different bandwidths, from [Wilhelmsson et al., 2007]. The loop consisting of black
arrows will have a high bandwidth but be less flexible consisting of an FPGA. The
loop consisting of grey arrows is intended to be more flexible consisting of a PC being
configured in Simulink. Speed performance will however be decreased using a PC and
Simulink.
The bandwidth of the two loops in absolute terms would of course be de-
termined by the slowest component included in each loop. To determine
67
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
Figure 5.2 Overview of the components within the suggested control system, from
[Wilhelmsson et al., 2007].
the bandwidth of the two different loops the bandwidth of each component
hence must be found, starting with the high bandwidth loop.
The clock frequency of the FPGA would be at least 100MHz depending
on device selection, FPGA clock would hence not be an issue. Clock fre-
quency of the HFADC would, again depending on device, range between a
few kHz up to 100MHz. As input the HFADC takes the output signal from
the CAMP which in turn takes the output from the CPS. CAMP cut-off fre-
quency would be in the range of 200kHz and CPS natural frequency in the
range of 40 − 200kHz all according to manufacturer specifications. The last
link in the HF loop is represented by the fuel injectors. Work published by
[M. Oki et al., 2006] indicates the available bandwidth of diesel fuel injec-
tors. It is found that the time it takes the injector to lift the nozzle needle to
half, from the instance the command signal is given, is 200µs and f −3dB is
hence ≈ 5kHz.
Appropriate loop bandwidth can be decided in many different ways, if
the Nyquist criterion is used the sampling frequency of the HFADC would
be decided to 2 ∗ 200kHz = 400kHz with the cut-off frequency of the CPS
in mind, or 2 ∗ 5kHz = 10kHz based on injector bandwidth. However, since
68
5.4 Loop Bandwidth
this system is intended for control purposes another sample rate criterion
should be used ensuring control system performance. [Åström and Witten-
mark, 1997] suggests a sampling frequency between 10 to 30 times the loop
bandwidth. Loop bandwidth is limited to the injector bandwidth of 5kHz
and an appropriate minimum sampling/control frequency would hence be
50 − 150kHz, if all six cylinders together are sampled by the same ADC it
has to be able to sample at 6 ∗ 150kHz = 900kHz. For the high speed loop
the Nyquist frequency will consequently be 150/2 = 75kHz. A fairly high
loop bandwidth in combination with the fact that the FPGA clock frequency
is, compared to the sampling frequency, significantly higher enables large
amounts of calculations to be carried out between each CPS sample. For ex-
ample in order to implement complex controllers (MPC etc), with such high
bandwidth requirement, in multiple cylinders simultaneously the very high
throughput, parallelism and high clock speed of the FPGA is regarded as
essential and the use of the FPGA system is hence motivated. Preferably the
HFADC is operated synchronously with the FPGA clock. The FPGA should
drive the HFADCs and in this way traditional real-time and synchronisa-
tion issues are avoided. The performance of the FPGA board is the enabling
factor, letting the systems perform very complex calculations between each
sample, without violating the bandwidth of the loop.
The low bandwidth xPC target based loop shares some components with
the high bandwidth one, the CPS, CAMP, the FPGA and the injection sys-
tem. In the case of the low bandwidth loop the FADC would be clocked
by the crank shaft pulses, a method which can be regarded as the ‘stan-
dard’ method. The sampling frequency will hence depend on current engine
speed, making anti-aliasing filtering more difficult. For simplicity an anti-
aliasing filter with cut-off frequency decided by maximum engine speed
would be used. Maximum clock speed of the FADC is decided by the crank
angle sensor resolution and the maximum physical engine speed. Results
are published using different angular resolution. One pulse each CAD is
frequently used, in this case a resolution of five pulses each CAD as used by
among others [Olsson et al., 2001] and [Wilhelmsson et al., 2006] is preferred.
Maximum engine speed is selected to be 6000rpm and with five crank pulses
each physical CAD the crank pulses will arrive at a frequency of 180kHz ac-
cording to Equation 5.2, at maximum engine speed and frequencies up to
180/2 = 90kHz are resolvable according to the Nyquist criterion. Conse-
quently the crank pulses will arrive at a frequency of 24kHz at the mini-
mum engine speed of 800rpm (according to Equation 5.1) still using five
crank pulses each CAD, Nyquist frequency for minimum engine speed is
hence 12kHz. The desire is to be able to handle at least a 6 cylinder engine
at maximum engine speed of 6000rpm preferably with a time resolution of
five samples each CAD.
69
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
800 [n/min]
CAD
f min = ∗ 360 [CAD/n] ∗ 5 [cad−1 ] = 24 000 [ Hz] (5.1)
60 [s/min]
6000 [n/min]
CAD
f max = ∗ 360 [CAD/n] ∗ 5 [cad−1 ] = 180 000 [ Hz] (5.2)
60 [s/min]
The suggested electronic hardware setup is indicated in Figure 5.2, the sys-
tem is intended to be built around a PC (lower right in the figure). There are a
number of different communication interfaces which could be used between
the x86 computer and peripheral components, for example PCI, PC/104 or
ethernet. Which interface that is best suited for the application is mainly
a question which I/O devices that hold support for Simulink/xPC-target.
The support for framed sampling in xPC-Target is somewhat limited and
one has to choose the I/O device with this in mind. As for the FADC there
are mainly two suitable devices supported, either an analog I/O module
from ‘Diamond Systems’ named ‘Diamond-MM-32-AT’ or one from ‘United
Electronic Industries (UEI)’ named ‘PD2-MFS-2M/14’. The Diamond Sys-
tems device is a 16-bit one, using the PC/104 bus, the device holds framed
sampling support in xPC-target and is capable of a sample frequency of
200 000 sps. However with this sampling frequency it is possible to handle
an engine speed of 5556rpm in a 6 cylinder engine (as desired) only if a res-
olution of 1 CAD is used (see Equation 5.3). The Nyquist frequency would
then be ≈ 16700Hz at maximum engine speed (Equation 5.4).
200 000[s−1 ]
Diamond 6[]
nmax = ∗ 60[s/min] ≈ 5556 [n/min = rpm] (5.3)
360[n−1 ]
200 000[s−1 ]
6[]
f NDiamond = ≈ 16 667 [ Hz] (5.4)
2
The other option, the UEI device, is a 14-bit device using the PCI bus and
capable of 2 Msps. Using the UEI device it is possible to sample five times
each CAD for a six cylinder engine up to ≈ 11 000rpm according to Equa-
tion 5.5 or handling the engine speed criterion (6000rpm) for up to a ten
70
5.5 Suitable EDC Hardware
2M [s−1 ]
6[]
nUEI
max = ∗ 60[s/min] ≈ 11 111 [n/min = rpm] (5.5)
1800[n−1 ]
2M [s−1 ]
10[]
nUEI
max = ∗ 60[s/min] ≈ 6667 [n/min = rpm] (5.6)
1800[n−1 ]
Besides the I/O module connected to the PCI or PC/104 bus to work
with xPC-Target one more ADC will be present in the system, the HFADC
sampling values to the FPGA. That ADC will share the input of the FADC
in an analogue manner and will have a high specification, a data resolution
of 16bit and a maximum sample frequency of up to 25MHz is possible. Min-
imum sample frequency for this ADC is 150 ∗ 6kHz = 900kHz. A high spec
ADC furthermore provides capability for system expansion by addition of
high speed signals. The high speed ADC will not run on a higher clock
frequency than necessary. The selected ADC could preferably be LTC2203
from Linear Technology (other options from Linear in the sampling range
of 10 − 105Msps are LTC2207, LTC2206, LTC2205, LTC2204, LTC2203, or
LTC2202). A MUX and sample-and-hold circuit might be needed as well.
The outputs of the HFADC will be communicated in a parallel manner to
the digital I/O of an FPGA development board.
The FPGA development board present in the lower left of Figure 5.2 will
be the center of the system. Communications between the FPGA card and
the x86 PC will be carried out using Direct Memory Access (DMA), which
enables very high speed communication in a manner which is fairly simple
to implement. Thus the FPGA board will have to be connected to one of the
data buses of the PC. Devices suitable for this are for example the ‘Virtex-
5 LX110 PCI Development Board’ from Vmetro which can be connected to
the PCI bus or the ‘TS-104-3001’ from GE Fanuk Embedded Systems, which
handles the PC/104 bus.
71
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
72
5.7 Chapter Summary
73
Chapter 5. FPGA Based Rapid Prototype System – a Suggestion
74
6
Concluding Remarks
6.1 Summary
New combustion engine principles increase the demand of feed-back com-
bustion control, at the same time economical considerations currently en-
forces the usage of low-end control hardware limiting the implementation
possibilities. Significant development is simultaneously and continuously
carried out within the field of Field Programmable Gate Arrays (FPGAs). In
recent years FPGAs has developed, from being a device mainly used in to
implement grids of ‘glue-logic’ to something of a flexible ‘dream device’ in
cost and performance sensitive applications. It is not solely the development
of FPGA devices which has made the FPGA the promising implementation
platform it is. Development of software tool-sets and design methodologies
is as important as the development of the device as such.
FPGAs and FPGA design has been thoroughly discussed based on liter-
ature found on the topic covering a wide span of considerations. Architec-
tural consideration and corresponding pros and cons have been discussed,
both on the FPGA design level and FPGA hardware level, as well as differ-
ent design tools and design considerations.
Using FPGAs as implementation platform for controllers and feed-back
control is a rewarding topic. The literature in the field has been scouted and
a number of points especially important for FPGA implementation of con-
trol logic, such as word-length, parallelization and high-speed sampling is-
sues have been highlighted. A short survey of application examples from
the literature was presented.
Implementation of a heat-release algorithm within an FPGA has been
described. Combustion phasing, calculated from the heat-release, is consid-
ered as a key feed back variable for closed-loop combustion control. A suc-
cessful FPGA implementation of a reformulated but completely equivalent
75
Chapter 6. Concluding Remarks
76
6.2 Future Works
77
Chapter 6. Concluding Remarks
78
7
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84
A
Abbreviations
85
Appendix A. Abbreviations
86
B
Symbols
β Over-sampling rate
δ An operator and transform corresponding
∆ Sampling time
γ Specific Heat Ratio
θ Crank Angle
ADCclk ADC clock frequency
Cv Molar specific heat at constant volume
DACclk DAC clock frequency
f −3dB Cut-off frequency, bandwidth
CAD
f max Maximum crank angle pulse frequency
CAD
f min Minimum crank angle pulse frequency
fN Nyquist frequency
fs Sample frequency
FPGAclk FPGA clock frequency
X
nmax Maximum engine speed using hardware ‘X’
n Number of moles
Pcyl Cylinder pressure
Plsb Pressure resolution (value of LSB)
Pmax Maximum pressure
P, p Pressure
Qnet
HR Net heat released from combustion
Q Heat
q The shift-operator
R Universal gas constant
T Temperature
t Time
U Internal energy
W Mechanical work
V Volume
87
Appendix B. Symbols
88
ISRN LUTMDN/TMHP—07/7050—SE
Carl Wilhelmsson
ISSN 0282-1990
Carl Wilhelmsson