MINI PROJECT TITLE

Mini Project 1 A Report

Submitted in partial fulfillment of the requirement of University of Mumbai
For the Degree of
(Electronics & Telecommunication Engineering)

By

1) “Raj Ravi Upreti” “ID No: TU2F1920001”

Under the Guidance of

Prof. Rupali Shekokar

Department of Electronics and Telecommunications Engineering

TERNA ENGINEERING COLLEGE

Plot no.12, Sector-22, Opp. Nerul Railway station,

Phase-11, Nerul (w), Navi Mumbai 400706

UNIVERSITY OF MUMBAI
 TERNA ENGINEERING COLLEGE, NERUL,

NAVI MUMBAI
Department of Computer Engineering
Academic Year 2020-21

CERTIFICATE
This is to certify that the mini project 1 A entitles “Mini Project Title” is a bonafide work of

1) “Raj Ravi Upreti” “ID No: TU2F1920001”

submitted to the University of Mumbai in partial fulfillment of the requirement for the award
of the Bachelor of Engineering (Computer Engineering).

Guide Head of Department Principal

 Project Report Approval

This Mini Project 1 A Report – entitled “Mini Project Title” by following students is
approved for the degree of B.E. in "Electronics and Telecommunications Engineering".

Submitted by:

1) “Raj Ravi Upreti” “ID No: TU2F1920001”

Examiners Name & Signature:

1.---------------------------------------------------------

2.----------------------------------------------------------

Date: ---------------------------------

Place: ---------------------------------
 Declaration

We declare that this written submission represents our ideas in our own words and where others'
ideas or words have been included, we have adequately cited and referenced the original sources.
We also declare that we have adhered to all principles of academic honesty and integrity and have
not misrepresented or fabricated or falsified any idea/data/fact/source in our submission. We
understand that any violation of the above will be cause for disciplinary action by the Institute and
can also evoke penal action from the sources which have thus not been properly cited or from
whom proper permission has not been taken when needed.

“Raj Ravi Upreti” “ID No: TU2F1920001” ---------------------------

Date: _____________________
Place: _____________________
 Acknowledgement

We would like to express our sincere gratitude towards our guide Prof. Guide name, Mini Project
Coordinators Prof. Mini Project Coordinator for their help, guidance and encouragement, they
provided during the project development. This work would have not been possible without their
valuable time, patience and motivation. We thank them for making our stint thoroughly pleasant
and enriching. It was great learning and an honor being their student.

We are deeply thankful to Dr. Jyothi Digge (H.O.D Electronics and Telecommunications
Department) and entire team in the Electronics and Telecommunications Department. They
supported us with scientific guidance, advice and encouragement, they were always helpful and
enthusiastic and this inspired us in our work.

We take the privilege to express our sincere thanks to Dr. L. K. Ragha our Principal for providing
the encouragement and much support throughout our work.

“Raj Ravi Upreti” “ID No: TU2F1920001” ---------------------------

Date: _____________________
Place: _____________________
 Index

TABLE OF CONTENTS

Sr. No. Title Page No.

Abstract

List of Figures

List of Tables

Chapter 1 Introduction
1.1 Sub chapter
1.2 Sub chapter
Chapter 2 Problem Statement

Chapter 3 Literature Survey

Chapter 4 Design and Implementation

Chapter 5 Results

Chapter 6 Conclusion and future work

Reference
 Abstract

Traffic light controller establishes a set of rules and instructions that drivers, pilots, train
engineers, and ship captains rely on to avoid collisions and other hazards. Traffic control systems
include signs, lights and other devices that communicate specific directions, warnings, or
requirements. In order to minimize the road congestion and avoid accidents we implement this
system, for a better traffic control at the highway-farm road intersections.

Highways in India connect India is a populated country with busy road schedule. Our highways
connect the rural to the urban or the sub-urban region. The supply and the daily trade trucks from
farms access the highways. By using Road Traffic Signal Controllers, they can reduce the
number without investing extra manpower and also avoid road traffic congestion.

We wrote a source code on Vivado Xilinx on xc7a100tcsg324-1 board to overcome the problem.
 List of Figures

Sr. No. Name of Figure Page No.

1 2.1 11

2 4.1 13

3 4.2 14

4 4.3 14

5 4.4 15

6 4.5 15

7 5.1 26

8 5.2 26

9 5.3 27

10 5.4 27
 Chapter 1

Introduction

1.1 Motivation:

1.1.1 Need of the problem

Road Traffic Signal Controllers provide safe and smooth road traffic by
conducting road traffic control in accordance with the road traffic conditions (traffic on a
highway is frequent, whereas the farm road is only used a few times in a day), and
perform advanced road traffic control to eliminate road traffic congestion. Suitable also
for crosswalks with multi-information displays, they are replete with many additional
functions.

1.2 Scope of the project:

India is a populated country with busy road schedule. Our highways connect the
rural to the urban or the sub-urban region. The supply and the daily trade trucks from
farms access the highways. According to Census of 2011 11.9% of road accidents occur
on these types of intersections. By using Road Traffic Signal Controllers, they can reduce
the number without investing extra manpower and also avoid road traffic congestion.
 Chapter 2
Problem Statement

2.1 Problem statement

A sensor on the farm is to detect if there are any vehicles and change the traffic light to
allow the vehicles to cross the highway. Otherwise, highway light is always green since it
has higher priority than the farm.

2.2 Features
There is a sensor in the farm way side to detect if there is any vehicle on the farm
way. If vehicles are detected on the farm way, traffic light on the high way turns to
YELLOW, then RED so that the vehicles from the farm way can cross the high way.
Otherwise, the traffic light on the high way is always GREEN and traffic light on the
farm way is always RED. The time period is 3 seconds for the YELLOW light and 10
seconds for the RED light.

2.3 Objectives
To write a source code for a traffic light controller on FPGA.

2.4 Specifications of the system

xc7a100tcsg324-1, Vivado Xilinx 2021.2
Fig.2.1(Source: https://www.findchips.com/search/xc7a100tcsg324)
 Chapter 3

Literature Survey

At an intersection, the movements of various users such as vehicles follow the rules indicated by
traffic signals. In traditional traffic signal settings, there exists a sequence of indications that
periodically repeats. There are three main concepts describing traffic signal sequence settings:
cycle, phase, and duration. The cycle is the total time required to complete one signalization
sequence for all movements at an intersection, the phase is the controller timing unit associated
with one or more movements, and the duration is the amount of time the signal spends in each
phase, during which the signal indications do not change. Furthermore, a traffic flow group is
defined as one or more compatible movements of road users, and each phase has a set of timings
for each traffic flow group.
 Chapter 4

Design and Implementation

The following is the desired design of the system:

System in Ideal State:

Fig.4.1

When the Farm Road sensor is inactive:

Fig.4.2

When the sensor gets active i.e., when sensor detects a vehicle on the farm road:

Fig.4.3

Sensor is active. Vehicle on the farm road is approaching the intersection:

 Fig.4.4

Sensor about to complete its time cycle i.e., Vehicle has crossed the intersection:

Fig.4.5

Algorithm:
 • Source code for traffic light controller.
• Preprocessor Directives.
• Include Statements.
• Parameter definitions.
• DUT Input regs.
• DUT Output wires.
• DUT Instantiation.
• Initial Conditions.
• Generating Test Vectors.
• Debug output.
• Determines the simulation limit.

Code:

• For Traffic Light Controller:

module traffic_light(light_highway, light_farm, C, clk, rst_n);

parameter HGRE_FRED=2'b00,

HYEL_FRED = 2'b01,

HRED_FGRE=2'b10,

HRED_FYEL=2'b11;

input C,

clk,

rst_n;

output reg[2:0] light_highway, light_farm;

reg[27:0] count=0,count_delay=0;

reg delay10s=0,
delay3s1=0,delay3s2=0,RED_count_en=0,YELLOW_count_en1=0,YELLOW_count_en2=0;

wire clk_enable;

reg[1:0] state, next_state;

always @(posedge clk or negedge rst_n)

begin

if(~rst_n)

state <= 2'b00;

else

state <= next_state;

end

always @(*)

begin

case(state)

HGRE_FRED: begin

RED_count_en=0;

YELLOW_count_en1=0;

YELLOW_count_en2=0;

light_highway = 3'b001;
light_farm = 3'b100;

if(C) next_state = HYEL_FRED;

else next_state =HGRE_FRED;

end

HYEL_FRED: begin

light_highway = 3'b010;

light_farm = 3'b100;

RED_count_en=0;

YELLOW_count_en1=1;

YELLOW_count_en2=0;

if(delay3s1) next_state = HRED_FGRE;

else next_state = HYEL_FRED;

end

HRED_FGRE: begin

light_highway = 3'b100;

light_farm = 3'b001;

RED_count_en=1;

YELLOW_count_en1=0;

YELLOW_count_en2=0;

if(delay10s) next_state = HRED_FYEL;

else next_state =HRED_FGRE;

end

HRED_FYEL:begin

light_highway = 3'b100;

light_farm = 3'b010;

RED_count_en=0;

YELLOW_count_en1=0;

YELLOW_count_en2=1;

if(delay3s2) next_state = HGRE_FRED;

else next_state =HRED_FYEL;

end

default: next_state = HGRE_FRED;

endcase

end

always @(posedge clk)

begin

if(clk_enable==1) begin

if(RED_count_en||YELLOW_count_en1||YELLOW_count_en2)

count_delay <=count_delay + 1;

if((count_delay == 9)&&RED_count_en)

begin
delay10s=1;

delay3s1=0;

delay3s2=0;

count_delay<=0;

end

else if((count_delay == 2)&&YELLOW_count_en1)

begin

delay10s=0;

delay3s1=1;

delay3s2=0;

count_delay<=0;

end

else if((count_delay == 2)&&YELLOW_count_en2)

begin

delay10s=0;

delay3s1=0;

delay3s2=1;

count_delay<=0;

end

else

begin

delay10s=0;

delay3s1=0;
 delay3s2=0;

end

end

end

always @(posedge clk)

begin

count <=count + 1;

if(count == 3)

count <= 0;

end

assign clk_enable = count==3 ? 1: 0;

endmodule

• Testbench Code:

`timescale 10 ns/ 1 ps

`define DELAY 1
module tb_traffic;

parameter ENDTIME = 400000;

reg clk;

reg rst_n;

reg sensor;

wire [2:0] light_farm;

wire [2:0] light_highway;

traffic_light tb(light_highway, light_farm, sensor, clk, rst_n);

initial

begin

clk = 1'b0;

rst_n = 1'b0;

sensor = 1'b0;

end

initial

begin
main;

end

task main;

fork

clock_gen;

reset_gen;

operation_flow;

debug_output;

endsimulation;

join

endtask

task clock_gen;

begin

forever #`DELAY clk = !clk;

end

endtask

task reset_gen;

begin

rst_n = 0;

# 20

rst_n = 1;

end
endtask

task operation_flow;

begin

sensor = 0;

# 600

sensor = 1;

# 1200

sensor = 0;

# 1200

sensor = 1;

end

endtask

task debug_output;

begin

$display("----------------------------------------------");

$display("------------------ -----------------------");

$display("----------- SIMULATION RESULT ----------------");

$display("-------------- -------------------");

$display("---------------- ---------------------");

$display("----------------------------------------------");
$monitor("TIME = %d, reset = %b, sensor = %b, light of highway = %h, light of farm road =
%h",$time,rst_n ,sensor,light_highway,light_farm );

end

endtask

task endsimulation;

begin

#ENDTIME

$display("-------------- THE SIMUALTION END ------------");

$finish;

end

endtask

endmodule
 Chapter 5

Results

When the Farm Road sensor is inactive:

Fig.5.1

When the sensor gets active i.e., when sensor detects a vehicle on the farm road:

Fig.5.2
Sensor is active. Vehicle on the farm road is approaching the intersection:

Fig.5.3

Sensor about to complete its time cycle i.e., Vehicle has crossed the intersection:

Fig.5.4
 Chapter 6

Conclusion and Future Scope

5.1 Conclusion

An FPGA code of traffic light controller system of a two roads structure with two traffic lights
has been simulated, implemented and tested. The system has been coded using Verilog, and
implemented on hardware using Artix-7 FPGA xc7a100tcsg324-1. The code reaches the
maximum utilization of the traffic either during rush hours or normal time.

5.2 Future Scope

Some of these functions are to control more than two traffic lights. Also, to allow the user to
assign the time for each traffic light (i.e., minimum time to be Green), adding more sensors on
each road to count the number of cars in each road and check for the longer queue to increase the
timer for that road, another function is to link the traffic light with the other traffic lights along
the streets to increase the flow of traffic.
 References

[1] FPGA-Based Advanced Real Traffic Light Controller System Design | Intelligent Data
Acquisition and Advanced Computing Systems: Technology and Applications, 2007. IDAACS
2007. 4th IEEE Workshop on.

[2] Lec-25 System Design Example - Traffic Light Controller | http://nptel.ac.in