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Lab 4

The document contains 8 sections describing various digital logic components. Section 1 describes a D flip flop module and testbench. Section 2 describes a structural model for a T flip flop using D flip flops. Section 3 describes a 4-bit loadable up counter and testbench. Section 4 describes a JK flip flop module using parameters. Section 5 describes a SR latch in gate level modeling and testbench. Section 6 describes a 4-bit mod-12 loadable up counter. Section 7 describes a 4-bit loadable synchronous up/down counter. Section 8 describes a 4-bit serial-in serial-out shift register and testbench.

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Suyash Mishra
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645 views23 pages

Lab 4

The document contains 8 sections describing various digital logic components. Section 1 describes a D flip flop module and testbench. Section 2 describes a structural model for a T flip flop using D flip flops. Section 3 describes a 4-bit loadable up counter and testbench. Section 4 describes a JK flip flop module using parameters. Section 5 describes a SR latch in gate level modeling and testbench. Section 6 describes a 4-bit mod-12 loadable up counter. Section 7 describes a 4-bit loadable synchronous up/down counter. Section 8 describes a 4-bit serial-in serial-out shift register and testbench.

Uploaded by

Suyash Mishra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB-4

1.Write RTL description and testbench for D flip flop.

module dff_T( din ,clk ,reset ,dout );

output dout ;

reg dout;

input din ;

input clk ;

input reset ;

always @ (posedge clk)

begin

if (reset)

dout <= 1;

else

dout <= din;

end

endmodule
//testbench

module dff_test;

reg D, clk,reset;

wire Q, QBAR;

dff dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(clk));

initial begin

clk=0;

forever #10 clk = ~clk;

end

initial begin

reset=1; D <= 0;

#100; reset=0; D <= 1;

#100; D <= 0;

#100; D <= 1;

end

endmodule
2.Write structural model for T flip flop using D flip flop.

DFF:

module dff_T( din ,clk ,reset ,dout );

output dout ;

reg dout;

input din ;

input clk ;

input reset ;

always @ (posedge clk)

begin

if (reset)

dout <= 1;

else

dout <= din;

end

endmodule

TFF:

module tff ( t ,clk ,reset ,q,qb );

output q,qb ;

input t ;

input clk ;

input reset ;

wire ip;
wire op;

assign ip = t ^ op;

dff_T DUT (.din(ip),

.clk(clk),

.reset(reset),

.dout(op));

assign q = op;

assign qb = ~q;

endmodule

//TESTBENCH

module tff_tb;

reg T;

reg Clk;

wire Q;

wire Qbar;

tff DUT (

.ip(T),

.clk(Clk),

.q(Q),

.qb(Qbar)

);

initial begin

Clk=0;

forever #10 Clk = ~Clk;

end
initial begin

T <= 0;

#100; T <= 1;

#100; T <= 0;

#100; T <= 1;

end

endmodule
3. Write RTL description for 4 bit loadable up counter and verify using testbench.

module upcounter (input clk,

input rstn,

output reg[3:0] out);

always @ (posedge clk) begin

if (! rstn)

out <= 0;

else

out <= out + 1;

end

endmodule

//TESTBENCH

module upcounter_tb;

reg clk;

reg rstn;

wire [3:0] out;

upcounter DUT ( .clk (clk),

.rstn (rstn),

.out (out));

always #5 clk = ~clk;

initial begin

clk <= 0;

rstn <= 0;

#20 rstn <= 1;

#80 rstn <= 0;

#50 rstn <= 1;

#20 $finish;

end

endmodule
4.Write RTL description for JK flip flop using parameter declaration for the respective scenarios
HOLD, SET, RESET, TOOGLE.

module jk(input clk,rst,j,k, output reg q, wire qb);

parameter HOLD = 2'b00;

parameter RESET = 2'b01;

parameter SET = 2'b10;

parameter TOGGLE = 2'b11;

always @(posedge clk)

begin

if(rst)

q<= 1'b0;

else

begin

case({j,k})

HOLD: q<= q;

SET: q<=1'b1;

RESET: q<= 1'b0;

TOGGLE: q<= ~q;

default :q<= 0;

endcase

end

end

assign qb = ~q;

endmodule
//TESTBENCH

module jt_tb;

reg clk,rst,j,k;

wire q,qb;

jk DUT(clk,rst,j,k,q,qb);

initial begin

clk=1'b0;

forever #10 clk=~clk;

end

task rest;

begin

@(negedge clk)

rst=1'b1;

@(negedge clk)

rst=1'b0;

end

endtask

task jk_inputs(input m,n);

begin

@(negedge clk)

j=m;

k=n;

end

endtask

initial begin

rest;

jk_inputs(1'b0,1'b0);
jk_inputs(1'b0,1'b1);

jk_inputs(1'b1,1'b0);

jk_inputs(1'b1,1'b1);

end

endmodule
5.Implement SR latch in gate level modelling and verify using test bench.

module sr_latch(Q, Qn, G, S, R);

output Q;

output Qn;

input G;

input S;

input R;

wire S1;

wire R1;

and(S1, G, S);

and(R1, G, R);

nor(Qn, S1, Q);

nor(Q, R1, Qn);

endmodule

//TESTBENCH

module sr_latch_tb;

reg p,q,r;

sr_latch DUT(.S(p),.R(q),.G(r));

initial begin

p = 1;

q = 1;

r = 1;

#100 p = 0;

#100 p = 1;
#100 q = 0;

#100 q = 1;

#100 p = 0;

q = 0;

#100 p = 1;

q = 1;

#100 p = 0;

q = 0;

#100 ;

end

endmodule
6. Write RTL description for 4 bit MOD 12 loadable binary up counter and verify using testbench.

module MOD_12_up(out,rst,clk);

output [3:0]out;

input rst,clk;

reg [3:0]out;

always @(posedge clk)

begin

if(rst|out==4'b1011)

out<=4'b0000;

else

out<=out+1;

end

endmodule

//TESTBENCH

module mod_12_up_tb;

reg clk;

reg rst;

wire [3:0] out;

MOD_12_up DUT ( .clk (clk),

.rst (rst),

.out (out));

always #10 clk = ~clk;

initial begin

clk <= 0;

rst <= 0;

#20 rst <= 1;

#40 rst <= 0;

end

endmodule
7. Write RTL description for 4 bit loadable binary synchronous up/down counter and verify using
testbench.

module up_dwn_cntr(

Clk,

reset,

UpOrDown,

Count

);

input Clk,reset,UpOrDown;

output [3 : 0] Count;

reg [3 : 0] Count = 0;

always @(posedge(Clk) or posedge(reset))

begin

if(reset == 1)

Count <= 0;

else

if(UpOrDown == 1)

if(Count == 15)

Count <= 0;

else

Count <= Count + 1;

else

if(Count == 0)

Count <= 15;

else

Count <= Count - 1;

end

endmodule
//TESTBENCH

module up_dwn_cntr_tb;

reg Clk;

reg reset;

reg UpOrDown;

wire [3:0] Count;

up_dwn_cntr DUT (

.Clk(Clk),

.reset(reset),

.UpOrDown(UpOrDown),

.Count(Count)

);

initial Clk = 0;

always #5 Clk = ~Clk;

initial begin

reset = 0;

UpOrDown = 0;

#300;

UpOrDown = 1;

#300;

reset = 1;

UpOrDown = 0;

#100;

reset = 0;

end

endmodule
8. Write RTL description for 4 bit SISO and verify using testbench.

module siso(clk,i,so);

input clk,i;

output so;

reg [0:7] temp;

always @(posedge clk)

begin

temp = temp>>1;

temp[0] =i;

end

assign so = temp[7];

endmodule

//TESTBENCH

module siso_tb;

reg clk,i;

wire s0;

siso dut (clk,i,so);

initial

begin

clk = 1'b0;

forever #10 clk=~clk;

end

task rst;

begin

i=0;

end

endtask
task inputs(input m);

begin

i=m;

end

endtask

initial

begin

rst;

inputs(1);

#10;

inputs(0);

#10;

inputs(1);

#10;

inputs(1);

#10;

end

endmodule

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