Proceedings of the Fourth International Conference on Computing Methodologies and Communication (ICCMC 2020)

IEEE Xplore Part Number:CFP20K25-ART; ISBN:978-1-7281-4889-2

VLSI Implementation of Turbo Coder for LTE

using Verilog HDL
2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC) 978-1-7281-4889-2/20/$31.00 ©2020 IEEE 10.1109/ICCMC48092.2020.ICCMC-00051

Akshaya V Sreehari K N Anu Chalil

Dept. of Electronics and Dept. of Electronics and Dept. of Electronics and
Communication Engineering Communication Engineering Communication Engineering
Amrita Vishwa Vidyapeetham, Amrita Vishwa Vidyapeetham, Amrita Vishwa Vidyapeetham,
Amritapuri, India Amritapuri, India Amritapuri, India
[email protected] [email protected] [email protected]

Abstract—Turbo codes are error correction codes that are conventional convolutional encoders since it generates low
widely used in communication systems.Turbo codes exhibits high weight parity codes. MAP algorithm is used for the decoding
error correction capability as compared with other error correc- of turbo encoded data in which errors are intentionally added
tion codes. This paper proposes a Very Large Scale Integration
(VLSI) architecture for the implementation of Turbo decoder. and verified an error free decoded data after decoding.
Soft-in-soft out decoders, interleavers and deinterleavers is used
in the decoder side which employs Maximum-a-Posteriori (MAP)
algorithm. The number of iterations required to decode the II. LITERATURE REVIEW
information bits being transmitted is reduced by the use of MAP Kavinilavu, Salivahanan, and Bhaaskaran in their work
algorithm. For the encoder part, this paper uses a system which
contains two Recursive convolutional encoders along with pseudo- [1] develop and integrates the Convolutional encoder and
random interleaver in encoder side.The Turbo encoding and Viterbi decoder. In ModelSim 10.0e they have planned and
decoding is done using Octave, Xilinx Vivado, Cadence tools.The modeled and synthesized using XILINX-ISE 12.4i.Max Log
system is implemented and synthesized in Application Specific MAP algorithm-based turbo decoder output variations on
Integrated Circuit (ASIC).Timing analysis has been done and implemented with fixed point, Vedic and Booth multipliers
GDSII file has been generated.
have been presented by authors in paper [2]. A basic turbo
Index Terms—Turbo codes, Channel coding, Interleaver, SISO, coding strategy is proposed in [3] to maximize the error
Iterative decoder, MAP, Cadence, NClaunch, Xilinx Vivado quality of a standard rate-1/3 turbo code. In the paper [4]
the authors introduced the high-speed turbo SISO Decoder.
I. I NTRODUCTION Standardization operation was applied to state metric branch
In a communication system, when data is transferred from values rather than branch metric values. A minimum- power,
the source system to a destination system, errors can be and area-efficient turbo soft-output (SISO) decoder based on
present in the received signal at the source end. So error the Viterbi algorithm are proposed in [5]. The paper presents
correction is required to retrieve the original message.Turbo the implementation of SOVA decoder for different constraint
codes, which were first introduced in 1993, represent a lengths. Compared to a conventional SOVA decoder applica-
quantum leap in channel coding techniques and a turning tion, simulation results show power savings and area savings.
point for modern digital telecommunication.Turbo codes is The designers in [6] developed a turbo decoder architecture
one of existing powerful error correcting codes.Turbo codes in which utilizes both parallel SISO decoder tier and parallel
has inspired the coding community with the possibility of trellis stage level.In the LTE-Advanced standard, the authors in
using an iterative decoding technique that relies solely on paper [7] present the design and implementation of a memory-
simple constituent code to achieve close channel capacity. reduced Turbo decoder on the field programmable gate array
Turbo coder architecture (Fig 1)comprises of turbo encoder (FPGA). In this paper [8] the author presents a summary
and turbo decoder. Encoder consists of two Recursive of the architecture issues relevant to turbo decoders. As a
Convolutional Encoders(RSC) and interleaver. In this paper, feature of the code’s key parameter, an evaluation of different
pseudo-random interleaver is used due to which the interleaved types of turbo decoders is carried out. The authors in paper
version of the code tends to be long and scrambled, that [9] proposed a new low-complexity Min-Log-MAP algorithm
gives good performance of random codes. In turbo code variant in their study. The encoding of tail-biting codes using
implementation, RSC encoders are employed rather than hierarchical input encoders is done in paper [10], which is an
important design criterion. Authors in their work [11] explore
the different methods used in turbo codes to end trellis in the

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 Proceedings of the Fourth International Conference on Computing Methodologies and Communication (ICCMC 2020)
IEEE Xplore Part Number:CFP20K25-ART; ISBN:978-1-7281-4889-2

recursive systematic convolutional encoders. With minimum The usually used method of turbo code decoding is carried
generator polynomials, the author in [12] has achieved very out using the BCJR algorithm.The fundamental and basic
low rate convolutional codes. For different code rates and for idea behind the turbo decoding algorithm is the iteration
different constraint lengths, the authors in the paper [13],the between the two SISO part decoders which is illustrated
Sum Product Algorithm (SPA) and One Step Majority Logic in figure 3. It comprises a pair of decoders,those which
Decoding Algorithm (OSMLGD)is put together to decode the work simulateneously in order to refine and upgrade the
LDPC codes and their individual performances were com- estimate of the original information bits. The first and
pared. second SISO decoder, respectively, decodes the convolutional
code generated by the first or second CE.A turbo-iteration
corresponds to one pass of the first component decoder which
III. IMPLEMENTATION is followed by a pass of the second component decoder.
A. Architecture of Turbo Coder
Turbo encoder and decoder together comprises the Turbo
coder architecture(shown in figure 1).Two identical Recursive
convolutional encoders(RSC) and a pseudorandom interleaver
constitutes the turbo encoder (figure 2).LTE employs a 1/3
rate parallel concatenated turbo code. Each RSC works on
two different data. Original data is provided to the first
encoder, while the second encoder receives the interleaved
version of the input data. A specified algorithm is used to
scramble the data bits and the method is called Interleaving.
An appreciable impact on the performance of a decoder
is seen with the interleaving algorithm when used. The
RSC1 and RSC2 encoder outputs along with systematic
input comprises the output of turbo encoder,that is, a 24 bit
output is generated which is illustrated in figure 6. This will
be transmitted through the channel to the Turbo decoder.A
standard turbo decoder block diagram is shown in Figure Fig. 3. Turbo Decoder Block diagram
3 that contains two modules of SISO decoders together
with two pseudorandom interleavers and a pseudorandom
deinterleaver. B. SISO Decoder
The signal which is received at the input of a soft-in-soft-
out (SISO) decoder is the real (soft)value of that signal.An
estimate of each input bit The decoder then generates an
approximation for each data bit expressing the probability
that the transmitted data bit is equal to one.The maximum
a-posteriori (MAP) algorithm is used in the turbo-decoder
under consideration in this paper for the SISO component
decoder.The MAP algorithm never restricts the set of bit
Fig. 1. Turbo Coder Block diagram estimates to correspond strictly to a valid path through the
trellis. Therefore, the results produced by a Viterbi decoder
that recognizes the most likely true path through the trellis
should differ from those generated by that.
1) The MAP Algorithm : The MAP algorithm minimizes
the likelihood of bit error by using the entire sequence that
was obtained to figure out the most likely bit at each trellis
point. Consider a frame of N coded symbols consisting of
m bits and the channel output received by the decoder as y.
For every dsymi , a MAP decoder provides a 2m a posteriori
probabilities. The hard decision on the value j that is equal to
dsym
i , helps to maximize the a posteriori probabilities. It is
expressed injoint probabilities as:

P (dsym = j, y)
Fig. 2. Turbo Encoder Block Diagram P r(dsym
i = j|y) = 2m −1 i sym (1)
k=0 (P (di = k, y)

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 Proceedings of the Fourth International Conference on Computing Methodologies and Communication (ICCMC 2020)
IEEE Xplore Part Number:CFP20K25-ART; ISBN:978-1-7281-4889-2

The trellis form of the code allows the decomposition of a Xilinx based software suite. It may be used for HDL design
computing the joint probabilities among the former and latter synthesis and analysis. Recursive convolutional encoder, Turbo
observations.The Forward recursion metric αi (S) used in de- encoder decoder simulation outputs are performed using Xil-
composing is shown in Equation 2. It provide the probabilties inx Vivado and Octave. The netlist is generated from RTL
of state S instantly at i acquired from previous values from the using Cadence NCLaunch during synthesis. Nclaunch is a GUI
channel.Backward recursion metric βi (S) is also used to find that helps in managing large-scale design projects and allows
the probabilities of the state calculated using the forthcoming to customize and launch Cadence simulation software. RTL

values from channel and Branch metric γ(S ,S) . compiler Ultra is used for logic synthesis and analysis for
digital designs. Physical design (Floor-planning, placement,
   routing) is done using Encounter tool. The Cadence imple-
P r(dsym
i = j|y) = αi (S )γi (S , S)βi+1 (S) mentation tool uses netlist as input and does optimization,
(S i ,S)/dsym
i =j placement, and routing.
(2)
And the branch metric is given by
 
γi (S , S) = p(yi |xi ).P ra (dsym
i = dsym
i (S , S)) (3)
where,
p(yi |xi ) =channel transition probability,
xi = ith transmitted modulated symbol and
yi = ith received symbol.

For an equiprobable source, the a priori probability is

1/2m . In Equation 1, the branch metric is adjusted to
eliminate the input of symbol channel.

Fig. 5. Output of RSC encoder using Xilinx Vivado. 1/2 rate RSC encoder
C. Interleaver is shown.That is, for 1 input bit, 2 output bits have been generated
Choosing the interleaver is a significant part of the turbo
code design. Interleavers scramble data in a pseudorandom
order to lessen the resemblance between adjacent bits at the
input of the convolutional encoder.The interleaver is used on
both the encoder part and the decoder part. It produces a
long block of data on the encoder side, while it compares
two SISO decoders’ output in the decoder portion and helps
to fix the error. Pseudo-random deinterleaver functions in a
complimentary manner of pseudo-random interleaver.

Fig. 6. Octave output :RSC encoder

Fig. 4. Psuedo-random interleaver:working principle

Fig. 7. Simulation output of Turbo Encoder using Vivado.The encoder output

IV. RESULTS AND DISCUSSION is in concatenated form which is of 24 bits which is transmitted through the
channel.
The turbo encoder and decoder simulations are done using
Verilog HDL in Xilinx Vivado 2018.3.Vivado Design Suite is

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 Proceedings of the Fourth International Conference on Computing Methodologies and Communication (ICCMC 2020)
IEEE Xplore Part Number:CFP20K25-ART; ISBN:978-1-7281-4889-2

Fig. 8. Octave Output:Turbo Encoder.

X is the random input generated which is interleaved(randomised) and finally
appended to get 24 bits after encoding.

Fig. 12. Layout of Turbo decoder

algorithm identifies the most probable bit of information

that was sent.Original MAP algorithm is used because the
number of iterations for process decoding is reduced. Many
approximations on the MAP algorithm are usable, such as the
Max-Log MAP algorithm, where computations are mostly in
the logarithmic realm, thus facilitating the implementation of
values and operations.Here, the decoder successfully corrects
the error and retrieves the original message.Synthesis is done
in Xilinx Vivado 2018.3 and results are tabulated.Synthesis
is done using Cadence NClaunch to convert the RTL into
Fig. 9. Simulation output of Turbo decoder using Vivado.
The two SISO component decoders generate dec data1 and dec data2 which
netlist.Encounter tool is used to convert the netlist to phys-
is of 8 bits each and error s1 and error s2 are the corresponding errors ical design.Floor planning, placement and routing are per-
calculated by the respective component decoders. Both of the SISO decoders formed.GDS II file has been generated successfully.
generate zero error.
R EFERENCES
[1] V. Kavinilavu1, S. Salivahanan, V. S. Kanchana Bhaaskaran2 , Samiappa
Sakthikumaran, B. Brindha and C. Vinoth ”Implementation of Convo-
lutional Encoder and Viterbi Decoder using Verilog HDL ”, IEEE 3rd
International Conference on Electronics Computer Technology,2011
[2] Aswathy Narayanan ; Senthil Murugan ; Ramesh Bhakthavatchalu, ”Low
Latency Max Log MAP based Turbo Decoder”, International Conference
on Communication and Signal Processing (ICCSP),2019
[3] C. Tanriover ; B. Honary ; Jun Xu ; Shu Lin”, ”Improving turbo code
error performance by multifold coding”,IEEE Communications Letters,
2002
[4] Shweta Ramteke ; Sandeep Kakde ; Yogesh Suryawanshi , ”HDL Imple-
mentation of Turbo Decoder Using Soft Output Viterbi Algorithm”,2015.
Fig. 10. Timing report of Turbo encoder decoder [5] J.H. Han ; A.T. Erdogan ; T. Arslan ,”Power and area efficient turbo
decoder implementation for mobile wireless systems”, IEEE Workshop
on Signal Processing Systems Design and Implementation,2005
[6] Cheng-Chi Wong ; Ming-Wei Lai ; Chien-Ching Lin ; Hsie-Chia Chang
; Chen-Yi Lee,”Turbo Decoder Using Contention-Free Interleaver and
Parallel Architecture”,IEEE Journal of Solid-State Circuits”,2010
[7] Yaqin Shi ; Ming Zhan ; Jie Zeng , ”FPGA Implementation and Power
Estimation of a Memory-Reduced LTE-Advanced Turbo Decoder”,
IEEE International Conference on Internet of Things (iThings) and
IEEE Green Computing and Communications (GreenCom) and IEEE
Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data
(SmartData), 2018.
Fig. 11. Power Utilisation Of Turbo encoder decoder [8] E. Boutillon, C. Douillard, and G. Montorsi , ”Iterative decoding of
concatenated convolutional codes: Implementation issues”,Proc. IEEE,
vol. 95, no. 6, pp. 1201–1227,June, 2007
[9] Rami Klaimi ; Charbel Abdel Nour ; Catherine Douillard ; Joumana
Farah ,”Low-complexity decoders for non-binary turbo codes” ,IEEE
10th International Symposium on Turbo Codes Iterative Information
V. CONCLUSION Processing (ISTC), 2018
[10] Maria Kovaci ; Horia Balta,”Performance of trellis termination meth-
Turbo encoding and decoding is done using Verilog HDL.The ods for RSC component encoders of turbo codes”, 10th International
decoder is developed based on MAP algorithm. The MAP Symposium on Electronics and Telecommunications,IEEE,2012

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IEEE Xplore Part Number:CFP20K25-ART; ISBN:978-1-7281-4889-2

[11] L. Dinoi and S. Benedetto,”Variable-size interleaver design for parallel

turbo decoder architectures”,IEEE Global Telecommunications Conf.,
Nov. 2004, pp. 3108–3112 ,2004
[12] Neha.S, Pargunarajan.K ”Hybrid sub-optimal decoding technique for
LDPC codes”,Proceedings of IEEE International Conference on Circuit,
Power and Computing Technologies, ICCPCT 2016 ,2 August 2016,
Article number 7530160.
[13] Priyadarshini, N. Pargunarajan, K., “A Constrained Search Algorithm
for Selection of Optimal Generators in Convolutional Encoder,” In-
ternational Journal of Computer Science Engineering and Technology
(IJCSET), July 2011,Vol 1, Issue 6, 324-326.

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