29-09-2021

Introduction: Counters Asynchronous (Ripple) Counters

 Counters are circuits that cycle through a specified
number of states.  Asynchronous counters: the flip-flops do not
change states at exactly the same time as they do
 Two types of counters: not have a common clock pulse.
 synchronous (parallel) counters  Also known as ripple counters, as the input clock
 asynchronous (ripple) counters pulse “ripples” through the counter – cumulative
delay is a drawback.
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.  n flip-flops  a MOD (modulus) 2n counter.
(Note: A MOD-x counter cycles through x states.)
 Synchronous counters apply the same clock to all
flip-flops.  Output of the last flip-flop (MSB) divides the
input clock frequency by the MOD number of the
counter, hence a counter is also a frequency
divider.

Asynchronous (Ripple) Counters Asynchronous (Ripple) Counters

 Example: 2-bit ripple binary counter. HIGH

J Q0 J Q1
 Output of one flip-flop is connected to the clock CLK C
Q0
C
input of the next more-significant flip-flop. K K

FF0 FF1

HIGH CLK 1 2 3 4

Q0 J Q1
J Q0

CLK C C
Q0
K K Q0 0 1 0 1 0

FF0 FF1 Timing diagram

Q1 0 0 1 1 0 00  01  10  11  00 ...

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Asynchronous (Ripple) Counters Asynchronous (Ripple) Counters

 Example: 3-bit ripple binary counter.  Propagation delays in an asynchronous (ripple-
HIGH
clocked) binary counter.
J Q0 J Q1 J Q2  If the accumulated delay is greater than the clock
CLK C Q0 C Q1 C pulse, some counter states may be misrepresented!
K K K
FF0 FF1 FF2
CLK 1 2 3 4

CLK 1 2 3 4 5 6 7 8 Q0

Q0 0 1 0 1 0 1 0 1 0 Q1

Q1 0 0 1 1 0 0 1 1 0 Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
Q2 0 0 0 0 1 1 1 1 0 tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
Recycles back to 0

Asynchronous (Ripple) Counters Asyn. Counters with MOD no. < 2n

 Example: 4-bit ripple binary counter (negative-  States may be skipped resulting in a truncated
edge triggered). sequence.
HIGH  Technique: force counter to recycle before going
J
Q0
J
Q1
J
Q2
J
Q3 through all of the states in the binary sequence.
CLK
K
C
K
C
K
C
K
C
 Example: Given the following circuit, determine the
FF0 FF1 FF2 FF3 counting sequence (and hence the modulus no.)
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C B A
Q J Q J Q J
Q0
All J, K CLK CLK CLK
inputs are Q K Q K Q K
Q1 CLR CLR CLR
1 (HIGH).
Q2
B
Q3 C

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Asyn. Counters with MOD no. < 2n Asyn. Counters with MOD no. < 2n
 Example (cont’d):  Example (cont’d): Counting sequence of
C
Q J
B
Q J
A
Q J
circuit (in CBA order).
1 2 3 4 5 6 7 8 9 10 11 12
All J, K CLK CLK CLK Clock
inputs are Q K Q K Q K A 0 1 0 1 0 1 0 1
CLR CLR CLR
1 (HIGH). 0 0 1 1 0 0 0 0
B
0 0 0 0 1 1 0 0
B C
C NAND 1
Output 0

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter 111 000
produced by clearing Temporary 001
A state
(a MOD-8 binary Counter is a MOD-6
B 110
counter) when count 010 counter.
C of six (110) occurs.
NAND 1 101 011
Output 0 100

Asyn. Counters with MOD no. < 2n Asyn. Counters with MOD no. < 2n
 Exercise: How to construct an asynchronous MOD-  Decade counters (or BCD counters) are counters
5 counter? MOD-7 counter? MOD-12 counter? with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
 Question: The following is a MOD-? counter? meters, odometers, etc.).
F E D C B A
 Design an asynchronous decade counter.
Q J Q J Q J Q J Q J Q J
(A.C)'
Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR HIGH
D C B A
J Q J Q J Q J Q

C CLK C C C C
D K K K K
E All J = K = 1. CLR CLR CLR CLR
F

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Asyn. Counters with MOD no. < 2n Asynchronous Down Counters

 Asynchronous decade/BCD counter (cont’d).  So far we are dealing with up counters. Down
counters, on the other hand, count downward
HIGH
J Q
D
J Q
C
J Q
B
J Q
A (A.C)'
from a maximum value to zero, and repeat.
CLK C
K
C
K
C
K
C
K
 Example: A 3-bit binary (MOD-23) down counter.
CLR CLR CLR CLR

1
Q2
1 2 3 4 5 6 7 8 9 10 11
J
Q0 J Q1 J 3-bit binary
Clock Q Q Q
CLK C C C up counter
D 0 1 0 1 0 1 0 1 0 1 0 K
Q' K Q' K Q'
C 0 0 1 1 0 0 1 1 0 0 0
1
B 0 0 0 0 1 1 1 1 0 0 0
Q0 Q1 Q2 3-bit binary
J J J
A 0 0 0 0 0 0 0 0 1 1 0 Q Q Q
CLK C C C down counter
NAND K
Q' K Q' K Q'
output

Asynchronous Down Counters Cascading Asynchronous Counters

 Example: A 3-bit binary (MOD-8) down counter.  Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.
000
001 111  Connect last-stage output of one counter to the
1 clock input of next counter so as to achieve higher-
J Q
Q0 J Q
Q1 J Q
Q2
010 110 modulus operation.
CLK
K
C
Q'
C
K Q'
C
K Q'  Example: A modulus-32 ripple counter constructed
011 101 from a modulus-4 counter and a modulus-8
100 counter.
CLK 1 2 3 4 5 6 7 8
Q0 Q1 Q2 Q3 Q4
Q0 0 1 0 1 0 1 0 1 0
J Q J Q J Q J Q J Q
Q1 0 1 1 0 0 1 1 0 0 CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K
Q2 0 1 1 1 1 0 0 0 0
Modulus-4 counter Modulus-8 counter

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Cascading Asynchronous Counters Cascading Asynchronous Counters

 Example: A 6-bit binary counter (counts from  If counter is a not a binary counter, requires
0 to 63) constructed from two 3-bit counters. additional output.
A0 A1 A2 A3 A4 A5  Example: A modulus-100 counter using two
decade counters.
Count 3-bit 3-bit
pulse binary counter binary counter freq/10
1 CTENDecade CTENDecade freq/10
TC TC 0
A5 A4 A3 A2 A1 A0 counter counter
CLK C Q3 Q2 Q1 Q0 C Q3 Q2 Q1 Q0
0 0 0 0 0 0
0 0 0 0 0 1 freq
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0 TC = 1 when counter recycles to 0000
0 0 1 0 0 1
: : : : : :

Synchronous (Parallel) Counters Synchronous (Parallel) Counters

 Synchronous (parallel) counters: the flip-flops are  Example: 2-bit synchronous binary counter (using T
clocked at the same time by a common clock pulse. flip-flops, or JK flip-flops with identical J,K inputs).
 We can design these counters using the sequential Present Next Flip-flop
logic design process state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
 Example: 2-bit synchronous binary counter (using T 0 0 0 1 0 1 TA0 = 1
flip-flops, or JK flip-flops with identical J,K inputs). 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

Present Next Flip-flop 1

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0 J
A0 J A1
Q Q
0 0 0 1 0 1 C C
0 1 1 0 1 1 Q' K Q'
11 10 K
1 0 1 1 0 1
1 1 0 0 1 1 CLK

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Synchronous (Parallel) Counters Synchronous (Parallel) Counters

 Example: 3-bit synchronous binary counter (using T  Example: 3-bit synchronous binary counter (cont’d).
flip-flops, or JK flip-flops with identical J, K inputs). TA2 = A1.A0 TA1 = A0 TA0 = 1
Present Next Flip-flop
state state inputs
A2 A1 A0 A2 + A1+ A0+ TA2 TA1 TA0 A2 A1 A0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1 Q Q Q
0 1 1 1 0 0 1 1 1
J K J K J K
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1 CP
1 1 0 1 1 1 0 0 1 1
1 1 1 0 0 0 1 1 1
A1 A1 A1
1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1

Synchronous (Parallel) Counters Synchronous (Parallel) Counters

 Note that in a binary counter, the nth bit (shown  Example: 4-bit synchronous binary counter.
underlined) is always complemented whenever TA3 = A2 . A1 . A0
TA2 = A1 . A0
011…11  100…00
TA1 = A0
or 111…11  000…00 TA0 = 1
 Hence, Xn is complemented whenever A1.A0
Xn-1Xn-2 ... X1X0 = 11…11. 1 A2.A1.A0

A0 A1 A2 A3
 As a result, if T flip-flops are used, then J
C
Q J
C
Q J
C
Q J
C
Q

TXn = Xn-1 . Xn-2 . ... . X1 . X0 K

Q' K Q' K Q' K Q'

CLK

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Synchronous (Parallel) Counters Synchronous (Parallel) Counters

 Example: Synchronous decade/BCD counter.  Example: Synchronous decade/BCD counter
(cont’d).
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0 T0 = 1
1 0 0 0 1 T0 = 1
2 0 0 1 0 T1 = Q3'.Q0 T1 = Q3'.Q0
3 0 0 1 1 T2 = Q1.Q0 T2 = Q1.Q0
4 0 1 0 0
5 0 1 0 1
T3 = Q2.Q1.Q0 + Q3.Q0 T3 = Q2.Q1.Q0 + Q3.Q0
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0 Q0
9 1 0 0 1
1 T T Q1 T Q2 T Q3
10 (recycle) 0 0 0 0 Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK

Up/Down Synchronous Counters Up/Down Synchronous Counters

 Up/down synchronous counter: a  Example: A 3-bit up/down synchronous
bidirectional counter that is capable of binary counter.
counting either up or down. Clock pulse Up Q2 Q1 Q0 Down

 An input (control) line Up/Down (or simply

0
1
0
0
0
0
0
1
Up) specifies the direction of counting. 2
3
0
0
1
1
0
1
4 1 0 0
 Up/Down = 1  Count upward 5 1 0 1
6 1 1 0
 Up/Down = 0  Count downward 7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’

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Up/Down Synchronous Counters Exercise

 Example: A 3-bit up/down synchronous
binary counter (cont’d). 1.Design sequential logic circuit to count 1-3-
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
7-8-9-12-15-1 using T-flip flop
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) 2. Design sequential logic circuit to count 2-4-
6-8-11-13-2 using T- flip flop
Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK

Shift Register Counters Ring Counters

 Shift register counter: a shift register with the serial  One flip-flop (stage) for each state in the sequence.
output connected back to the serial input.  The output of the last stage is connected to the D
 They are classified as counters because they give a input of the first stage.
specified sequence of states.  An n-bit ring counter cycles through n states.
 Two common types: the Johnson counter and the  No decoding gates are required, as there is an
Ring counter. output that corresponds to every state the counter
is in.

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Ring Counters Johnson Counters

 Example: A 6-bit (MOD-6) ring counter.  The complement of the output of the last stage is
PRE connected back to the D input of the first stage.
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q  Also called the twisted-ring counter.
 Require fewer flip-flops than ring counters but
CLR
CLK more flip-flops than binary counters.
 An n-bit Johnson counter cycles through 2n states.
Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
010000
 Require more decoding circuitry than ring counter
1 0 1 0 0 0 0 000001 but less than binary counters.
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100

Johnson Counters Johnson Counters

 Example: A 4-bit (MOD-8) Johnson counter.  Decoding logic for a 4-bit Johnson counter.
Q0 Q1 Q2 Clock A B C D Decoding
D Q D Q D Q D Q A'
0 0 0 0 0 A'.D' State 0
Q' D'
Q3' 1 1 0 0 0 A.B'
2 1 1 0 0 B.C' A
CLR 3 1 1 1 0 C.D' State 1
CLK B'
4 1 1 1 1 A.D
5 0 1 1 1 A'.B B
Clock Q0 Q1 Q2 Q3 6 0 0 1 1 B'.C State 2
0000 C'
0 0 0 0 0 7 0 0 0 1 C'.D
1 1 0 0 0 0001 1000 C
State 3
2 1 1 0 0 D'
3 1 1 1 0 0011 1100 B' A
4 1 1 1 1 State 6 State 4
C D
5 0 1 1 1 0111 1110
6 0 0 1 1 C' A'
1111 State 7 State 5
7 0 0 0 1 D B