VC SpyGlass RTL Signoff Platform

VC SpyGlass RDC

Arjay Virdi
June 2021
CONFIDENTIAL INFORMATION
The following material is confidential information of Synopsys and is being
disclosed to you pursuant to a non-disclosure agreement between you or your
employer and Synopsys. The material being disclosed may only be used as
permitted under such non-disclosure agreement.

IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans,
such plans are as of the date of this presentation and are subject to
change. Synopsys is not obligated to develop the software with the features
and functionality discussed in these materials. In any event, Synopsys’
products may be offered and purchased only pursuant to an authorized quote
and purchase order or a mutually agreed upon written contract.

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VC SpyGlass RDC

• Understanding RDC
• Types of asynchronous resets
• RDC design techniques
• Types of RDC checks
• RDC flow

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VC SpyGlass
Industry-standard RTL signoff platform for static checking; Includes DO-254 rule set
Addresses Key Challenges in Static Verification Unified Compile with VCS

Unified Setup with DC/PT

Finding the hundred bugs out the million violations
10x noise reduction with AI vs. competition Lint

Clock Reset
Making multiple runs per day vs overnight runs
Domain Domain
3x performance vs. competition Crossing
Crossing

Running on standard vs high-end compute server AI

½ memory vs. competition

Unified Debug with Verdi

Avoiding setup and debug headaches
Synopsys Design Compiler, PrimeTime, Multi-Core Engines
VCS, Verdi compatibility
VC Data Model

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Why RDC is Critical Now?

• Now 100s of software resets

• Reset recovery during functional
Mobile SoCs operation a must
Artificial • Unstable resets can cause failures Number of Resets / Design
Intelligence (2018 Synopsys GUS)
50
IoT
40
• Low power design is pervasive
30
20
• Each power domain needs reset
10
0
Servers
• Many subsystems 2000 2005 2010 2015 2020
GPU
• 100s of blocks working
independently
• Each block needs reset

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What is Reset Domain Crossing (RDC)?

• Metastability caused by Asynchronous Reset Assertion

– Race condition between reset and clock rst1 causes d2 to
• Clocks can be same for source and destination flops of RDC violate setup-hold
window of FF2
Source Reset Destination
Domain FF1 FF2
Reset Domain
q1 d2 q2
D Q D Q

QB QB

RSTB RSTB

rst1 rst2

q2 goes metastable
• non-deterministic
clk
• high-current

Metastability (non deterministic value) can cause chip failures!

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What is *not* RDC
clkB Reset synchronizer could
be involved in RDC issue
Reset
synchronizer

ckA rstB_
rstA_ Synchronous
deassertion

• Reset synchronizers ensure synchronous deassertion (release) of asynchronous resets

– Avoids recovery-removal violations
• Deassertion of asynchronous resets is not an RDC problem
– Reset deassertion always depends on clock edge → CDC problem
– Synopsys CDC tools check for reset deassertion (can also be enabled in VC SpyGlass RDC)

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Types of Asynchronous Resets

Power On /
System
Hard
Power
Resets Domain

Functional /
Software
Configuration

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 Reset Verification Challenges

Asynchronous
No Synchronization of Incorrect Reset
Reset Assertion Reset Glitch
Reset de assertion Functionality
(RDC)

Metastability Incorrect
Metastability Metastability due to spurious Functional
RDCs State

Power
Clock Glitch Functionality
Dissipation

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Reset Domain Crossing Design Techniques
rst1 rst2

D Q D Q RSTB RSTB
D Q D Q

QB QB

RSTB RSTB

clk
CGC
rst1 rst2 qualifier
Reset Assertion Order
Clock Gating Method

rst1 qualifier rst2

RSTB RSTB
D Q D Q

clk

Gate Based Method

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Reset Relationship
Time

Describes reset t=0 t1 t2=x+t1 t3=x+t2

Destination assertion order
rst1,rst2 rst3,rst4 rst5
Source
rst1,rst2
to_rst from_rst

rst3, rst4 Src Dest

Unsafe assertion
flop order flop
rst1 rst3

rst5
Source
Destination
Src Safe assertion Dest
flop
Constraints to describe Reset Relationships flop order
rst5 rst3
set_rdc_define_assertion_sequence –from {rst5} –to {rst3 rst4 rst1 rst2}

set_rdc_define_assertion_sequence –from {rst3 rst4} –to {rst1 rst2}

set_reset_groups -name rst_grp1 -group {rst3 rst4} Dest

Src Same group
flop resets flop
set_reset_groups -name rst_grp2 -group {rst1 rst2}
rst3 rst4

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Reset-to-Clock Assertion Order for Noise Reduction

FF1 FF2
q1 d2 q2
D Q D Q

QB QB
Clock de-asserted
RSTB RSTB

rst1 rst2 Reset asserted

CLK1
CLK2

Definition of assertion sequence

set_rdc_define_assertion_sequence –from_reset {rst1} –to_clock {CLK2}

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Regular RDC
Metastability Detection
1 2 3 4

Regular RDC • All flop to flop paths with different resets are
Crossings 4 potential candidates
• Restricts designer’s ability to constraint
Total Violations 4

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 Scenario Based RDC
Metastability Detection 1

Reset Name Power On Functional

mode Scenario1

rst1 (PoR) Y N

rst2 (Software/Func) Y Y

rst3 (Software/Func) Y Y

rst4 (PoR) Y N

Regular PoR Functional

RDC Mode1 Mode2 • Increases designer’s ability to constrain
Crossings 4 0 1
heavily (divide & conquer)
• Quickly go to real RDC bugs in functional
Total 4 1 mode
Violations

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Corruption detection in resetless flops

• Focus of Analysis moves from Metastability to Corruption

• Skip Reset-less Support:
– RDC can go through many layers of sequential reset-less elements
– RDC issue can be addressed at the final sequential end point that has reset control

SRC DST

CLK CLK
rst1 rst2
Pipeline, Math Engines, Simple Logic in between
DSP unit, Storage reset less flops

configure_rdc_corrupt -skip_resetless_flops true

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VC SpyGlass RDC Flow

RTL
VC SpyGlass RDC
Setup RDC Setup
Clock-Reset
Setup Provide Reset Assertion Order
Ignore Paths
RDC Qualifiers
Config RDC Sync

Violation Analysis
Database
Identify Sequential RDC Paths
(.vdb) Apply Ignore Path + Assert Sequence Reports
(.csv)
RDC Synchronization
(Observability + Blocking Controls)

Report Generation

Verdi Debug
(Violation Browser, Schematic)

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 Efficient, Low Noise Flow Design Information
- Reset Table (Modes)
Black Boxes - Reset categorization (PoR, Soft, test/debug etc.)
- report_link command to check - Reset assertion modes (Specification would
Glass boxes
Design Read Methodology provide relationships)
- Check Simon Messages Clean Options - Reasons for resetless flops if there is any in
- Reason for elab perf bottleneck design
.db models - Memories/ Analogs are provided in form of
- Memory, 3rd party IP macros liberty models (.db)
configure_rdc_corrupt options
Clock, Case Analysis, Clock Groups - report_rdc_on_cdc false
- sgdc (convert_sgdc_to_tcl)
Constraints RDC Checking - report_observable_cgc_destination true
- sdc (Make sure to get clean clock groups) (check_rdc –type
Reset Constraints (.tcl) corrupt) Reset Control Signals
- SoC/design specification provides initial set - set_rdc_qualifier
- Can Leverage Inference (regular RDC qualifiers)
(Do not recommend) - create_rdc_static
(Particular signals is at reset value when reset
- SETUP_RESET_UNDECL (create_reset) asserts)
- SETUP_RESET_CONSTANT_ACTIVE Design configure_rdc_qualifier
Review set_case_analysis, potential RTL bug - Change default behavior of qualifier
driving constants on resets Constraints,
Design Setup - Treat UPF isolation as rdc qualifier
- SETUP_RESET_CONV_MUX
(check_rdc –type setup) Debug - Treat src resets as qualifier
Use set_case_analysis, create_reset -tdr configure_rdc_formal
- SETUP_ASYNCRESET_UNUSED - Automatically find blocked paths, works only if
RTL bug blocking resets, check set_case_analysis design has this in built
- SETUP_RESET_OVERLAP Sign-Off Debug
Review for over constraining - Never debug paths, debug groups.
- SETUP_RESET_DRIVING_NON_ASYNC_PIN - Explore compress_rdc
Enable D->Q reset prop, re position resets (Use option based on customer methodology or
- Clean Missing Clocks, Clock Convergences start with reset grouping)

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VC SpyGlass RDC Command File Example
Loading Design and Running RDC checks
vc_static_shell> set search_path “<space separated list of
directories >”

vc_static_shell> set link_library “<space separated list of

libs>”

vc_static_shell> read_file -format verilog { List of source Design setup & read
file} –vcs { -work WORK –sv=2005 –error=noMPD} Leverage Existing DC
setup
vc_static_shell> elaborate <top level module>

vc_static_shell> configure_rdc_corrupt -report_bbox_destination - Same RTL, analysis &

false …… elaborate command
Configuring checks & - Same constraints / SDC
vc_static_shell> configure_rdc_qualifier -depth 2 …. / TCL scripts
vc_static_shell> set_rdc_qualifier -object <obj> ….
reading constraints
- Add reset / RDC
vc_static_shell> read_sdc common_consraints.sdc constraints and run RDC
vc_static_shell> read_sdc rdc_setup.tcl

vc_static_shell> check_rdc -type setup Running & reporting

RDC checks
vc_static_shell> check_rdc -type corruption
vc_static_shell> report_rdc
vc_static_shell> quit

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VC SpyGlass RDC Design Compiler and PrimeTime Compatibility
PT/DC commands supported and consistent
• Software modules shared with DC/PT all_clocks
all_inputs
set_false_path all_connected
set_fanout_load all_fanin
– TCL/CCI interface all_outputs
all_registers
set_ideal_latency
set_ideal_network
all_fanout
create_clock all_instances
– DB reader
set_ideal_transition
create_generated_clock set_input_delay get_attribute
create_voltage_area set_input_transition get_clock_network_objects
– Netlist parser current_design
delay_port_pin_list
set_level_shifter_strategy get_clock_relationship
set_load get_clocks
– Memory manager set_min_pulse_width
get_cells
set_logic_one
set_logic_zero
add_to_collection
get_lib_cells set_max_area remove_from_collection
get_lib_pins set_max_capacitance append_to_collection
get_libs set_max_delay define_user_attribute
• UPF functionality driven by same common get_nets
get_pins
set_case_analysis
set_clock_gating_check
get_timing_arcs
get_timing_paths
master specs in all Synopsys tools get_ports
group_path
set_clock_groups
set_clock_latency
set_sense
set_level_shifter_threshold set_cell_mode
– UPF cross-team effort for consistency max_case_voltage
set_clock_sense
set_clock_transition Non-SDC Commands
set_wire_load_model set_clock_uncertainty
set_min_capacitance set_data_check
set_min_delay set_disable_timing

• R&D Level collaboration with DC & PT R&D set_multicycle_path

set_wire_load_selection_group
set_drive
set_driving_cell

for consistent behavior of commands set_max_fanout

set_max_time_borrow
set_operating_conditions
set_output_delay
set_max_transition set_port_fanout_number
set_timing_derate set_propagated_clock
set_voltage set_resistance
set_wire_load_min_block_size set_wire_load_mode

SDC Commands
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Tool specific constraints (beyond SDC)
Additional constraints needed for CDC/RDC analysis
• Common SDC constraints through read_sdc
– e.g. create_clock, create_generated_clock, set_clock_groups, set_case_analysis, set_clock_sense …
etc. through read_sdc

• Source Tcl file consisting of additional constraints such as:

– create_reset, create_rdc_static, configure_rdc_corrupt, configure_rdc_qualifier

e.g.
read_sdc top_clocks.sdc // Add Standard SDC commands
read_sdc exception.sdc // Add Standard SDC commands
source rdc_setup.tcl // Additional constraints

This Photo by Unknown Author is licensed under CC BY

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VC Spyglass RDC Report Filtering

• Filter crossings on ignored paths using set_rdc_ignore_path

• Reported under RDC_CORRUPT_IGNORED tag
• Path to reset-less destinations can be ignored using –dest_no_reset

set_rdc_ignore_path –from dffr_1/o –to dffr_2/o

set_rdc_ignore_path –from_rst rst1 –to_rst rst2
set_rdc_ignore_path –from_rst rst1 –dest_no_reset

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Reset Order Viewer with VC SpyGlass RDC

• Reset Order Viewer, ROV for graphical

visualization of reset assertion sequence

• Syntax for assertion sequence definition:

set_rdc_define_assertion_sequence
-from <reset1_list>
-to <reset2_list>
-to_clk <to_clk_list>
-rising_edge <rising_edge>
-falling_edge <falling_edge>

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Native Integration with Verdi Debug View

Cross- Probing
With RTL, Hierarchy
view of Verdi

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 Native Integration with Verdi Debug
Schematic View, Locators & Debug Data
Schematic View with Color Coding
Purple: Src flop, reset
Golden: Dest flop, reset
Crossing: Orange

Locators
Quickly find src and dest object

Cross probing between

schematic and debug data

Debug data
Object name
Constraints
Reset / Clock domain data

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VC SpyGlass RDC
Powerful TCL debug
foreach reg1 $reg_list {
set reset_root_list [get_reset_roots -of_objects $reg1 ]
foreach_in_collection reset $reset_root_list {
set reset_name [get_attribute $reset name]
set name1 [get_resets $reset_name -filter {is_sync==true}]
set N1 [sizeof_collection $name1]
if {$N1 > 0} {
puts "$reg1/Q"
redirect -file rdc_dest_receiving_sync_reset.txt { puts "Register receiving
Sync reset: $reg1 with sync reset: $reset_name \n" } -append
set name2 [get_rdc_paths -to "$reg1/*" ]
set N2 [sizeof_collection $name2]
if {$N2 > 0} {
redirect -file rdc_dest_receiving_sync_reset.txt { puts "RDC destination
reg receiving Sync reset: $reg1 with sync reset: $reset_name \n" } -append
}
break
} Reset and RDC aware
}
}
commands and attributes

######## All registers and RDC destination receiving Sync reset########

Register receiving Sync reset: q1 with sync reset: srst1

RDC destination reg receiving Sync reset: q1 with sync reset: srst1

Register receiving Sync reset: q4 with sync reset: srst3

Register receiving Sync reset: q2 with sync reset: srst2

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VC SpyGlass RDC
Powerful Filtering and Waiver Mechanism
• Any field can be copy/pasted into a filter
• Wildcards and expressions use standard syntax
• Waivers can be built using the same expressions

report_rdc -tag RDC_CORRUPT_POTENTIAL -filter

{(SrcObject=~*or1200_du/dmr1/Q*)&&(DestObject=~*or1200_du/wp_latched/Q*)} -verbose

-----------------------------------------------------------------------------
RDC_CORRUPT_POTENTIAL (2 errors/0 waived)
-----------------------------------------------------------------------------
Tag : RDC_CORRUPT_POTENTIAL
Description : data corruption due to asynchronous reset assertion may be blocked before reaching the destination .
Violation : CDC:235
ReasonInfoList
ReasonInfo
ReasonCode : QUAL_CONVERGES_ASYNC_SRC
ReasonCodeMsg : [ERROR] Qualifier converges with another asynchronous source before gating logic
SrcObject : or1200_top/or1200_du/dmr1/Q[2:19]
DestObject : or1200_top/or1200_du/wp_latched/Q[0:9]
SrcResetInfoList
SrcResetInfo
ResetName : wb_rst
ResetObject : wb_rst
DestResetInfoList
DestResetInfo
ResetName : ‘sticky_rst'

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VC SpyGlass Lowers Noise
Smarter debug using grouping techniques

Violation Spread Sheet

Insightful Violation View

Unique src/dest based grouping,
Object type based grouping

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Thank You