Design Trade-offs of a 6T FinFET SRAM Cell in the Presence of Variations

Eric Chin, Mohan Dunga

ABSTRACT
Increased process variation in short channel transistors
is reducing the robustness of bulk-FET based SRAM.
FinFETs based SRAM designs have been proposed as an
alternate solution. In this work, an analysis of SRAM
failure mechanisms in the presence of variations and
corresponding design trade-offs are reviewed. We propose
to extend the existing analytical models for bulk-FET
SRAM failure rates to FinFET based SRAM. The impact of
systematic variations on the SRAM failure rates and design
trade-offs in the presence of process variations will also be
examined.

1 INTRODUCTION Figure 1: The 6T SRAM Cell

The semiconductor industry is facing technological In this paper, the work presented in [1-5] will be
challenges to maintain the constant bulk CMOS scaling. To reviewed. An approach to study the systematic inter-die and
meet the challenge, the industry has proposed FinFETs as intra-die variations through the use of a FinFET compact
possible device architecture. Process variations in the model will be presented. A possible design approach to
fabrication of short channel FinFETs introduce significant optimize SRAM performance in the presence of variations
variations in on/off currents resulting in a variable circuit will also be outlined.
performance.
SRAM is built using the minimum size transistors to 2 BULK-FET 6T SRAM
minimize area making it highly vulnerable to process
variations. Memory designs are optimized for 6 sigma 2.1 Analytical Modeling of SNM of bulk-FET based
variations. SRAM failure can occur due to an increase in SRAM
access time (access failure AF), failure to write a bit into the Due to the similarity in the operation and the failure
cell (write failure WF), accidental writing into memory mechanisms of bulk-FET based and FinFET-based SRAM,
during read (read failure RF) or loss of stored bit in standby it is important to review the bulk-FET based works.
mode (hold failure HF). In scaled technologies, an optimal In [1], a semi-analytical approach is used to calculate
design strategy of SRAM should consider minimization of the SNM during a read access. To find the SNM, analytical
area and access times in conjunction with reducing the model for the inverter transfer characteristics is developed.
failure probabilities due to variations. The edge of the largest possible square nested between the
Several efforts have been made in examining the effects transfer characteristics is calculated to represent SNM of
of variations on SRAM failure rates for bulk CMOS the memory cell (Fig. 2). Transistors which are ON during
technologies [1], [2] and FinFET technologies [4], [5], [6].
Threshold voltage (Vth) variation due to Random Dopant
Fluctuations (RDF) is the prime contributor for bulk FET
variations, whereas Line Edge Roughness (LER) and Body
Thickness (Tsi) variations are prime contributors for
FinFETs. Failure rates have been studied using Monte
Carlo simulations or through semi-analytical models. All
the works looked at the worst case failure probability by
assuming random mismatch between all the 6 transistors
(Fig.1). However, there has been little focus on studying the
impact of systematic variation and optimization of FinFET-
based SRAM design in the presence of variations.
Figure 2: SNM of SRAM cell defined as the edge of the
largest possible square
the read operation are identified and Kirchoff’s law is used leakage currents flowing through the access transistors, the
to derive the transfer characteristics. To formulate the access time and its distribution due to Vth variation is
problem, a regional I-V model is used which captures the calculated. Read failure rate is the probability of the node
mobility degradation due to vertical electrical field and storing “0” rising to a voltage (Vread) greater than the
velocity saturation. The SNM expression is an explicit switching threshold of the adjacent inverter pair (Vsw). The
function of gate length and threshold voltages of different voltages Vread and Vsw are calculated through analytical
transistors, enabling the study of the change in SNM to due modeling following [1]. Access and pull down FETs decide
to variations in the individual transistors. Using a certain Vread while pull-up and pull-down FETs decide Vsw
stochastic distribution of Vth due to RDF, the SNM change indicating that RF is most sensitive to NMOS Vth variation.
of 6-T cell was calculated through summing of SNM For a successful write operation, when writing a bit (for ex.
change due to Vth variation of each individual transistor. “1”) into a node, the node voltage after write (Vwrite) should
During a read with a bit “0”, the ratio of strength of pull be larger than switching threshold of adjacent inverter pair
down transistor and access transistor determines the (Vsw). WF can then be estimated through the probability of
increase in node voltage where bit “0” was stored. As a Vwrite < Vsw similar to RF. However, in [2] a dynamic
result, read SNM is expected is to be more sensitive to approach was taken wherein time required for the node
access and pull down transistors which is consistent with being written to attain Vsw is calculated and compared with
the findings in [1] using the analytical SNM expressions. write time. It is not very clear why a static approach was
They estimated the SNM variations at T = 398K for worst taken to calculate RF but a dynamic approach was chosen
case analysis. One of the solutions suggested to reduce the for WF. During the standby mode, Vdd is lowered to reduce
effects of variations was to use longer channel lengths. leakage power. However, this may cause the node storing
However, this was not analyzed to see the trade-off in bit “1” to go (Vhold1) below the switching threshold (Vsw) of
SRAM performance and improvement in robustness. This the adjacent inverter pair leading to loss of information. HF
is a possible design strategy which will be explored in this is then defined as the probability of Vhold1 < Vsw, where
work. both the voltages are calculated from the analytical I-V
Some improvements can be made to the I-V model used model [1]. Using the estimates of failure rates, the sign of
in the analysis. Source/drain resistance which is significant Vth shifts in the 6 transistors needed to cause a particular
for narrow short channel transistors seem to be neglected in failure is shown. The overall failure probability is
the model formulation and they can change the I-V calculated from the individual failure rates and is used to
characteristics significantly. Output conductance change estimate the rate of a memory column failure. For a given
in the saturation region due to channel length modulation number of redundant columns (NRC) in a memory block,
and DIBL seems to be missing which can underestimate the the failure of the block is given by the probability that more
drain current for sub-45nm transistors significantly. The than NRC columns are not functional. Longer columns
regional I-V model developed here can be used for increase failure rate of the column, while shorter columns
modeling SNM of FinFETs through the extraction of increase the number of columns again leading to increased
corresponding electrical parameters for FinFETs. The failure rates of memory block. The model was used to
SNM expression derived is function of gate length of Vth examine the width sizing to improve the failure rates.
of all 6 transistors. By changing the Vth of all transistors Increases pull down FETs widths improves the RF and AF.
systematically, an estimate of the impact of systematic Increasing the width of access transistor improves the WF
variation on SNM can be shown. and AF at a small expense of RF. Increasing the width of
pull up FET improves the HF and RF at the expense of WF.
2.2 Failure Probabilities of SRAM Cell These are useful conclusions which can be used in selecting
width ratios in presence of variations.
Instead of looking only at SNM of the cell, the The analysis in [2] is an extension of [1] through
probability of SRAM failure due to the four failure estimation of different failure rates. While calculating
mechanisms AF, RF, WF, and HF were estimated in [2]. Vth access time, the gate leakage of the two access transistors
variation due to RDF was considered as the only source of was assumed equal. However, due to different biasing
variations. To look at the impact of variations on sizing, the conditions between the two access transistors, the gate
variance of Vth was made a function of transistor size, leakage can differ by 3x. For sub-45nm nodes, since gate
since larger sized transistors exhibit less Vth variation. leakage is more than 50% of drain leakage, it is necessary
Starting from a numerical approach to solve for the failure to account for the difference in gate leakages while
probabilities of individual memory cells, memory failure calculating the access time to estimate AF rates. Based on
rates of a block of memory was studied. the RF estimation, an interesting observation can be noted
The individual failure rates were calculated by between systematic and random variation. When Vth is
estimating the currents leading to charging/discharging of lowered for both pull down FETs, both Vtrip and Vsw will
the nodes involved. In access mode, differential voltage on decrease. However, if the Vth move in opposite directions
bit lines is generated through a difference in current flowing due to random mismatch, Vtrip and Vsw will move in
through the two access transistors. By a careful inclusion of opposite direction either improving the failure rate or
making it worse compared to systematic variation case. Using only the access time for benchmarking the
Even though [2] mentioned the study of inter-die variation, variability is inadequate. As observed in [2], the variation in
the work focused on worst case estimates through coupling pull-up PMOS devices has a small impact on the access
of intra-die random mismatch with inter-die variation. The time variations while it affects the read/write margins
net failure rate was used to study the impact of width tuning significantly. Read failure or SNM is a better metric to
to improve robustness. However, the analysis did not gauge the effect of variability arising from all the 6
highlight its impact on memory performance, mean access transistors in the SRAM cell. An improvement to their
time, write time, etc and also the loss in area due to comparison will involve using more physical estimates of
increased widths. A similar analysis based on L variation Vth distributions for bulk-FETs and FinFETs.
will also be interesting as it can improve the power Variations in the electrical parameters of FinFETs have
consumption and HF also. been analyzed [4] as a function of channel doping, TSi and
Lg. The analysis was done using device simulations in the
3 VARIATIONS IN FINFETS presence of quantum effects and mobility degradation. For
thin body (TSi = 10nm) with moderate doping, the Vth of
Challenges in the continued scaling of planar bulk FinFETs changes about 20mV when doping increases from
CMOS devices include heavy halo doping to compensate 1017cm-3 to 1018cm-3. For thicker bodies, where halo doping
for degraded short channel effects, reduced carrier is still being used to reduce SCE, the change in Vth can be
mobilities in the channel, increased source-drain leakage higher highlighting the importance of RDF even for
current, random dopant fluctuations, and critical dimension FinFETs. For thinner bodies where QME are important, Vth
control. FinFETs (Fig. 3) have been proposed as changes by about 35mV/nm of TSi. For thicker bodies, the
alternatives to bulk FETs due to their stronger electrostatic change in Vth due to variation in TSi will be smaller due to
control over the channel resulting in improved short less QME. Change in Vth due to LER will be smaller in
channel behavior. In addition, due to light body doping FinFETs than bulk-FETs because of the tighter control of
used in FinFETs, the absence of RDF minimizes the SCE.
amount of process variation and on/off current for short In summary, TSi and Lg variations are important for thin
channel lengths has smaller spread. In [3], variations in body FinFETs. The absence of RDF makes them robust to
bulk CMOS and FinFET technologies are compared for random mismatch. However, for thicker body FinFETs, the
both logic and memory applications. RDF becomes important due to the necessity of adding halo
6T SRAM cell is used to benchmark the variability of doping.
FinFETs for memory against bulk technology for 45nm and
32nm nodes. Spread in access time was used a metric to
perform the benchmarking. It was found that FinFET based 4 FINFET BASED SRAM
SRAM showed smaller spread in access times. For
benchmarking spread in logic, FO4 delays were simulated. 4.1 Technology and Design Co-optimization of 6T
FinFET based FO4 chains showed a tighter spread. For the SRAM
simulations, 3σ Vth deviation of 15% was used for both The better SCE control and smaller RDF in FinFETs
FinFET and bulk-FETs. This ignores the fact that RDF are make them ideal candidate for scaling SRAM. Two
absent in FinFETs which leads to a tighter Vth distribution different approaches to optimize the 6T SRAM cell design
for FinFETs. :Device-Vt and Device-Vt-Vdd are presented in [5]. Each
of these approaches includes FinFETs with different
combinations of fin dimensions, oxide thickness, and gate
workfunctions that keep the drive current and short channel
effect (SCE) constant. For each device structure, the
tradeoffs between cell area, read and write access times,
soft error immunity, and stability are explored.
The SRAM cell design used in this analysis includes 6
transistors with two fins per transistor. A slightly larger L is
used for the access transistor to increase the beta ratio of the
cell. Because the area of the cell is determined by the
number of fins and the number of fins is constant, the cell
area is constant for all the device structures explored in this
paper. Since the drive current is constant for all the devices
in design space, the read access time of the transistor does
not change with device dimensions. The write access time
of the cell increases with fin size due to the increased
Figure 3: FinFET : alternative to bulk CMOS for scaling capacitance at the storage nodes.
 The immunity to soft errors is determined through a While this paper presents a compelling argument that
comparison of stored charge versus the critical charge there exist optima for both device and circuit
needed to flip the state of the cell. As the fin size increases, characteristics, the analysis presented is of more utility
stored charge, and consequently, soft error immunity, from a process optimization standpoint. Through
increases. This simple model does not account for the optimization of device parameters, SRAM design
charge provided by the inverters to recover from an upset at characteristics can be improved to reduce the impact of
the storage node. process variations and improve operating characteristics.
The stability of the cell is assessed through an analytical Once this point has been reached, further optimization at
approach instead of static noise margin analysis. An the circuit level can further reduce the impact of process
alternative metric, Vmargin, is defined to capture the ability of variations.
the cell to prevent a flipping of its state. This is a function
of the threshold voltage and hence the variations in Vth are 4.2 Design Trade-offs in 6T and 4T SRAM
explored. These variations occur from physical variations in The design tradeoffs of both 6T and 4T SRAM cell
L, Tox, and TSi. design using back gated and double gated FinFETs are
The paper cites other works indicating that Vth variations examined in [6]. Common design metrics include area, read
occurring from Tox variations is insignificant and can be and write stability, access time, and power. The FinFET
ignored. However, variations from the physical gate length was designed using device parameters similar to that of the
and body thickness cannot be ignored. The 3σ values bulk-Si transistor, with the exception of channel doping.
associated with these variations are defined to be 10% of The layout of the FinFET was created with one fin per
the nominal physical gate length. It is then shown that the transistor. Pull down transistors were rotated to exploit the
static noise margin is maximized by increasing the fin increased mobility along the (100) plane and hence
dimensions (TSi and Hfin). increasing the effective beta ratio of the cell.
An analysis of source-drain and gate leakages is then The static noise margin for both cells was determined
presented. Increasing TSi allows for higher threshold through butterfly plots of the SRAM cells. A conventional
devices that decrease source drain leakage. However, to bulk-Si SRAM cell with a beta ratio of 1.5 was compared to
compensate for degraded control of the channel, the oxide the 1 fin per transistor FinFET SRAM cell, and a 22%
thickness must be decreased, increasing the gate leakage. improvement in the read SNM was achieved. Rotation of
Therefore both sources of leakage change in opposite the pull down transistors yielded a further 15%
directions. It is also shown that there exists an optimal improvement of SNM at the cost of increased cell size.
minimum to reduce the overall leakage current. Adding additional fins for the pull down transistors
The primary objective of this paper is the optimization increases cell size and read margin while decreasing write
of FinFET device parameters for SRAM circuit design margin.
applications. One of the shortcomings is that the all of the A back gated biasing scheme is introduced for
FinFET devices examined are designed for the same short independently controlled double gate FinFETs (Fig. 4). The
channel effect. For example, a thin body device would have storage nodes are connected to the back gates of the
a thick oxide while a thick body device would have a thin connected bias transistors to control the threshold of the
device. This is not representative of any device created with access transistors and thus dynamically adjust the threshold
the latest process technology, where the priority is to voltage of the access transistors. A 71% read margin
minimize the oxide thickness to minimize the short channel improvement is demonstrated with this circuit topology.
effects. However, the write margin decreases because the threshold
Stability analysis in this paper is presented analytically voltage of the access transistor decreases as the storage
without the generation of butterfly curves, and is limited to node is pulled low.
read noise margin. An alternative metric of static noise
margin is presented and is related to variations in threshold
voltage. One concern is that the authors do not mention the
effects of random dopant fluctuations on the threshold
voltage, instead attributing Vth variations primarily to L and
TSi.
Another concern is that the amount of variation in TSi is
assumed to be 10% of the L, which may be too large if the
fins are defined by spacer lithography. These values of
physical variation are used to perform a worst case analysis
of static noise margin where worst case thresholds are
assigned to the transistors. The analysis that they present
could be enhanced through modeling of systematic
variations instead of assuming a random mismatch between Figure 4: Schematic of 6T SRAM cell with feedback
transistors.
 Variations in random dopant fluctuations, L, and Tsi, are extend the analysis to study systematic variations. A
studied through random Monte Carlo simulations in the physics based Double-gate model (BSIM-MG) compact
device simulator, Taurus. 3σ variation in both L and Tsi, model will be used to estimate the variations in the
estimated as 10% of L. The distributions of static noise electrical parameters of FinFET due to variations in the
margins for bulk-Si, FinFET, and FinFET with feedback process parameters (L, Tsi, and doping). For FinFETs with
SRAM designs are calculated. The FinFET static noise Tsi 20nm, Hfin 30nm and Lg 32nm, for a background doping
margins have a standard deviation of 5-7mV, which is of 1e17cm-3, there are 2 dopants in the fin. Due to RDF, if
much tighter than the bulk-Si implementation with a there are 4 dopants, it is equal to 2x increase in body doping
corresponding standard deviation of 16nm. and can yield threshold voltage shift of more than 10mV.
The paper analyzes four different 6T FinFET SRAM This number will increase in the presence of halo doping or
designs with variations on back biasing, rotation of fins, due to diffusion of dopants from S/D into the channel
and number of fins. One of these designs included a 45 region. As a result, we will consider RDF in FinFETs
degree rotation of the NMOS pull down transistor. While through Poisson statistics (because it is a discrete event).
this is a unique and novel attempt to improve the noise Analytical models exist for bulk-FET SRAM failure
margin, the tradeoffs of increased cell area (13%) and rates. We will try to extend the approach towards analysis
increased manufacturing complexity must be considered. of the failure rates for FinFET based SRAMs. The different
The state of the art lithography steppers would require an failure SRAM mechanisms will be analyzed. SRAM can be
additional exposure step to print a 45 degree feature. The made robust to variations through changing Tsi, Lg or
complexity and cost of this additional step make this design adding fins at the expense of common metrics such as area
highly infeasible. and access time. We will explore the trade-offs involved in
In contrast, the back gated 6T SRAM design shows this analysis.
promise, especially because the effective width quantization
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5 FUTURE WORK
Most of the current efforts analyzing the variability in
SRAM designs focused on random mismatch among the 6
transistors in the 6T SRAM cell. In our work, we intend to