Power

Ref: Weste-Harris
 Outline
 Power and Energy
 Dynamic Power
 Static Power

7: Power CMOS VLSI Design 4th Ed. 2

 Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P(t )  I (t )V (t )

T
 Energy: E   P(t )dt
0
T
 Average Power: E 1
Pavg    P(t )dt
T T 0

7: Power CMOS VLSI Design 4th Ed. 3

 Power in Circuit Elements
PVDD  t   I DD  t VDD

VR2  t 
PR  t    I R2  t  R
R

 
dV
EC   I  t V  t  dt   C V  t  dt
0 0
dt
VC

 C  V  t dV  12 CVC2
0

7: Power CMOS VLSI Design 4th Ed. 4

 Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
EC  12 CLVDD
2

– But energy drawn from the supply is

 
dV
EVDD   I  t VDD dt   CL VDD dt
0 0
dt
VDD

 dV  C V
 CLVDD 2
L DD
0

– Half the energy from VDD is dissipated in the pMOS

transistor as heat, other half stored in capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 6

 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

7: Power CMOS VLSI Design 4th Ed. 8

 Switching Power
T
1
Pswitching   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD
 Tfsw CVDD  VDD
T iDD(t)
fsw

 CVDD 2 f sw
C

7: Power CMOS VLSI Design 4th Ed. 9

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor

 Dynamic power:
Pswitching  a CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 10

 Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component

7: Power CMOS VLSI Design 4th Ed. 11

Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

7: Power CMOS VLSI Design 4th Ed. 12

Dynamic Power Example
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 l
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 l
• Activity factor = 0.02
– 1.0 V 65 nm process (λ = 25 nm)
– C = 1 fF/mm (gate) + 0.8 fF/mm (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 13

 Solution
Clogic   50 106  12l  0.025m m / l 1.8 fF / m m   27 nF
Cmem   950 106   4l  0.025m m / l 1.8 fF / m m   171 nF

Pdynamic  0.1Clogic  0.02Cmem  1.0  1.0 GHz   6.1 W

2

Pswitching  a CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 14

 Dynamic Power Reduction

P
 switching  a CV 2
DD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency

7: Power CMOS VLSI Design 4th Ed. 16

 Activity Factor Estimation
 Let Pi = Prob(node i = 1)
– Pi = 1-Pi
 ai = Pi * Pi
 Completely random data has P = 0.5 and a = 0.25
 Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
 Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically a ≈ 0.1

7: Power CMOS VLSI Design 4th Ed. 17

 Switching Probability

7: Power CMOS VLSI Design 4th Ed. 18

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have probabilities PA = PB = PC = PD = 0.5.

7: Power CMOS VLSI Design 4th Ed. 19

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5

7: Power CMOS VLSI Design 4th Ed. 21

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5

7: Power CMOS VLSI Design 4th Ed. 23

 Clock Gating
 Clock gating ANDs a clock signal with an enable to
turn off the clock to idle blocks.

7: Power CMOS VLSI Design 4th Ed. 24

 Capacitance
 Gate capacitance
– Fewer stages of logic
– Small gate sizes
 Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than complex gates

7: Power CMOS VLSI Design 4th Ed. 26

 Voltage / Frequency
 Run each block at the lowest possible voltage and
frequency that meets performance requirements
 Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains

 Dynamic Voltage Scaling

– Adjust VDD and f according to
workload

7: Power CMOS VLSI Design 4th Ed. 27

 Static Power
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices

7: Power CMOS VLSI Design 4th Ed. 28

 Static Power Example
 Revisit power estimation for 1 billion transistor chip which
contains 50M logic transistors and 950M memory transistors.
Logic transistor average width is 12λ and memory transistor
average width is 4λ.
 Estimate static power consumption.

– Subthreshold leakage
• Normal Vt: 100 nA/mm
• High Vt: 10 nA/mm
• High Vt used in all memories and in 95% of logic gates
– Gate leakage 5 nA/mm
– Junction leakage negligible

7: Power CMOS VLSI Design 4th Ed. 29

 Solution

Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

Wnormal-Vt   50 106  12l  0.025m m / l  0.05   0.75 106 m m

Whigh-Vt   50 106  12l  0.95    950 106   4l    0.025m m / l   109.25 106 m m

I sub  Wnormal-Vt 100 nA/m m+Whigh-Vt 10 nA/m m  / 2  584 mA

 
I gate   Wnormal-Vt  Whigh-Vt  5 nA/m m  / 2  275 mA
 
Pstatic   584 mA  275 mA 1.0 V   859 mW

7: Power CMOS VLSI Design 4th Ed. 30

 Subthreshold Leakage
 For Vds > 50 mV Typical values in 65 nm
Vgs  Vds VDD   k Vsb Ioff = 100 nA/mm @ Vt = 0.3 V
I sub  I off 10 S Ioff = 10 nA/mm @ Vt = 0.4 V
Ioff = 1 nA/mm @ Vt = 0.5 V
 = 0.1
 Ioff = leakage at Vgs = 0, Vds = VDD
k = 0.1
S = 100 mV/decade

7: Power CMOS VLSI Design 4th Ed. 32

 Stack Effect
 Series OFF transistors have less leakage
– Vx > 0, so N2 has negative Vgs
 Vx VDD  Vx   VDD Vx  VDD   k Vx

I sub  I off 10 S  I off 10 S

    
N2 N1
Series OFF
VDD transistors
Vx 
1  2  k demonstrating
 1  k  the stack effect
VDD  
 1 2  k  VDD
 
I sub  I off 10 S
 I off 10 S

– Leakage through 2-stack reduces ~10x

– Leakage through 3-stack reduces further

7: Power CMOS VLSI Design 4th Ed. 33

 Leakage Control
 Leakage and delay trade off
– Aim for low leakage in sleep and low delay in
active mode
 To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input vector control in sleep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode

7: Power CMOS VLSI Design 4th Ed. 34

 Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD

7: Power CMOS VLSI Design 4th Ed. 35

 Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other
leakage is small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)

7: Power CMOS VLSI Design 4th Ed. 37

 Power Gating
 Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block

 Voltage drop across sleep transistor degrades

performance during normal operation
– Size the transistor wide enough to minimize
impact
 Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
7: Power CMOS VLSI Design 4th Ed. 38