Amrita School of Engineering

Bengaluru Campus

19EAC181 Digital System Lab

II Semester

Lab Manual

Kasavanhalli, Carmelaram P. O., Bengaluru – 5600035

 Vision and Mission of the Institute

Vision To be a global leader in the delivery of engineering education,

transforming individuals to become creative, innovative, and socially
responsible contributors in their professions.
M1 To provide best-in-class infrastructure and resources to achieve
excellence in technical education
M2 To promote knowledge development in thematic research areas that
have a positive impact on society, both nationally and globally
M3 To design and maintain the highest quality education through active
engagement with all stakeholders – students, faculty, industry, alumni
Mission
and reputed academic institutions
M4 To contribute to the quality enhancement of the local and global
education ecosystem
M5 To promote a culture of collaboration that allows creativity, innovation,
and entrepreneurship to flourish
M6 To practice and promote high standards of professional ethics,
transparency, and accountability
 Vision and Mission of the Department
To provide a value-based learning environment for producing
engineers with a blend of technical skills, moral values and leadership
Vision
qualities in the field of Electronics, Communication and Computing
channelized towards technological advancement to cater to the needs
of the industry and the society.
M1 Achieving excellence in teaching and learning with an emphasis
on fundamental knowledge and hands-on exposure to match the
state-of-the-art in technology.
M2 Providing an environment for core competency development
Mission and enhancing quality research in emerging areas.
M3 Facilitating professional growth to the students for higher
education and career in industry and academia
M4 Imbibing the essence of human values, ethics and
professional skills to sustain socio -economic development
 Amrita Vishwa Vidyapeetham
Amrita School of Engineering, Bengaluru
Department of Electronics & Communication Engineering
19EAC181/ Digital System Lab
II Semester
List of Experiments

Course Outcomes
CO1: Ability to familiar with digital gates and implementing Boolean logics.
CO2: Ability to implement ALU circuits.
CO3: Ability to construct and analyze sequential circuits.
CO4: Ability to construct the synchronous and asynchronous circuits.

CO/P PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO

O 1 2 3 4 5 6 7 8 9 0 1 2 1 2
CO1 3 2 - - - - - - - - - - 2 -
CO2 3 2 2 - - - - - - - - - 2 -
CO3 3 2 2 - - - - - - - - - 2 -
CO4 3 2 2 - - - - - - - - - 2 -

1)Study and Realization of Basic Logic Gates.

2)Design and Realization of Basic Gates using Universal Logic Gates.
3)Design, Simplification and Realization of given Boolean Expressions.
4)Design and Realization of Adders and Subtractors.
5)Study and Realization of Parallel Adder cum Subtractor.
6)Design and Realization of Code Converters.
7)Study and Realization of 1-bit, 2-bit, 4-bit and 8-bit Magnitude Comparators.
8)Study and Design of Multiplexers and Demultiplexers.
9)Study, Design and Verification of Flip-flops.
10)Study, Design and Implementation of Asynchronous & Synchronous Counters and Shift
Registers.
 19EAC181-Digital System Lab
Lab Experiment 1

Aim: Study and Realization of Basic Logic Gates.

Tool used: Microwind DSCH2

Study and Realization of Basic Logic Gates

2 –Input NOR Gate->7402LS
Logic Gates From the 74 series TTL IC Family
 19EAC181-Digital System Lab
Lab Experiment 2

Aim: Study and Realization of all Logic Gates using Universal Logic Gates only.

Tool used: Microwind DSCH2

Study and Realization of Basic Gates using Universal Logic Gate

EXERCISE: Try XNOR GATE USING NAND GATE and XOR GATE USING NOR GATES.
 19EAC181-Digital System Lab
Lab Experiment 3

Aim: Study, Simplification and Realization of given Boolean Expression

f (a, b, c) = Ʃ m (2,3,5,6,7)
i) Using basic gates
ii) SOP Using NAND gates only
iii) SOP Using NOR gates only
iv) POS Using NAND gates only
v) POS Using NOR gates only
vi) Compare the implementations and analyze.
Tool used: Microwind DSCH2
Study, Simplification and Realization of given Boolean Expression
SOP Implementation - Simplification using Boolean algebra:
f (a, b, c) = Ʃ m (2,3,5,6,7)
= a’bc’ + a’bc + ab’c + abc’ + abc
= a’bc’ + a’bc +ab’c +abc +abc’ + abc {x + x = x}
= a’b(c’+c) + ac(b’+b) + ab(c’+c) = a’b + ac+ ab {x + x’ =1}
= b + ac
 POS Implementation - Simplification using Boolean algebra:
f = b +ac
f = (a + b). (b + c)

Assignment Lab 3 :
Simplify the Boolean function F1(w, x, y, z) = (1, 2, 4, 6, 9, 10, 12, 14) and design a circuit with 2-
input NAND gates only to realize the function. Simplify the same Boolean function F1 to the
POS form and design a circuit with 2
 19EAC181 - Digital System Lab
Lab Experiment 4

Study and Realization of Adders and Subtractors

Aim: To study and realize half adder, full adder, half subtractor and full subtractor.

Tool used: Microwind DSCH2

Study and Realization of Adders and Subtractors

Half adder-
A half adder is used to add two 1-bit number. The output of the system is sum and carry-out.

Truth Table:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0

1 1 0 1

Logical Expression:
𝑆𝑢𝑚 = 𝐴′ 𝐵 + 𝐴𝐵 ′ = 𝐴 ⊕ 𝐵
𝐶𝑎𝑟𝑟𝑦 = 𝐴. 𝐵

Logic Diagram:
Full adder-
A full adder is used to add three 1-bit number. The output of the system is sum and carry-out.

Truth Table:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logical Expression:
Sum = A’B’C + A’BC’ + AB’C’ + ABC
= A’ (B’C +BC’) + A (B’C’ + BC)
= A’ (B⊕ 𝐶) + 𝐴(𝐵 ⊕ 𝐶)
Sum = 𝐴 ⊕ 𝐵 ⊕ 𝐶

Carry = A’BC + AB’C + ABC’ + ABC

= A’BC + ABC + AB’C + ABC + ABC’ + ABC
= (A’ + A) BC + (B’ + B) AC + (C’ + C) AB
= BC + AC + AB
Carry = AB + BC + AC

Logic Diagram:
Full adder using Half adders:

Half subtractor-
The half subtractor is a building block for subtracting two 1-bit numbers.

Truth Table:

Logical Expression:

Logic Diagram:
Full subtractor-
The full subtractor is a combinational circuit which is used to perform subtraction of three input
bits.

Truth Table:
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Logic expression:
Diff = 𝐴 ⊕ 𝐵 ⊕ 𝐶

Borrow = A’B + A’C + BC

Logic Diagram:
 19EAC181 - Digital System Lab
Lab Experiment 5

Code Converters

Aim: To study and realize binary to gray code converter and vice versa.

Tool used: Microwind DSCH2

Binary to Gray Code Converter

Design:
A binary code represents text, computer processor instructions, or any other data using a two-
symbol system. The two-symbol system used is often "0" and "1" from the binary number system.

The reflected binary code, also known just as reflected binary or Gray code after Frank Gray, is
an ordering of the binary numeral system such that two successive values differ in only one bit.

Conversion Procedure:
We have a binary number 01001 which we wish to convert to gray code-

Truth Table:

Logical Equation:
g3 = Ʃm (8,9,10,11,12,13,14,15)
g2 = Ʃm (4,5,6,7,8,9,10,11)
g1 = Ʃm (2,3,4,5,10,11,12,13)
 g0 = Ʃm (1,2,5,6,9,10,13,14)

K-Map Simplification:

Logic Diagram:

Gray to Binary Code Converter

Conversion Procedure:
Truth Table:

Logic Equation:
b3 = Ʃm (8,9,10,11,12,13,14,15)
b2 = Ʃm (4,5,6,7,8,9,10,11)
b1 = Ʃm (2,3,4,5,8,9,14,15)
b0 = Ʃm (1,2,4,7,8,11,13,14)

K-Map Simplification
Logic Diagram:
 19EAC181 - Digital System Lab
Lab Experiment 6

Code Converters

Aim: To study and realize BCD to Excess-3 code converter and vice versa.

Tool used: Microwind DSCH2

BCD to Excess-3 Code converter

Design:
In computing and electronic systems, binary-coded decimal is a class of binary encodings of
decimal numbers where each digit is represented by a fixed number of bits, usually four or eight.
Excess-3 codes are unweighted and can be obtained by adding 3 to each BCD digit then
it can be represented by using 4-bit binary number for each digit.

Conversion Procedure:
To Find the Excess-3 code for the BCD representation of 53. According to excess-3 code we need
to add 3 to both digit in the BCD number then convert into 4-bit binary number for result of each
digit. Therefore, Result = 53+33=86 =1000 0110, which is required excess-3 code for given
number 53.

Truth Table:

Logical Equation:
w = Ʃm (5,6,7,8,9) + d (10,11,12,13,14,15)
x = Ʃm (1,2,3,4,9) + d (10,11,12,13,14,15)
y = Ʃm (0,3,4,7,8) + d (10,11,12,13,14,15)
z = Ʃm (0,2,4,6,8) + d (10,11,12,13,14,15)
The logical expressions have to minimized considering the don’t care conditions

K-Map Simplification:
Logic Diagram:
 Excess-3 to BCD Code converter
Truth Table:

Logic Equation:
A = Ʃm (11,12) + d (0,1,2,13,14,15)
B = Ʃm (7,8,9,10) + d (0,1,2,13,14,15)
C = Ʃm (5,6,9,10) + d (0,1,2,13,14,15)
D = Ʃm (4,6,8,10) + d (0,1,2,13,14,15)

K-Map Simplification:
Logic Diagram:
 19EAC181 - Digital System Lab
Experiment - 7
Study and Realization of Magnitude Comparator
Aim:
To study and realize 2-bit Magnitude Comparator.

Tool Used:
Microwind DSch2

Design:
A 2-bit comparator compares two binary numbers, each of two bits and produces their relation
such as one number is equal or greater than or less than the other.

Truth Table:

K-Map Simplification:
Logic Diagram:
 19EAC181 - Digital System Lab
Experiment - 8
Study and Realization of Parallel Adder/Subtractor
Aim:
To study and realize 4-bit parallel adder/subtractor.

Tool Used:
Microwind DSch2

Design:
A parallel adder/subtractor is a system consists of n full adders connected in series for an n bit
addition. The inputs for the system is two n bit numbers and carry-in, output for the system is n
bit sum and carry-out.

Logic Diagram -
Fig. 1 is for n bit parallel adder/subtractor, convert this for 4-bit and implement. Fig. 2 depicts
the internal realization of an n bit parallel adder.

Fig 1. N bit parallel adder/subtractor

Fig 2. N bit ripple carry adder

Assignment:

1. Implement a logic circuit to perform the following operation using one parallel
adder/subtractor.
 19EAC181 - Digital System Lab
Experiment - 9
Study and Realization of Combinational Circuit using Multiplexer
Aim:
To study and realize following combinational circuits using 4:1 Multiplexers-
i) Half adder
ii) Full adder
iii) Half subtractor
iv) Full subtractor

Tool Used:
Microwind DSch2

Design:
A multiplexer routes (or connects) the selected data input to the output. The value of the selection
inputs determines the data input that is selected.
A multiplexer has
 n Selection inputs
 2n data inputs
 1 output

Block Diagram
4:1 Multiplexer:
i) Half adder using 4:1 Multiplexers

ii) Full adder using 4:1 Multiplexers

Truth Table
A B C SUM COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Assume A and B are selection inputs for 4:1 Multiplexer.

A B SUM COUT
0 0 C 0
0 1 C’ C
1 0 C’ C
1 1 C 1
 Logic Diagram of Full adder using 4:1 MUX

iii) Half subtractor using 4:1 Multiplexers

Truth Table

iv) Full subtractor using 4:1 Multiplexers

Truth Table
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
 0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Assume A and B are selection inputs for 4:1 Multiplexer.

A B Diff Borrow
0 0 C C
0 1 C’ 1
1 0 C’ 0
1 1 C C
 19EAC181 - Digital System Lab

Experiment - 10
Study and Verification of Flip-flops
Aim:
To study and verification of D flip-flop, JK flip-flop and T flip-flop.

Tool Used:
Microwind DSch2

Design:
Flip-flop-
 Flip-flop is a basic digital memory circuit, which stores one bit of information. Flip flops
are the fundamental blocks of most sequential circuits which are used as memory element.
 It is also known as a bistable multivibrator or a binary or one-bit memory.
 The state of flip-flop changes at active state of clock pulses and remains unaffected when
the clock pulse is not active.
 Flip-flops are edge-triggered circuit.

D-Latch-
Latch is an electronic device that can be used to store one bit of information. Latches are level
sensitive circuit. For positive level triggered D latch or Data latch is used to capture, or ‘latch’ the
logic level which is present on the Data line when the clock input is high. When the Clk input falls
to logic 0, the last state of the D input is trapped and held in the latch.

D Flip-Flop (Negative edge triggered)-

The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as
the rising edge of the clock or falling edge of the clock). That captured value becomes the Q output.
At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, or
a delay line.

Timing Diagram for D-Latch and D-Flip flop-

JK Flip-Flop (Negative edge triggered)-

T Flip-Flop (Negative edge triggered)-
 19EAC181 - Digital System Lab

Experiment - 11
Study of Shift Registers
Aim: To study the characteristics of the shift register.
(i) Simple Shift Register
(ii) Universal Shift Register

Tool Used:
Microwind DSch2

Design:
Simple Shift Register

 Figure shows a four-bit shift register that is used to shift its contents one bit-position to the
right.
 The data bits are loaded into the shift register in a serial fashion using the In input.
 The contents of each flip-flop are transferred to the next flip-flop at each positive edge of
the clock.
 An illustration of the transfer is shown below, which shows what happens when the signal
values at In during eight consecutive clock cycles are 1,0,1,1,1,0,0,and 0, assuming that
the initial state of all flip-flops is 0.

Universal Shift Register

  Figure shows a four-bit shift register that allows the parallel access.
 The control signal Shift/Load is used to select the mode of operation. If Shift/Load
= 0, then the circuit operates as a shift register. If Shift/Load = 1, then the parallel input
data are loaded into the register.
In both cases the action takes place on the positive edge ok clock.
 19EAC181 - Digital System Lab

Experiment - 12
Study of Ring and Johnson Counters
Aim: To study the characteristics of following counters-
(iii) Ring Counter
(iv) Johnson Counter

Tool Used:
Microwind DSch2

Design:
Ring Counter

n-bit Ring Counter Logic Circuit

 The circuit in Figure is referred to as a ring counter. This counter is developed by modifying a shift
register.
 The true output of the last flip-flop is fed back directly to the data input of the first flip-flop, thus
generating a sequence of pulses.
 Its operation has to be initialized by injecting a 1 into the first stage. This is achieved by using the
Start control signal, which presets the left-most flip-flop to 1 and clears the others to 0.

n-bit Ring counter = n-flip-flops = n different states

 Timing Diagram

Johnson Counter

n-bit Johnson counter

n-bit Johnson counter = n-flip-flops = 2n different states

Timing Diagram
 19EAC181 - Digital System Lab

Experiment - 13
Study of Asynchronous Binary Counters
Aim: To study and verify the characteristics of following asynchronous binary counters using T
flip-flop-
(v) 4-bit Up Counter
(vi) 4-bit Down Counter

Tool Used:
Microwind DSch2

Design:
4-bit Asynchronous Binary Up Counter

4-bit Asynchronous Up Counter

 Figure gives a four-bit counter capable of counting from 0 to 15. The clock inputs of the four flip-
flops are connected in cascade.
 The T input of each flip-flop is connected to a constant 1, which means that the state of the flip-
flop will be reversed (toggled) at each positive edge of its clock.
 The clock input of the first flip-flop is connected to the Clock line. The other two flip-flops have
their clock inputs driven by the Q output of the preceding flip-flop.
 Therefore, they toggle their state whenever the preceding flip-flop changes its state from Q = 1
to Q = 0, which results in a negative edge of the Q signal.

Truth Table
4-bit Asynchronous Binary Down Counter

4-bit Asynchronous Down Counter

Timing Diagram