Std : 12th Year : 2020-21

Subject : Computer Science II

Chapter : 2 Instruction set and Programming of 8085

Subtopic : Study of instructions

Programs based on instructions (ALP)
 CHAPTER 2
INSTRUCTION SET AND
PROGRAMMING OF 8085
8085 has 74 instructions

Each instruction of microprocessor 8085

consists of opcode & operand.

Opcode tells about the type of operation

while operand can be data (8 or 16 bit),
address, registers, register pair, etc.
DIRECT ADDRESSING :
• Addressappears after opcode of instruction
• The address of operand is specified within instruction
• These are 3 byte instructions.
• Byte 1 is opcode while byte 2 & 3 are of address.

Example : LDA D500 H

This instruction will load accumulator with content of memory location D500 H.

Instruction Byte 1 Byte 2 Byte 3

LDA D500 H LDA 00 D5

Example : STA 95FF H

This instruction will store the content of accumulator to memory
location 95FF H
Instruction Byte 1 Byte 2 Byte 3
STA 95FF H STA FF 95
REGISTER ADDRESSING :
• Register appears after opcode
• Operands are general purpose registers specified withininstruction
• These are ONE byte instructions.
• All actions occur within CPU

Example : MOV A,B

This instruction transfers the content of register B to accumulator
without modifying the contentof B

Example : INR B
This instruction will increment the content of register B by 1

Example : ADD C
This instruction will add the content of register C to accumulator
without modifying the contentof C
REGISTER INDIRECT ADDRESSING :

• Content of register pair points to the addressof operand.

• A register pair (H-L pair) is specified for addressing 16-bit address of
memory location.
• These generally are single byte instructions.

Example : MOV M,B

This instruction transfers the content of register B to memory location
whose address is placed in HL register pair without modifying the
content of B

Example : ADD M
This instruction will add the content of memory location whose address
is placed in HL register pair to accumulator without modifying the
content of memory location
IMMEDIATE ADDRESSING :
• Data (8 or 16-bit) appears immediately after opcode of instruction.
• In these instructions actual data is specified within the instruction.
• These may be 2 to 3 byteinstructions.

Example : MVI A,99H

This instruction will load the accumulatorwith 8-bit immediate data
99H which is specified within second byte ofinstruction.

Example : LXI D,8C50H

This instruction will load DE register pair with 16-bit immediate data
8C50H. Where D=8C & E=50

Instruction Byte 1 Byte 2 = E Byte 3 = D

LXI D,8C50 H LXI D 50 8C
IMPLIED/IMPLICIT ADDRESSING :
• Operand is generally not specified within the instruction but it
is predetermined.
• Generally operand is accumulator.
• Most of the logical group instructions belong to this addressing mode.
• These are single byte instructions.
• All actions occur within CPU

Example : CMA
This instruction complements the content of accumulator. Result is
placed in accumulator.

Example : RLC
This instruction rotates the content of accumulator to left by 1-bit
position without modifying the content of memory location
 GROUPING OF INSTRUCTIONS OF 8085
ACCORDING TO LENGTH

One Byte Two Byte Three Byte

instruction instruction instruction
(One word) (Two word) (three word)
Opcode & Opcode is 1st byte Opcode is 1st byte
operand both operand is 2nd operand is 2nd & 3rd
in 1 byte byte(generally 8-bit byte(generally 16-
data) bit address or data)
Eg: MOV A,B
ADD M Eg: ADI 88H Eg: LXI H,C588H
SUI FCH STA D5FCH
 CLASSIFICATION OF INSTRUCTIONS BASED
ON FUNCTIONS
Data Arithmetic Logical Group Branching Machine
Transfer Group Group Control
Group Group
Copies data Performs Performs Allows Control
from a arithmetic logical programmer to machine
location operations operations change the operations
(source) to such as such as AND, sequence of such as
another addition, OR, EX-OR, execution of Halt,
location subtraction, Complement, program Interrupt,
(destination) increment, etc. generally conditionally Input,
without decrement, with or Output, etc.
modifying etc. on data accumulator. unconditionally
content of registers or (Also rotate & enables to Eg: HLT,
source memory operation) form a loop of PUSH, POP,
Eg: MOV, Eg: ADD, Eg: ANA, instruction IN, OUT
MVI, SHLD, SUB, SUI, ORI, XRA, Eg: JMP, JNC,
LDA, STA DCX, INR RLC, CMP JZ, JPE, JP
INSTRUCTION CYCLE:-
DEFINITION :-
• T-State: The subdivision of an operation ,which equals to one clock period is
called as T-state.

• Machine Cycle: The time required to complete any operation which is a sub part
of an instruction.
The machine cycle consist of number of T-state.
Machine cycle operation like Opcode fetch, MR, MW, Acknowledge

• Instruction Cycle: The time required to complete the execution of an

instruction.
An instruction cycle may consist of no.of machine cycles.
e.g. One to five machine cycle.
 I] DATA TRANSFER GROUP

1) MOV rd, rs : MOVE REGISTER

Format: [rd] [rs]
Addressing: Register addressing

Group: Data transfer group

Bytes: 1 byte
Flags: None

This instruction will copy contents of source register to destination

register without modifying contentof source register.
Example: Let [A] = 87 H & [C] = 55 H
Instruction: MOV C,A (hence ‘A’ is rs & ‘C’ is rd)
After execution: [A] = 87 H &[C] = 87 H
 I] DATA TRANSFER GROUP

2) MOV r, M : MOVE FROM MEMORY TO REGISTER

Format: [r] [[H-L]]
Addressing: Register indirect addressing

Group: Data transfer group

Bytes: 1 byte
Flags: None

This instruction will load destination register with content of

memory location whose address is stored in HL register pair
withoutmodifying content of memory location.
Example: Let [H-L] = C050H, [C050] = 58H & [B] = C5 H
Instruction: MOV B,M
After execution: [B] = 58H & [C050] = 58 H
 I] DATA TRANSFER GROUP
3) MOV M, r : MOVE FROM REGISTER TO MEMORY
Format: [[H-L]] [r]
Addressing: Register indirect addressing
Group: Data transfer group
Bytes: 1 byte
Flags: None
This instruction will copy content of source register to the memory
location whose address is stored in HL register pair without
modifying content of source.

Example: Let [H-L] = C050H, [C050] = 58H & [A] = C5 H

Instruction: MOV M,A

After execution: [A] = C5H & [C050] = C5H
I] DATA TRANSFER GROUP

4) MVI r, data : MOVE IMMEDIATE 8-BIT DATA TO REGISTER

Format: [r] data (2nd byte)
Addressing: Immediate addressing

Group: Data transfer group

Bytes: 2 byte
Flags: None

This instruction will load register r with 8-bit immediate dataspecified

in 2nd byte of instruction.

Example: Instruction: MVI C, 23H

After execution: [C] = 23H
 I] DATA TRANSFER GROUP
5) MVI M, data : MOVE IMMEDIATE 8-BIT DATA TO MEMORY

Format: [[H-L]] data (2nd byte)

Addressing: Immediate/ Register indirect addressing
Group: Data transfer group
Bytes: 2 byte
Flags: None
This instruction will load the memory location whose address is stored
in HL register pair with 8-bit immediate data specified in 2nd byte of
instruction.
Example: Let [H] = C0 H & [L] = 50 H i.e., [H-L] = C050 H

Instruction: MVI M, 88 H

After execution: [C050] = 88 H

 I] DATA TRANSFER GROUP
6) LXI rp, 16-bit data : LOAD REGISTER PAIR IMMEDIATE
Format: [rp] 16-bit data i.e,. [rh] 3rd byte, [rl] 2nd byte
Addressing:Immediate addressing
Group: Data transfer group
Bytes: 3 byte
Flags: None
This instruction will load the specified register pair with 16-bit data
specified in last 2 bytes of instruction. Byte 3 is moved into higher
order register & byte 2 is moved into lower order register.
Example: Instruction LXI B, D500 H
This instruction will load BC register pair with D500 H. D5 H
will be in higher order register (B) & 00 H will be in lower
order register (C)

Instruction Byte 1 Byte 2 [C] Byte 3 [B]

LXI B, D500 H LXI B 00 D5
 I] DATA TRANSFER GROUP
7) LDA address : LOAD ACCUMULATOR DIRECT WITH DATA AT
GIVEN ADDRESS
Format: [A] [16-bit address] i.e,. [A] [[byte3][byte2]]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flags: None
This instruction will load accumulator with content of memory location
whose address is given in the last 2 bytes of instruction. Content of
the memory location remains unchanged.
Example: Let [9580] = 28 H & [A] = 55 H
Instruction: LDA 9580 H
After execution: [A] = 28H
[9580] = 28 H
Instruction Byte 1 Byte 2 Byte 3
LDA 9580H LDA 80 95
 I] DATA TRANSFER GROUP
8) STA address : LOAD ACCUMULATOR DIRECT WITH DATA AT
GIVEN ADDRESS
Format: [16-bit address] [A] i.e,. [[byte3][byte2]] [A]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flags: None
This instruction will store content of accumulator direct into the
memory location whose address is given in the last 2 bytes of
instruction. Content of accumulator remainsunchanged
Example: Let [C050] = 28 H & [A] = 66 H
Instruction: STA C050 H
After execution: [A] = 66H
[C050] = 66 H
Instruction Byte 1 Byte 2 Byte 3
STA C050 H STA 50 C0
 I] DATA TRANSFER GROUP
9) LHLD address : LOAD H & L REGISTER DIRECT
Format: [L] [16-bit addr] i.e., [L] [[byte3][byte2]]
[H] [16-bit addr +1] i.e., [H] [[byte3][byte2]+1]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flags: None
1st byte is opcode, 2nd & 3rd byte give 16-bit address of memory
location. The content of memory location whose address is given in the
last 2 bytes of instruction is loaded into register L & the content of
next memory location is loaded into register H.
Example: Let [C050] = 28 H & [C051] = 66 H
Instruction: LHLD C050 H
After execution: [H] = 66 H & [L] = 28 H
Instruction Byte 1 Byte 2 Byte 3
LHLD C050 H LHLD 50 C0
 I] DATA TRANSFER GROUP
10) SHLD address : STORE H & L REGISTER DIRECT
Format: [16-bit addr] [L] i.e., [[byte3][byte2]] [L]
[16-bit addr +1] [H] i.e., [[byte3][byte2]+1] [H]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flags: None
1st byte is opcode, 2nd & 3rd byte give 16-bit address of memory
location. The content of register L is stored into the memory location
whose address is given in the last 2 bytes of instruction & the content
of register H is stored into the next memory location.
Example: Let [H] = 34H & [L] = 89H
Instruction: SHLD C050 H
After execution: [C050] = 89 H & [C051] = 34 H
Instruction Byte 1 Byte 2 Byte 3
SHLD C050 H SHLD 50 C0
 I] DATA TRANSFER GROUP
11) LDAX rp : LOAD ACCUMULATOR INDIRECT
Format: [A] [[rp]]
Addressing:Register Indirect addressing
Group: Data transfer group
Bytes: 1 byte
Flags: None

• The content of memory location whose address is stored

in register pair specified in instruction is loaded into
accumulator. The content of memory location remains
unchanged. Here rp can be B (B-C pair) or D (D-E pair).
• Example: Let [B] = 35H & [C] = 45H & [3545] =
22H
• Instruction: LDAX B
• After execution: [A] = 22 H & [3545] = 22 H
 I] DATA TRANSFER GROUP
12) STAX rp : STORE ACCUMULATOR INDIRECT
Format: [[rp]] [A]
Addressing:Register Indirect addressing
Group: Data transfer group
Bytes: 1 byte
Flags: None
• The content of accumulator is stored into the memory location whose
address is stored in register pair specified in instruction. The content of
accumulator remains unchanged. Here rp can be B (B-C pair) or D
(D-E pair).
• Example: Let [A] = 88H, [D] = 35H, [E] = 45H & [3545] = 22H

Instruction: STAX D

After execution: [A] = 88 H & [3545] = 88 H

I] DATA TRANSFER GROUP

13) XCHG : EXCHANGE H & L WITH D & E

Format: [H] [D]
[L] [E]
Addressing: Register addressing
Group: Data transfer group
Bytes: 1 byte
Flags: None
The content of register H is exchanged with that of register D & the
content of register L is exchanged with that of register E.
Example: Let [H] = 28H, [L] = 35H, [D] = 45H & [E] = 22H
Instruction: XCHG
After execution: [H] = 45 H & [L] = 22 H
[D] = 28 H & [E] = 35 H
 I] DATA TRANSFER GROUP

14) IN – Input 8-bit data from an input port to accumulator

Format : IN port 8 bit
Addressing:
Group: Data transfer group
Bytes: 2 bytes
Flags: None
When this instruction is executed the 8 bit data is then inputted from
selected port into accumulator.
The port address can range from 00 H to FF H
e.g IN 53 H
I] DATA TRANSFER GROUP

15) OUT – Output 8-bit data from accumulator to an output port.

Format : OUT port 8 bit
Addressing:
Group: Data transfer group
Bytes: 2 bytes
Flags: None
When this instruction is executed the 8 bit data in accumulator is output on to
the output port.
The port address can range from 00 H to FF H
e.g OUT 55 H
 II] ARITHMETIC GROUP
1) ADD r : ADD REG TO ACC
Format: [A] [A] + [r]
Addressing: Register addressing Bytes: ONE
Group: Arithmetic group Flags: ALL
The content of register r is added accumulator. The result is stored
in accumulator. All flags may be affected
Example: Let [C] = 27H & [A] = 15H
Instruction: ADD C
Addition: 27H = 0 0 1 0 0 1 1 1
+15H = 0 0 0 1 0 1 0 1
3C H = 0 0 1 1 1 1 0 0
S = 0, Z = 0, Ac = 0
P = 1, Cy = 0
After execution: [A] = 3CH [C] = 27
Flag register - 0 0 - 0 - 1 - 0
 II] ARITHMETIC GROUP
2) ADD M : ADD MEMORY CONTENT TOACCUMULATOR
Format: [A] [A] + [[H] [L]]
Addressing:Register Indirect addressing
Group: Arithmetic group
Bytes: 1 byte
The content of accumulator is added to the content of memory HL
register pair. The result is stored in accumulator. All flags may be
affected
Example: Let [HL] = C000H & [C000] = 15H & [A] =30H
Instruction: ADD M
Addition: 15H = 0 0 0 1 0 1 0 1
+30H = 0 0 1 1 0 0 0 0
45H = 0 1 0 0 0 1 0 1
S = 0, Z = 0, Ac = 0
P = 0, Cy = 0
After execution: [A] = 45H [C000] = 15 H
Flag register - 0 0 - 0 - 0 - 0
 II] ARITHMETIC GROUP
3) ADI data : ADD IMMEDIATE TO ACCUMULATOR
Format: [A] [A] + data (BYTE 2)
Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flags: All
The 8-bit immediate data specified in 2nd byte instruction is added to
the content accumulator. The result is stored in accumulator. All flags
may be affected
Example: Let [A] = 8A H
Instruction: ADI 28 H
Addition: 8AH = 1 0 0 0 1 0 1 0
+ 28H = 0 0 1 0 1 0 0 0
B2H = 1 0 1 1 0 0 1 0
S = 1, Z = 0, Ac = 1
P = 1, Cy = 0
After execution: [A] = B2H
Flag register - 1 0 - 1 - 1 - 0
 II] ARITHMETIC GROUP
4) ADC r : ADD REGISTER TO ACCUMULATOR WITH CARRY
Format: [A] [A] + [r] + [Cy]
Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flags: All
The content of accumulator is added to the content of register & the
content of the carry flag. The result is stored in accumulator. All
flags may be affected
Example: Let [A] = 4C H & [B] = 25 H & [Cy] =01 H
Instruction: ADC B
Addition: [A] : 4CH = 0 1 0 0 1 1 0 0
[B] : +25H = 0 01 0 0 1 0 1
[Cy] : +01H = 0 00 0 0 0 0 1
After execution: [A] = 72H = 0 1 1 1 0 0 1 0
S = 0, Z = 0, Ac = 1
P = 1, Cy = 0
Flag register - 0 0 - 1 - 1 - 0
 II] ARITHMETIC GROUP
5) ADC M : ADD MEMORY CONTENT TO ACCUMULATOR WITH CARRY
Format: [A] [A] + [[H-L]] + [Cy]
Addressing: Register Indirect addressing
Group: Arithmetic group
Bytes: 1 byte
Flags: All
The content of memory location whose address is stored in HL register pair
is added to the content of accumulator & the content of the carry flag. The
result is stored in accumulator. All flags may be affected
Example: Let [A] = 2B H, [HL] = C050 H, [C050] = 58 H & [Cy] =00 H
Instruction: ADC M
Addition: [A] : 2BH = 0 0 1 0 1 0 1 1
[B] : +58H = 0 1 0 1 1 0 0 0
[Cy] : +00H = 0 0 0 0 0 0 0 0
After execution: [A] = 83H = 1 0 0 0 0 0 1 1
S = 1, Z = 0, Ac = 1
P = 0, Cy = 0
Flag register - 1 0 - 1 - 0 - 0
II] ARITHMETIC GROUP
6) ACI data : ADD IMMEDIATE TO ACCUMULATOR WITHCARRY
Format: [A] [A] + data + [Cy]
Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flags: All
The 8-bit immediate data specified in 2nd byte instruction is added to
the content accumulator & to the contents of carry flag. The result is
stored in accumulator. All flags may beaffected
Example: Let [A] = 8A H & [Cy] = 01 H
Instruction: ACI 28 H
Addition: 8AH = 1 0 0 0 1 0 1 0
+28H = 0 0 1 0 1 0 00
+01H = 0 0 0 0 0 0 0 1
B3H = 1 0 1 1 0 0 1 1
S = 1, Z = 0, Ac = 1
P = 1, Cy = 0
After execution: [A] = B3H
Flag register - 1 0 - 1 - 1 - 0
 II] ARITHMETIC GROUP
7 SUB r : SUBTRAC REG FROM ACC Format: [A] [A] - [r]
Addressing: Register addressing
Bytes: ONE
Group: Arithmetic group
Flags: ALL

The content of register r is subtracted from accumulator. The result is stored in

accumulator. All flags affect. Cy is complemented after subtraction.
Example: Let [C] = 37 H & [A] = 40H Instruction:
SUB C

A 0100 0000 C 0011 0111

1’s complement of C 1100 1000
2’s complement 1100 1000 + 1 =1100 1001
A+ C’= 0100 0000 +1100 1001= 1 0000 1001=-09 H
CY =1 after complementing CY=0
After execution A= 09 H Cy= 0
II] ARITHMETIC GROUP
8) SUI data : Subtract Immediate data from ACCUMULATOR
Format: [A] [A] - data (BYTE 2)
Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flags: All
The 8-bit immediate data specified in 2nd byte instruction is SUBTRACTED
from the content of accumulator. The result is stored in accumulator.
All flags may be affected

Example: Let [A] = 40 H

Instruction: SUI 37H

After execution accumulator will contain 09 H with carry flag=0

indicating result is positive
 II] ARITHMETIC GROUP
9) SBB r/m : SUBRTRACT REGISTER/MEMORY FROM ACCUMULATOR
WITH BORROW
Format: [A] [A] - [r] -[Cy]
Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flags: All
The content of source and borrow from the accumulator contents. The
result is stored in accumulator. All flags are affected.

Example: Let [A] = 37H & [B] = 3F H & [Cy] =01 H

Instruction: SBB B

After the execution result in accumulator is A= F7 H & CARRY= 1

Carry flag set indicates the result in accumulator is negative and in 2’s
complement form.
 II] ARITHMETIC GROUP
10) SBI data : SUBTRACT IMMEDIATE WITH BORROW FROM ACCUMULATOR
Format: [A] [A] - data - [Cy]
Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flags: All
The 8-bit immediate data specified in 2nd byte instruction is subtracted from
content of accumulator along with contents of carry flag. The result is stored in
accumulator.

Example:
Instruction: SBI 21 H
When executed it will subtract 21 H from accumulator contents and store the
result in accumulator.
II] ARITHMETIC GROUP
11) INR –INCREMENT CONTENTS OF REGISTER/MEMORY BY 1
Format: INR r / INR m
Addressing : Register
Group: Arithmetic
Bytes: 1 Byte
Flags: All flags except Carry flags are modified. The contents of operand are
incremented by one.
e.g. let E reg content be 2F H
INR E
After execution 0010 1111+1 = 0011 0000
so E= 30 H
II] ARITHMETIC GROUP
12) DCR –DECREMENT CONTENTS OF REGISTER/MEMORY BY 1
Format: DCR r / DCR m
Addressing : Register
Group: Arithmetic
Bytes: 1 Byte
Flags: All flags except Carry flags are modified. The contents of operand are
drecremented by one.
e.g. let E reg content be 2F H
DCR E
After execution 0010 1111 -1 = 0010 1110
so E= 2E H
II] ARITHMETIC GROUP

13) INX –INCREMENT REGISTER PAIR (MEMORY) BY 1

Format: IN X rp
Addressing : Register
Group: Arithmetic
Bytes: 1 Byte
Flags: No flags are modified.
The 16 bit contents of operand register pair are incremented by one.
e.g. let HL = 29FF H
INX H
After execution HL = 3000 H
II] ARITHMETIC GROUP

14) DCX – DECREMENT REGISTER PAIR (MEMORY) BY 1

Format: DCX rp
Addressing : Register
Group: Arithmetic
Bytes: 1 Byte
Flags: No flags are modified.
The 16 bit contents of operand register pair are decremented by one.
e.g. let HL = 29FF H
DCX H
After execution HL = 29FEH
 II] ARITHMETIC GROUP
15) DAD rp - Add register pair to H & L register (DOUBLE ADD)
Format: [HL] [HL] + [rp]
Addressing : Register
Group: Arithmetic
Bytes: 1 Byte
Flags: Only carry flag is affected.
It adds 16 bit contents of specified operand to 16 bit contents of HL pair.
The result is stored in HL Pair.
e.g HL and DE are H =10 L= 10
+ D= 23 E=23
After DAD D
H= 33 L= 33 CY=0
II] ARITHMETIC GROUP
16) DAA – DECIMAL ADJUST ACCUMULATOR
Format: DAA
Addressing : Implicit
Group: Arithmetic
Bytes: 1 Byte
Flags: All flags are affected.
• This instruction give addition of two BCD numbers.
• It adjusts the sum of two BCD nos and not convert the binary no.
to BCD.
• This is the only instruction uses AC flag internally for code adjustment.
II] ARITHMETIC GROUP

• DAA Adjustment Procedure

1. Carry out BCD addition
2. If lower nibble of result is greater than 9 or AC flag is set add
06 H to lower nibble.
3. If higher nibble of result is greater than 9 or C flag is set add
60 H to higher nibble.
4. If both nibble of result is greater than 9 or AC & C flag are set
add 66 H to lower nibble.
II] ARITHMETIC GROUP
• Example: ADD 12 BCD to 39 BCD
39 BCD 0011 1001
12 BCD 0001 0010
51 BCD 0100 1011 > 9
4 B
The binary sum is 4B H so add 06 H to lower nibble

4B 0100 1011
06 0000 0110
51 0101 0001
5 1
III] LOGICAL GROUP INSTRUCTION
1. ANA r (Logical AND reg. with Accumulator)
ANA M ( Logical AND memory with Accumulator)
Addressing: Register
Group: logical
Byte: 1 Flags :S, Z, P

Carries logical ANDing contents of ACCUMULATOR with contents of

Register or Memory.
This instruction is used to masking bits during Programming.

e.g. Let A=54 H D=82 H

ANA D
After execution A= 00 H
III] LOGICAL GROUP INSTRUCTION

1. ANI 8 bit data (Logical AND 8 bit no. with Accumulator)

Addressing: Immediate
Group: Logical
Byte: 2 Flags :S, Z, P

Carries logical ANDing contents of ACCUMULATOR with 8 bit no.

This instruction is used to masking bits during Programming.

e.g. The instruction ANI 3F H when executed will store result of ANDing 3F H with
Accumulator.
III] LOGICAL GROUP INSTRUCTION
1. ORA r (Logical OR reg. with Accumulator)
ORA M ( Logical OR memory with Accumulator)
Addressing: Register
Group: Logical
Byte: 1 Flags :S, Z, P

Carries logical ORing contents of ACCUMULATOR with contents of

Register or Memory.

e.g. Let A=BA H B=11 H

ORA D
After execution A= BB H F=84 H
III] LOGICAL GROUP INSTRUCTION

1. ORI 8 bit data (Logical AND 8 bit no. with Accumulator)

Addressing: Immediate
Group: Logical
Byte: 2 Flags :S, Z, P

Carries logical ORIng contents of ACCUMULATOR with 8 bit no.

e.g. The instruction ORI 4C H when executed will store result of ORing 4CH with
Accumulator.
The result is stored in accumulator.
III] LOGICAL GROUP INSTRUCTION
1. XRA r (Logical EX-OR reg. with Accumulator)
XRA M ( Logical EX-OR memory with Accumulator)
Addressing: Register
Group: Logical
Byte: 1 Flags :S, Z, P

Carries logical Ex -Oring contents of ACCUMULATOR with contents of

Register or Memory.
XRA A it makes accumulator clear.

e.g. Let A=AA H B=55 H

EXA B
After execution A=FF H F=84 H
III] LOGICAL GROUP INSTRUCTION

1. XRI 8 bit data (Logical AND 8 bit no. with Accumulator)

Addressing: Immediate
Group: Logical
Byte: 2 Flags :S, Z, P

Carries logical EX-ORing contents of accumulator with 8 bit no.

e.g. The instruction XRI FF H when executed will store result of EX-ORing FF H with
Accumulator.
III] LOGICAL GROUP INSTRUCTION
• CMA – (COMPLEMENT THE ACCUMULATOR)
Format ҧ A
Addressing – Implicit
group – logical
byte- 1 Flag- No flags are affected.
This instruction complements the accumulator contents. The result is stored in
accumulator.
e.g. Let A= 57 H 0101 0111
CMA
After execution 1010 1000
so A=A8 H
III] LOGICAL GROUP INSTRUCTION
III] LOGICAL GROUP INSTRUCTION
III] LOGICAL GROUP INSTRUCTION
III] LOGICAL GROUP INSTRUCTION
III] LOGICAL GROUP INSTRUCTION
III] LOGICAL GROUP INSTRUCTION