Resonant

Converters-II
Performance of Series RLC Circuit
with Square Wave Input
➢ Series RLC circuit is studied with square wave
input.
➢ Square wave input is having fundamental
component and odd harmonics.
➢ When series RLC circuit is operated with square
wave as input and quality factor (Q) of the circuit
is reasonably high, then the circuit responds
mainly to fundamental component of the input
voltage.
➢ The current in the circuit is very close to sine
wave as impedance of the circuit is very high for
other components of the input voltage.
➢ Other current components are negligible.
 For fs =fo, Z = R
➢ nth harmonic voltage of the source is expressed as

➢ Fundamental component of the source is

➢ For reasonable Q of the circuit, series RLC circuit offers

high impedance to harmonics. Hence current in the
circuit is mainly due to fundamental component of the
input voltage and close to sine wave.
➢ Current in the circuit can be expressed as
➢Current in the circuit is expressed as
➢Current and voltage are in phase. The voltage
and current waveforms are represented as
 For fs >fo, Circuit is inductive
➢ Capacitive reactance is completely nullified by a part
of inductive reactance and still certain amount of
inductive reactance is left in the circuit.
➢ The series RLC circuit now acts as R-Le circuit. Le is
the effective inductance left in the circuit.
➢ Hence the current lags the voltage by certain angle.
Impedance of the resonant tank, Z(LC)
 For fs < fo, Circuit is capacitive
➢ Inductive reactance is completely nullified by a part
of capacitive reactance and still certain amount of
capacitive reactance is left in the circuit.
➢ The series RLC circuit now acts as R-Ce circuit. Ce is
the effective capacitance left in the circuit.
➢ Hence the current leads the voltage by certain angle.
Impedance of the resonant tank, Z(LC)
 Load Resonant Converters
Classification:

i) Series resonant converter

ii) Parallel resonant converter
iii) Series-parallel resonant converter
Various parameters of the converter are:
VDC = DC Supply voltage
Vo = output voltage
Ip = peak value of i(t)
Io = Load current
RL = Load resistance
Re = equivalent load resistance referred to
resonant tank
VAB1 = peak value of fundamental component of vAB
VB’B1 =peak value of fundamental component of vB’B1
Waveforms of SRC
Expression for output voltage
The quality factor (Q), resonant frequency (o),
and characteristic impedance (Zc) of the SRC
are given as follows:

➢Q = (oLr)/Re
➢o = 1/Lr.Cr
➢Zc = Lr/Cr
Gain vs. Normalized frequency
characteristic of SRC
 Advantages of series Resonant Converter

➢ HV transformer is free from possible saturation,

➢ Leakage inductance of HV transformer is absorbed into
the resonant tank circuit,
➢ Simple capacitive filter at the output stage,
➢ Suitable for HV applications as the ripple current rating
of the output capacitor becomes low,
➢ High efficiency over a wide range of load variations,
➢ Provides inherent short circuit protection capability
when operated above resonant frequency, and
➢ ZVS of the switching devices is possible when the
converter is operated above resonant frequency.
 Disadvantages of series Resonant Converter

➢Doesn’t absorb winding capacitance of the HV

transformer into the resonant tank circuit, and

➢Output voltage is not controllable under no-

load condition in frequency-controlled
converter.
Expression for output voltage
Gain vs. Normalized frequency
characteristic of PRC
Advantages of the parallel resonant converter:

➢ Winding capacitance of the HV transformer is absorbed into

its resonant tank network, and
➢ Provides high gain, which can reduce turns ratio of the HV
transformer.

Disadvantages of the parallel resonant converters:

➢ Possibility of HV transformer saturation as there is no DC

blocking series capacitor,
➢ Low efficiency under light load condition,
➢ Large peak stresses on tank elements, and
➢ Need of an L-C filter at the output stage, which is prohibitive
for HV applications due to large size of the filter inductor.
Expression for output voltage
Advantages of the series-parallel converter:
➢ Winding capacitance and leakage inductance of
the HV transformer are absorbed into the tank
circuit,
➢ Output voltage is controllable under no-load or
light-load condition also, and
➢ Light-load efficiency is high.
Disadvantages of the series-parallel converter:
➢ More complicated to analyze and difficult to
control due to multiple resonant frequencies as
compared to SRC and PRC, and
➢ Presence of certain amount of circulating current
in the tank circuit under no-load condition,
though smaller than in PRC.
References:
1. Robert L. Steigerwald, “A Comparison of Half-Bridge
Resonant Converter Topologies”, IEEE Transactions on
Power Electronics”, vol.3, No.2, April 1988, pp. 174-182.

2. Ramesh Oruganti and F.C. Lee, “Resonant Power

Processors, Part I – State Plane Analysis”, IEEE
Transactions on Industry Applications, vol.IA-21, No.6,
November / December 1985, pp.1453-1460.

3. S.D. Johnson, A.F. Witulski, and R.W. Erickson,

“Comparison of Resonant Topologies in High Voltage DC
Applications”, IEEE Transactions on Aerospace and
Electronic Systems, Vol.24, No.3, May 1988, pp.263-274.
Phase-shift Controlled Series
Resonant Inverter
Gate Voltages and Inverter Output
voltage Waveforms
Equation for Tank Current and
Capacitor Voltage
Phase-shifted series resonant inverter operates
in following three modes of operation based on
the values of quality factor(Q) and duty cycle(D):

➢Mode-1 operation
➢Mode-2 operation
➢Mode-3 operation

Mode of operation influences ZVS operation of

the inverter.
Mode-1 Operation
Mode-2 Operation
Mode-3 Operation
➢ Under each sub-interval there is certain
combination of voltage and current.
➢ During sub-interval-A, when both voltage and
current are positive, energy is drawn from the
source.
➢ During sub-interval-B, current is positive and
voltage is zero. Energy stored in tank is circulated
and transferred to output.
➢ During sub-interval-C, current is positive and
voltage is negative. Energy is returned back to the
source.
➢ Similar type of situations will exist in other three
sub-intervals also.
➢In mode-1 operation, when vAB is rising to
+vDC, i(t) is negative. This is suitable for ZVS.
➢In mode-2 operation, when vAB is rising to
+VDC, i(t) is positive. This is not suitable for
ZVS.
➢In mode-3 operation, when vAB is rising to
+VDC, i(t) is zero. This is also not suitable for
ZVS.
➢In mode-2 and mode-3 operation, additional
circuit is required for ZVS operation of the
switching devices.
 Output power vs. Duty cycle for
various values of Q and fs/fo = 1.1
➢ The above characteristic is drawn between output power vs.
duty cycle for different values of Q and fs/fr = 1.1.
➢ Output power increases with increase in duty cycle for all Q.
➢ For any duty cyce, output power increases with increases in Q
or load.
➢ Rate of increase of output power with duty cycle is more for
lower values of duty cycles than for higher values. At lower
values of duty cycles, converter is in mode-3 and at higher
duty cycles it may go into mode-2 or mode-1. In mode-2 and
mode-1 certain amount of energy is returned to the source
whereas it is not so in mode-3. As duty cycle approaches
towards unity, characteristic relatively becomes flat.
Output power vs. Q for D = 1 and
fs/fo = 1.1
➢Above characteristic shows output power
variation with Q (load) for D = 1 and fs/fr =
1.1.
➢Output power increases with load and reaches
a maximum and then decreases. This is a
situation for maximum power transfer.
Output power vs. Q for D = 1 and
various values of fs/fo
➢Above characteristic is again output vs. Load
for different values of fs/fr.
➢For any load, as fs/fr decreases output
increases.
➢For any characteristic, rate of increase of
output is more at lower values of load. This is
because of the converter being in mode-3. At
higher loads the converter may enter into
mode-2 and mode- 1.
Peak tank current vs. Q for fs/fo = 1.1
and various values of D
 Peak capacitor voltage vs. Q for
fs/fo = 1.1 and various values of D
➢Peak tank current and peak capacitor voltage
are peak stresses of the resonant circuit.
➢Above two characteristics are for peak
stresses of the converter as load changes.
These are for different values of duty cycle.
➢For any given load, as duty cycle increases
peak stresses increase.
➢Also, for any given characteristic, peak stresses
increase as load increases i.e., Q.
 Asymmetrical Duty Cycle Control
(ADC Control)
➢Asymmetrical duty cycle control is a method
by which range of ZVS operation can be
extended.
➢In this, output voltage of the converter has
only two levels i.e., either +VDC or –VDC.
➢Width of the positive half-cycle and negative
half-cycle need not be same.
Asymmetric duty cycle (ADC) control of SRI
ADC control of SRI with low Q
Circuit operation can be described by writing equations in
intervals TA and TB. Solving equations using the initial conditions
tank current and capacitor voltage can be expressed as
ZVS Operation
➢ For ZVS operation, the capacitance across the device
drain-source is useful. This capacitance needs to be
charged and discharged at suitable rate.
➢ Amount of capacitance needed is calculated for this
purpose.
➢ If more capacitance is required, additional capacitance
is added externally.
➢ It needs to be calculated for devices of both lagging-leg
as well as leading-leg.
➢ Charging and discharging of these capacitances is done
during the dead time of the gating pulses of the same
leg.
➢ Based on the amount of load and duty cycle, ZVS
operation may be effected. It needs to be compensated
externally.
• In the figure, leading-leg (left leg) of the inverter is
shown. It is assumed that the inverter is in mode-1
operation and square wave mode.
• i(t) is shown going away from node-A. Let vAB is initially
positive. Hence S1 and S4 are on. Hence voltage across
S1 is zero and voltage across S2 is VDC .
• The instant vAB has to go to -VDC from +VDC , S1 and S4
are turned-off and S2 and S3 are turned-on with
certain dead-time(Td).
• During Td the capacitor across S1 has to charge to +VDC
and capacitor across S2 has to discharge to zero for
left-leg. The charging current for each capacitor is
i(t)/2. Similar is the situation for right-leg. Direction of
i(t) is suitable for this. Hence this results in ZVS
operation of S1 and S2. Similarly for the right leg
devices also.
➢The value of the capacitance required is
calculated based on the current at that instant
and Td value.
➢Once S1 is turned-off, voltage across it rises at
certain rate and it is not very fast. This is
because of capacitance across S1. Hence this
results in ZVS turn-off of S1.
➢During Td the capacitor across S2 is discharged
to zero. After this gate pulse is applied to S2.
Hence it results in ZVS turn-on of S2. Similar
things happen for right leg also.
➢ZVS operation of leading-leg devices is not a
problem under mode-2 and mode-3
condition.
➢But ZVS operation of lagging-leg devices needs
additional circuit under mode-2 and mode-3
condition.
➢The above method indicates external
compensation for ZVS operation of lagging-leg
devices. The above figure shows mode-2
condition.
➢When vAB is rising to +VDC, i(t) is positive. By an
additional circuit total current at node-B
should be made negative.
➢ This is achieved by an external inductor(Lex) and
two split capacitors(large electrolytic capacitors)
creating two sources of VDC/2 as shown in the
figure.
➢ Voltage across Lex is a square wave with + VDC/2
and - VDC/2.
➢ The current waveform in Lex is triangular as
shown. The waveform is in such a manner that it
will create net negative current at node-B which
is helpful for ZVS of lagging-leg devices.
➢ When vAB is rising to +VDC, i(t) is positive(going
towards node-B). But iLex is negative(going away
from node-B) with such a magnitude that overall
current at node-B is negative.
➢ Just before the rise of vAB to +VDC , it is zero and
S1 and S3 are free-wheeling the tank current. For
making vAB to +VDC , S3 is turned-off and S4 is
turned-on.
➢ Now since the net current is going away from
node-B, it will charge the capacitor across S3
when it is turned-off and will discharge capacitor
across S4 before it is turned-on. This results in
ZVS operation of both devices.
➢ Hence during mode-2 also, ZVS of lagging-leg
devices can be achieved.
➢ Similarly, ZVS operation can be achieved during
mode-3 operation also.
External Inductor
For Leading Leg
For Lagging Leg
ZCS Operation
 ZCS Operation
➢ZCS operation is achieved for leading current.
➢Just before t = 0, VAB is –VDC and current in the
resonant circuit is positive. S2 and S3 are on.
Hence anti-parallel diodes (D2 and D3) are
conducting. It means, device current is
negative.
➢At t=0, gate pulse of S2 is made zero. At this
instant, D2 is conducting and not the device.
Hence S2 turns-off with ZCS.
➢ D2 continues to conduct current. Hence drain-
source capacitor of S1 is not discharged and also
drain-source capacitance of S2 is not charged.
➢ After the dead time, gate pulse to S1 is applied.
Resonant circuit current instantly shifts from D2
to S1. Momentarily, D2 acts like short and there is
current surge through S2 and D2 and D2 turns-
off.
➢ Also, after S1 is tuned-on, drain-source capacitor
of S1 discharges into S1 and this energy is lost.
Turn-on of S1 is neither ZCS nor ZVS.
➢Similar events happen with the right-leg
devices also.
➢Hence in the ZCS operation of left-leg, only
the device with negative current, i.e., S2 gets
ZCS operation whereas S1 doesn’t get either
ZCS or ZVS. Also, the energy of its drain-source
capacitance is also lost.
➢ Hence ZVS operation is preferred compared
to ZCS.
➢In practice, based on the situation there can
be ZCS, ZVS or combination of them.
References:

1. Vlatkovic,V., Borojevic, D. & Lee, F. “ Input filter design for

p.f. correction circuits” International Conference on
Industrial Electronics, Control and Instrumentation, 1993,
pp. 954-958.
2. H. Fujita, H. Akagi, K. Sano, K. Mitu, R. H. Leonard, “Pulse
Density Modulation Based Power Control of a 4 kW, 400
kHz Voltage Source Inverter for Induction Heating
Application”, PC-Yokohama’93., pp.111-116.
3. Barbi, I. & Silva, S.A.O. “Sinusoidal line Current
Rectification at Unity p.f. with Boost Quasi Resonant
Converters”, Proceedings of the Applied Power Electronics
Conference, 1990, pp. 553-562.
4. J.M. Ho & M.T. Lee, “A Novel PWM Inverter Control
Circuitry for Induction Heating”, CIEP,96, pp.113-119.