Microprocessors and Microo

1.68
Table 1.2. Procedures Vs
Macros
icrocontrola
PROCEDURES MACROS
s.No.
To use a procedure CALL and RET To use a macro, Just type its na
instructions are needed name
2. It occupies less memory. It occupies more memory.
3. Stack is used. Stack is not used.
To mark the end of the procedure, type To mark the end of the macro EN
the name of the procedure before the| directive is enough. NDN
ENDP directive.
Overhead time is required to call the| No overhead time during
procedure and return to the calling| execution the
program.

1.13 INTERRUPTS AND INTERRUPT SERVICE ROUTINES

1.13.1 Interrupts
Asignal to the processor to halt its current operation and immediately transfer
to an interrupt service routine is called as interrupt. Interrupts are triggered either by control
as when the keyboard detects a key press, or by software, as when a hardware
INT instruction. program executes the

Interrupts can be seen as a number of functions. These functions make the

much easier, instead of programming
it will do
writing a code to
print a character,
simply call the interrupt and
everything.
There are also interrupt functions that work with disk drive and other hardware. They
are called as software interrupts.
Interrupts are also triggered by different
hardware, these are called
interrupts. hardware
To make software
a
interrupt there is an INT instruction, it has very simple syntax
INT value.
Where value can be a number between 0 to 255 (or 00 to FF H).
1.13.2 Interrupt Service Routines (ISRs)
ISR is routine that receives
a
processor control when a specific interrupt occurs.
The 8086 will
directly call the service routine for 256 vectored
Software processing. This is in
contrast to non vectored
interrupts without any
to a
single interrupt service routine, regardless of the interrupts that transfer control direcy
The 8086
interrupt source.
provides a 256 entry
interrupt vector table beginning at address 0:0 in memor
This is a lK table
containing 256 4-byte entries. Each entry in this table contains a
segmen
8086 Microprocessor 1.69

that points
atthe interrupt service routine in memory. Generally, interrupts referred
ress
eir index into this table, so interrupt zero's address (vector) is at memory location U0,
their s vector is at address 0:4, interrupt two's vector is at address 0:8, etc.
rupt o n e ' s v e

Interrupt vector table:

It is a table by the operating system. It contains addresses (vectors) of

maintained

rent interrupt
service routine. When an interrupt occurs, the CPU branches to the address
rhe table that corresponds to the interrupt's number.
3FFH TYPE 255 POINTER:
AVAILABLE 3FC H (AVAILABLE)
INTERRUPT

TYPE 33 POINTER:
084 H
(AVAILABLE)
TYPE 32 POINTER:
080 H
(AVAILABLE)
TYPE 31 POINTER:
RESERVED 07FH
(AVAILABLE)
INTERRUPT

TYPE 5 POINTER:
014 H
(RESERVED)
TYPE 4 POINTER:
010 H OVERFLOW
TYPE 3 POINTER:
DEDICATED 00 1-BYTE INT INSTRUCTION
INTERRUPT TYPE 2 POINTER:
008 H NON MASKABLE

TYPE 1 POINTER:
004 H SINGLE STEP
TYPE O POINTER:
000 H
DIVIDE ERROR
Vector Table
Fig. 1.18. Interrupt
does the following:
When an interrupt occurs, regardless of source, the 8086
stack.
T h e CPU pushes the flags register onto the
(segment:offset) onto the stack, segment
T h e CPU pushes a far return address
value first.
the interrupt number) and
3. The CPU determines the cause of the interrupt (i.e., 0:8 etc)
fetches the four byte interrupt vector
from address 0: vector x 4 (0:0, 0:4,
the interrupt vector table
4. The CPU transfers control to the routine specified by
entry.
1.70
After the completion of these steps, the interrupt service routine takes control. wh
Microcontrollery
Microprocessors and Microcontron

the interrupt service routine wants to

return control, it must execute an IRET(interrupt
and
retum
instruction. The interrupt return
that executing a
the
pops far return address the flags off the stack. No
far return is insufficient since that would leave the flags on the stack. Note

1.13.3 Types of Interrupts

Hardware Interrupt -

External uses INTR and NMI

2. Software Interrupt Internal from INT or INTO
3 Processor Interrupt - Traps and 10 Software Interrupts
External - generated outside the CPU by other hardware
(INTR, NMI)
Internal generated within CPU as a result of an instruction or operation
(INT, INTO, Divide Error and Single Step)

Progammable
NMI Requesting Interrupt Controller
Device
IRo
NMI -IR,
8086 CPU INTR Intel -IR2
Interrupt Logic 8259A -IR
IR
IR,
INTO Error Step
INTINTovideSingle IR
Software Traps -IR
Fig. 1.19. 8086 Interrupt Connections

1.13.4 Dedicated Interrupts

(i) Divide Error Interrupt (Type 0)
This interrupt occurs automatically following the execution of DIV or IDIV instructions
when the quotient exceeds the maximum value that the division instructions allow.
(ii) Single Step Interrupt (Type 1)
This interrupt occurs automatically after execution of each instruction when the Trap
Flag (TF) is set to 1. It is used to execute programs one instruction at a time, after which an
interrupt is requested. Following the ISR, the next instruction is executed and another single
stepping interrupt request occurs.
(ii) Non Maskable Interrupt (Type 2)
It is the highest priority hardware interrupt that triggers on the positive edge.
interrupt occurs automatically when it receives a low-to-high transition on its NMI input p
This interrupt cannot be disabled or masked. It is used to save program data or process
status in case of system power failure.
 The 8086 Microprocessor

1.71
iv) Breakpoint Interrupt (Type 3)
This interrupt is used to set break
points in software debugging programns.
()Overflow Interrupt (Type 4)
This interrupt is initiated by INTO (Interrupt on Overflow) instruction. It is used to
herk overflow condition after any signed arithmetic operation in the system. The overflow
che
aa (OF) will be set if the signed arithmetic operation generates a result whose size is larger
han the size of destination register or memory location. At this time overflow interrupt is
indicate an error condition.
used to
1.13.5 Software Interrupts (INT n)
The software interrupts are non maskable interrupts. They are higher priority than
hardware interrupts.
The software interrupts are called within the program using the instruction INT n.
Here 'n'means value and is in the range of 0 to 255. These interrupts are useful for debugging,
testing ISRs and calling procedures.

1.13.6 Hardware Interrupts

INTR and NMI are called hardware interrupts. INTR is maskable and NMI is non-
maskable interrupts.
INTR interrupts (Type 0 -255) can be used to interrupt a program execution. This
interrupt is implemented by using two pins: INTR and NMI. This interrupts can be enabled
or disabled by STI (1F=1) or CLI (IF=0) respectively.

1.13.7 Interrupt Priority

The priority of interrupts of 8086 is shown in Table 1.3. The software interrupts except
single step interrupt have the highest priority; followed by NMI, followed by INTR. Single
step interrupt has the least priority. The 8086 checks for internal interrupts before for any
hardware interrupt. Therefore software interrupts have higher priority than hardware interrupts.
Table 1.3. Interrupt Priority

Interrupt Priority
INT n, INTO, Divide Error Highest

NMI

INTR

Single Step Lowest