BRIEF CONTENTS

Preface v

CHAPTER 1: Semiconductor Diodes 1

CHAPTER 2: Diode Applications 55

CHAPTER 3: Bipolar Junction Transistors 129

CHAPTER 4: DC Biasing—BJTs 160

CHAPTER 5: BJT AC Analysis 253

CHAPTER 6: Field-Effect Transistors 378

CHAPTER 7: FET Biasing 422

CHAPTER 8: FET Amplifiers 481

CHAPTER 9: BJT and JFET Frequency Response 545

CHAPTER 10: Operational Amplifiers 607

CHAPTER 11: Op-Amp Applications 653

CHAPTER 12: Power Amplifiers 683

CHAPTER 13: Linear-Digital ICs 722

CHAPTER 14: Feedback and Oscillator Circuits 751

CHAPTER 15: Power Supplies (Voltage Regulators) 783

CHAPTER 16: Other Two-Terminal Devices 811

CHAPTER 17: pnpn and Other Devices 841

Appendix A: Hybrid Parameters—Graphical

Determinations and Conversion Equations (Exact
and Approximate) 879

ix
x BRIEF CONTENTS Appendix B: Ripple Factor and Voltage Calculations 885

Appendix C: Charts and Tables 891

Appendix D: Solutions to Selected

Odd-Numbered Problems 893

Index 901
 CONTENTS

Preface v

CHAPTER 1: Semiconductor Diodes 1

1.1 Introduction 1
1.2 Semiconductor Materials: Ge, Si, and GaAs 2
1.3 Covalent Bonding and Intrinsic Materials 3
1.4 Energy Levels 5
1.5 n-Type and p-Type Materials 7
1.6 Semiconductor Diode 10
1.7 Ideal Versus Practical 20
1.8 Resistance Levels 21
1.9 Diode Equivalent Circuits 27
1.10 Transition and Diffusion Capacitance 30
1.11 Reverse Recovery Time 31
1.12 Diode Specification Sheets 32
1.13 Semiconductor Diode Notation 35
1.14 Diode Testing 36
1.15 Zener Diodes 38
1.16 Light-Emitting Diodes 41
1.17 Summary 48
1.18 Computer Analysis 49

CHAPTER 2: Diode Applications 55

2.1 Introduction 55
2.2 Load-Line Analysis 56
2.3 Series Diode Configurations 61
2.4 Parallel and Series–Parallel Configurations 67
2.5 AND/OR Gates 70
2.6 Sinusoidal Inputs; Half-Wave Rectification 72
2.7 Full-Wave Rectification 75
2.8 Clippers 78
2.9 Clampers 85
2.10 Networks with a dc and ac Source 88
xi
xii CONTENTS 2.11 Zener Diodes 91
2.12 Voltage-Multiplier Circuits 98
2.13 Practical Applications 101
2.14 Summary 111
2.15 Computer Analysis 112

CHAPTER 3: Bipolar Junction Transistors 129

3.1 Introduction 129
3.2 Transistor Construction 130
3.3 Transistor Operation 130
3.4 Common-Base Configuration 131
3.5 Common-Emitter Configuration 136
3.6 Common-Collector Configuration 143
3.7 Limits of Operation 144
3.8 Transistor Specification Sheet 145
3.9 Transistor Testing 149
3.10 Transistor Casing and Terminal Identification 151
3.11 Transistor Development 152
3.12 Summary 154
3.13 Computer Analysis 155

CHAPTER 4: DC Biasing—BJTs 160

4.1 Introduction 160
4.2 Operating Point 161
4.3 Fixed-Bias Configuration 163
4.4 Emitter-Bias Configuration 169
4.5 Voltage-Divider Bias Configuration 175
4.6 Collector Feedback Configuration 181
4.7 Emitter-Follower Configuration 186
4.8 Common-Base Configuration 187
4.9 Miscellaneous Bias Configurations 189
4.10 Summary Table 192
4.11 Design Operations 194
4.12 Multiple BJT Networks 199
4.13 Current Mirrors 205
4.14 Current Source Circuits 208
4.15 pnp Transistors 210
4.16 Transistor Switching Networks 211
4.17 Troubleshooting Techniques 215
4.18 Bias Stabilization 217
4.19 Practical Applications 226
4.20 Summary 233
4.21 Computer Analysis 235
CHAPTER 5: BJT AC Analysis 253 CONTENTS xiii
5.1 Introduction 253
5.2 Amplification in the AC Domain 253
5.3 BJT Transistor Modeling 254
5.4 The re Transistor Model 257
5.5 Common-Emitter Fixed-Bias Configuration 262
5.6 Voltage-Divider Bias 265
5.7 CE Emitter-Bias Configuration 267
5.8 Emitter-Follower Configuration 273
5.9 Common-Base Configuration 277
5.10 Collector Feedback Configuration 279
5.11 Collector DC Feedback Configuration 284
5.12 Effect of RL and Rs 286
5.13 Determining the Current Gain 291
5.14 Summary Tables 292
5.15 Two-Port Systems Approach 292
5.16 Cascaded Systems 300
5.17 Darlington Connection 305
5.18 Feedback Pair 314
5.19 The Hybrid Equivalent Model 319
5.20 Approximate Hybrid Equivalent Circuit 324
5.21 Complete Hybrid Equivalent Model 330
5.22 Hybrid p Model 337
5.23 Variations of Transistor Parameters 338
5.24 Troubleshooting 340
5.25 Practical Applications 342
5.26 Summary 349
5.27 Computer Analysis 352

CHAPTER 6: Field-Effect Transistors 378

6.1 Introduction 378
6.2 Construction and Characteristics of JFETs 379
6.3 Transfer Characteristics 386
6.4 Specification Sheets (JFETs) 390
6.5 Instrumentation 394
6.6 Important Relationships 395
6.7 Depletion-Type MOSFET 396
6.8 Enhancement-Type MOSFET 402
6.9 MOSFET Handling 409
6.10 VMOS and UMOS Power and MOSFETs 410
6.11 CMOS 411
6.12 MESFETs 412
6.13 Summary Table 414
xiv CONTENTS 6.14 Summary 414
6.15 Computer Analysis 416

CHAPTER 7: FET Biasing 422

7.1 Introduction 422
7.2 Fixed-Bias Configuration 423
7.3 Self-Bias Configuration 427
7.4 Voltage-Divider Biasing 431
7.5 Common-Gate Configuration 436
7.6 Special Case VGSQ ⴝ 0 V 439
7.7 Depletion-Type MOSFETs 439
7.8 Enhancement-Type MOSFETs 443
7.9 Summary Table 449
7.10 Combination Networks 449
7.11 Design 452
7.12 Troubleshooting 455
7.13 p-Channel FETs 455
7.14 Universal JFET Bias Curve 458
7.15 Practical Applications 461
7.16 Summary 470
7.17 Computer Analysis 471

CHAPTER 8: FET Amplifiers 481

8.1 Introduction 481
8.2 JFET Small-Signal Model 482
8.3 Fixed-Bias Configuration 489
8.4 Self-Bias Configuration 492
8.5 Voltage-Divider Configuration 497
8.6 Common-Gate Configuration 498
8.7 Source-Follower (Common-Drain) Configuration 501
8.8 Depletion-Type MOSFETs 505
8.9 Enhancement-Type MOSFETs 506
8.10 E-MOSFET Drain-Feedback Configuration 507
8.11 E-MOSFET Voltage-Divider Configuration 510
8.12 Designing FET Amplifier Networks 511
8.13 Summary Table 513
8.14 Effect of RL and Rsig 516
8.15 Cascade Configuration 518
8.16 Troubleshooting 521
8.17 Practical Applications 522
8.18 Summary 530
8.19 Computer Analysis 531
CHAPTER 9: BJT and JFET Frequency Response 545 CONTENTS xv
9.1 Introduction 545
9.2 Logarithms 545
9.3 Decibels 550
9.4 General Frequency Considerations 554
9.5 Normalization Process 557
9.6 Low-Frequency Analysis—Bode Plot 559
9.7 Low-Frequency Response—BJT Amplifier with RL 564
9.8 Impact of Rs on the BJT Low-Frequency Response 568
9.9 Low-Frequency Response—FET Amplifier 571
9.10 Miller Effect Capacitance 574
9.11 High-Frequency Response—BJT Amplifier 576
9.12 High-Frequency Response—FET Amplifier 584
9.13 Multistage Frequency Effects 586
9.14 Square-Wave Testing 588
9.15 Summary 591
9.16 Computer Analysis 592

CHAPTER 10: Operational Amplifiers 607

10.1 Introduction 607
10.2 Differential Amplifier Circuit 610
10.3 BiFET, BiMOS, and CMOS Differential Amplifier Circuits 617
10.4 Op-Amp Basics 620
10.5 Practical Op-Amp Circuits 623
10.6 Op-Amp Specifications—DC Offset Parameters 628
10.7 Op-Amp Specifications—Frequency Parameters 631
10.8 Op-Amp Unit Specifications 634
10.9 Differential and Common-Mode Operation 639
10.10 Summary 643
10.11 Computer Analysis 644

CHAPTER 11: Op-Amp Applications 653

11.1 Constant-Gain Multiplier 653
11.2 Voltage Summing 657
11.3 Voltage Buffer 660
11.4 Controlled Sources 661
11.5 Instrumentation Circuits 663
11.6 Active Filters 667
11.7 Summary 670
11.8 Computer Analysis 671

CHAPTER 12: Power Amplifiers 683

12.1 Introduction—Definitions and Amplifier Types 683
12.2 Series-Fed Class A Amplifier 685
xvi CONTENTS 12.3 Transformer-Coupled Class A Amplifier 688
12.4 Class B Amplifier Operation 695
12.5 Class B Amplifier Circuits 699
12.6 Amplifier Distortion 705
12.7 Power Transistor Heat Sinking 709
12.8 Class C and Class D Amplifiers 712
12.9 Summary 714
12.10 Computer Analysis 715

CHAPTER 13: Linear-Digital ICs 722

13.1 Introduction 722
13.2 Comparator Unit Operation 722
13.3 Digital–Analog Converters 729
13.4 Timer IC Unit Operation 732
13.5 Voltage-Controlled Oscillator 736
13.6 Phase-Locked Loop 738
13.7 Interfacing Circuitry 742
13.8 Summary 745
13.9 Computer Analysis 745

CHAPTER 14: Feedback and Oscillator Circuits 751

14.1 Feedback Concepts 751
14.2 Feedback Connection Types 752
14.3 Practical Feedback Circuits 758
14.4 Feedback Amplifier—Phase and Frequency Considerations 763
14.5 Oscillator Operation 766
14.6 Phase-Shift Oscillator 767
14.7 Wien Bridge Oscillator 770
14.8 Tuned Oscillator Circuit 771
14.9 Crystal Oscillator 774
14.10 Unijunction Oscillator 777
14.11 Summary 778
14.12 Computer Analysis 779

CHAPTER 15: Power Supplies (Voltage Regulators) 783

15.1 Introduction 783
15.2 General Filter Considerations 784
15.3 Capacitor Filter 786
15.4 RC Filter 789
15.5 Discrete Transistor Voltage Regulation 791
15.6 IC Voltage Regulators 798
15.7 Practical Applications 803
15.8 Summary 805
15.9 Computer Analysis 806
CHAPTER 16: Other Two-Terminal Devices 811 CONTENTS xvii
16.1 Introduction 811
16.2 Schottky Barrier (Hot-Carrier) Diodes 811
16.3 Varactor (Varicap) Diodes 815
16.4 Solar Cells 819
16.5 Photodiodes 824
16.6 Photoconductive Cells 826
16.7 IR Emitters 828
16.8 Liquid-Crystal Displays 829
16.9 Thermistors 831
16.10 Tunnel Diodes 833
16.11 Summary 837

CHAPTER 17: pnpn and Other Devices 841

17.1 Introduction 841
17.2 Silicon-Controlled Rectifier 841
17.3 Basic Silicon-Controlled Rectifier Operation 842
17.4 SCR Characteristics and Ratings 843
17.5 SCR Applications 845
17.6 Silicon-Controlled Switch 849
17.7 Gate Turn-Off Switch 851
17.8 Light-Activated SCR 852
17.9 Shockley Diode 854
17.10 Diac 854
17.11 Triac 856
17.12 Unijunction Transistor 857
17.13 Phototransistors 865
17.14 Opto-Isolators 867
17.15 Programmable Unijunction Transistor 869
17.16 Summary 874

Appendix A: Hybrid Parameters—Graphical Determinations

and Conversion Equations (Exact and Approximate) 879
A.1 Graphical Determination of the h-Parameters 879
A.2 Exact Conversion Equations 883
A.3 Approximate Conversion Equations 883

Appendix B: Ripple Factor and Voltage Calculations 885

B.1 Ripple Factor of Rectifier 885
B.2 Ripple Voltage of Capacitor Filter 886
B.3 Relation of Vdc and Vm to Ripple r 887
B.4 Relation of Vr (rms) and Vm to Ripple r 888
B.5 Relation Connecting Conduction Angle, Percentage
Ripple, and Ipeak兾Idc for Rectifier-Capacitor Filter Circuits 889
xviii CONTENTS Appendix C: Charts and Tables 891

Appendix D: Solutions to Selected

Odd-Numbered Problems 893

Index 901
 BJT AC Analysis
5
CHAPTER OBJECTIVES
●
● Become familiar with the re, hybrid, and hybrid p models for the BJT transistor.
● Learn to use the equivalent model to find the important ac parameters for an amplifier.
● Understand the effects of a source resistance and load resistor on the overall gain and
characteristics of an amplifier.
● Become aware of the general ac characteristics of a variety of important BJT
configurations.
● Begin to understand the advantages associated with the two-port systems approach to
single- and multistage amplifiers.
● Develop some skill in troubleshooting ac amplifier networks.

5.1 INTRODUCTION
●
The basic construction, appearance, and characteristics of the transistor were introduced in
Chapter 3. The dc biasing of the device was then examined in detail in Chapter 4. We now
begin to examine the ac response of the BJT amplifier by reviewing the models most fre-
quently used to represent the transistor in the sinusoidal ac domain.
One of our first concerns in the sinusoidal ac analysis of transistor networks is the mag-
nitude of the input signal. It will determine whether small-signal or large-signal techniques
should be applied. There is no set dividing line between the two, but the application—and
the magnitude of the variables of interest relative to the scales of the device characteristics—
will usually make it quite clear which method is appropriate. The small-signal technique is
introduced in this chapter, and large-signal applications are examined in Chapter 12.
There are three models commonly used in the small-signal ac analysis of transistor
networks: the re model, the hybrid p model, and the hybrid equivalent model. This chapter
introduces all three but emphasizes the re model.

5.2 AMPLIFICATION IN THE AC DOMAIN

●
It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device.
That is, the output sinusoidal signal is greater than the input sinusoidal signal, or, stated
another way, the output ac power is greater than the input ac power. The question then arises
as to how the ac power output can be greater than the input ac power. Conservation of energy
dictates that over time the total power output, Po, of a system cannot be greater than its power

253
254 BJT AC ANALYSIS input, Pi, and that the efficiency defined by h = Po >Pi cannot be greater than 1. The factor
missing from the discussion above that permits an ac power output greater than the input ac
power is the applied dc power. It is the principal contributor to the total output power even
though part of it is dissipated by the device and resistive elements. In other words, there is an
“exchange” of dc power to the ac domain that permits establishing a higher output ac power.
In fact, a conversion efficiency is defined by h = Po(ac) >Pi(dc), where Po(ac) is the ac power
to the load and Pi(dc) is the dc power supplied.
Perhaps the role of the dc supply can best be described by first considering the simple
dc network of Fig. 5.1. The resulting direction of flow is indicated in the figure with a plot
Idc R
Idc of the current i versus time. Let us now insert a control mechanism such as that shown in
+ Fig. 5.2. The control mechanism is such that the application of a relatively small signal to
E the control mechanism can result in a substantial oscillation in the output circuit.
–
Idc
Idc
Control iT R iT = Idc + iac
iT
mechanism
i +
Idc ic
E
–
iT
iT 0 t

0 t

FIG. 5.1 FIG. 5.2

Steady current established by a Effect of a control element on the steady-state flow of the electrical
dc supply. system of Fig. 5.1.

That is, for this example,

iac(p@p) W ic(p@p)
and amplification in the ac domain has been established. The peak-to-peak value of the
output current far exceeds that of the control current.
For the system of Fig. 5.2, the peak value of the oscillation in the output circuit is con-
trolled by the established dc level. Any attempt to exceed the limit set by the dc level will
result in a “clipping” (flattening) of the peak region at the high and low end of the output
signal. In general, therefore, proper amplification design requires that the dc and ac com-
ponents be sensitive to each other’s requirements and limitations.
However, it is extremely helpful to realize that:
The superposition theorem is applicable for the analysis and design of the dc and ac
components of a BJT network, permitting the separation of the analysis of the dc and
ac responses of the system.
In other words, one can make a complete dc analysis of a system before considering the
ac response. Once the dc analysis is complete, the ac response can be determined using a
completely ac analysis. It happens, however, that one of the components appearing in the
ac analysis of BJT networks will be determined by the dc conditions, so there is still an
important link between the two types of analysis.

5.3 BJT TRANSISTOR MODELING

●
The key to transistor small-signal analysis is the use of the equivalent circuits (models) to
be introduced in this chapter.
A model is a combination of circuit elements, properly chosen, that best approximates
the actual behavior of a semiconductor device under specific operating conditions.
Once the ac equivalent circuit is determined, the schematic symbol for the device can
be replaced by this equivalent circuit and the basic methods of circuit analysis applied to
determine the desired quantities of the network.
In the formative years of transistor network analysis the hybrid equivalent network was
employed the most frequently. Specification sheets included the parameters in their listing,
and analysis was simply a matter of inserting the equivalent circuit with the listed values.
The drawback to using this equivalent circuit, however, is that it is defined for a set of oper- BJT TRANSISTOR 255
ating conditions that might not match the actual operating conditions. In most cases, this is MODELING
not a serious flaw because the actual operating conditions are relatively close to the chosen
operating conditions on the data sheets. In addition, there is always a variation in actual
resistor values and given transistor beta values, so as an approximate approach it was quite
reliable. Manufacturers continue to specify the hybrid parameter values for a particular
operating point on their specification sheets. They really have no choice. They want to give
the user some idea of the value of each important parameter so comparisons can be made
between transistors, but they really do not know the user’s actual operating conditions.
In time the use of the re model became the more desirable approach because an impor-
tant parameter of the equivalent circuit was determined by the actual operating conditions
rather than using a data sheet value that in some cases could be quite different. Unfortu-
nately, however, one must still turn to the data sheets for some of the other parameters of
the equivalent circuit. The re model also failed to include a feedback term, which in some
cases can be important if not simply troublesome.
The re model is really a reduced version of the hybrid p model used almost exclusively
for high-frequency analysis. This model also includes a connection between output and
input to include the feedback effect of the output voltage and the input quantities. The full
hybrid model is introduced in Chapter 9.
Throughout the text the re model is the model of choice unless the discussion centers
on the description of each model or a region of examination that predetermines the model
that should be used. Whenever possible, however, a comparison between models will be
discussed to show how closely related they really are. It is also important that once you gain
a proficiency with one model it will carry over to an investigation using a different model,
so moving from one to another will not be a dramatic undertaking.
In an effort to demonstrate the effect that the ac equivalent circuit will have on the
analysis to follow, consider the circuit of Fig. 5.3. Let us assume for the moment that the
small-signal ac equivalent circuit for the transistor has already been determined. Because
we are interested only in the ac response of the circuit, all the dc supplies can be replaced
by a zero-potential equivalent (short circuit) because they determine only the dc (quiescent
level) of the output voltage and not the magnitude of the swing of the ac output. This is
clearly demonstrated by Fig. 5.4. The dc levels were simply important for determining the
proper Q-point of operation. Once determined, the dc levels can be ignored in the ac analy-
sis of the network. In addition, the coupling capacitors C1 and C2 and bypass capacitor C3
were chosen to have a very small reactance at the frequency of application. Therefore, they,
too, may for all practical purposes be replaced by a low-resistance path or a short circuit.
Note that this will result in the “shorting out” of the dc biasing resistor RE. Recall that ca-
pacitors assume an “open-circuit” equivalent under dc steady-state conditions, permitting
an isolation between stages for the dc levels and quiescent conditions.

FIG. 5.3
Transistor circuit under examination in this introductory discussion.
256 BJT AC ANALYSIS
Io

+
Ii

Zo
+ Vo
Zi

Vi

–
–

FIG. 5.4
The network of Fig. 5.3 following removal of the dc
supply and insertion of the short-circuit equivalent
for the capacitors.

It is important as you progress through the modifications of the network to define the ac
equivalent that the parameters of interest such as Zi, Zo, Ii, and Io as defined by Fig. 5.5 be
carried through properly. Even though the network appearance may change, you want to be
sure the quantities you find in the reduced network are the same as defined by the original
network. In both networks the input impedance is defined from base to ground, the input
current as the base current of the transistor, the output voltage as the voltage from collector
to ground, and the output current as the current through the load resistor RC.

Ii Io

+ + Ii Io
Vi System Vo
Zi Zo + + + +
– – Vi Ri Ro Vo
– – – –

FIG. 5.5 FIG. 5.6

Defining the important parameters Demonstrating the reason for the defined
of any system. directions and polarities.

The parameters of Fig. 5.5 can be applied to any system whether it has one or a thou-
sand components. For all the analysis to follow in this text, the directions of the currents,
the polarities of the voltages, and the direction of interest for the impedance levels are as
appearing in Fig. 5.5. In other words, the input current Ii and output current Io are, by defini-
tion, defined to enter the system. If, in a particular example, the output current is leaving the
system rather than entering the system as shown in Fig. 5.5, a minus sign must be applied.
The defined polarities for the input and output voltages are also as appearing in Fig. 5.5. If
Vo has the opposite polarity, the minus sign must be applied. Note that Zi is the impedance
“looking into” the system, whereas Zo is the impedance “looking back into” the system
from the output side. By choosing the defined directions for the currents and voltages as
appearing in Fig. 5.5, both the input impedance and output impedance are defined as having
positive values. For example, in Fig. 5.6 the input and output impedances for a particular
system are both resistive. For the direction of Ii and Io the resulting voltage across the resis-
tive elements will have the same polarity as Vi and Vo, respectively. If Io had been defined
as the opposite direction in Fig. 5.5 a minus sign would have to be applied. For each case
Zi = Vi >Ii and Zo = Vo >Io with positive results if they all have the defined directions and
polarity of Fig. 5.5. If the output current of an actual system has a direction opposite to that
of Fig. 5.5 a minus sign must be applied to the result because Vo must be defined as appear- THE r e TRANSISTOR 257
ing in Fig. 5.5. Keep Fig. 5.5 in mind as you analyze the BJT networks in this chapter. It is MODEL
an important introduction to “System Analysis,” which is becoming so important with the
expanded use of packaged IC systems.
If we establish a common ground and rearrange the elements of Fig. 5.4, R1 and R2 will
be in parallel, and RC will appear from collector to emitter as shown in Fig. 5.7. Because
the components of the transistor equivalent circuit appearing in Fig. 5.7 employ familiar
components such as resistors and independent controlled sources, analysis techniques
such as superposition, Thévenin’s theorem, and so on, can be applied to determine the
desired quantities.

Ii

B
Zi

FIG. 5.7
Circuit of Fig. 5.4 redrawn for small-signal ac analysis.

Let us further examine Fig. 5.7 and identify the important quantities to be determined
for the system. Because we know that the transistor is an amplifying device, we would
expect some indication of how the output voltage Vo is related to the input voltage Vi—
the voltage gain. Note in Fig. 5.7 for this configuration that the current gain is defined
by Ai = Io >Ii.
In summary, therefore, the ac equivalent of a transistor network is obtained by:
1. Setting all dc sources to zero and replacing them by a short-circuit equivalent
2. Replacing all capacitors by a short-circuit equivalent
3. Removing all elements bypassed by the short-circuit equivalents introduced by steps
1 and 2
4. Redrawing the network in a more convenient and logical form
In the sections to follow, a transistor equivalent model will be introduced to complete
the ac analysis of the network of Fig. 5.7.

5.4 THE re TRANSISTOR MODEL

●
The re model for the CE, CB, and CC BJT transistor configurations will now be introduced
with a short description of why each is a good approximation to the actual behavior of a
BJT transistor.

C
Ib
Common-Emitter Configuration B

The equivalent circuit for the common-emitter configuration will be constructed using the + +
device characteristics and a number of approximations. Starting with the input side, we find Vi Vbe E
the applied voltage Vi is equal to the voltage Vbe with the input current being the base cur- Ie
– –
rent Ib as shown in Fig. 5.8.
Recall from Chapter 3 that because the current through the forward-biased junction of
the transistor is IE, the characteristics for the input side appear as shown in Fig. 5.9a for FIG. 5.8
various levels of VBE. Taking the average value for the curves of Fig. 5.9a will result in the Finding the input equivalent circuit
single curve of Fig. 5.9b, which is simply that of a forward-biased diode. for a BJT transistor.
258 BJT AC ANALYSIS IE IE

Various Average
values value
of VCB of VCB

0 0.7 V VBE 0 0.7 V VBE

(a) (b)

FIG. 5.9
Defining the average curve for the characteristics of Fig. 5.9a.

Ic
Ib For the equivalent circuit, therefore, the input side is simply a single diode with a current
Ie, as shown in Fig. 5.10. However, we must now add a component to the network that will
+
establish the current Ie of Fig. 5.10 using the output characteristics.
Ie
Vbe If we redraw the collector characteristics to have a constant b as shown in Fig. 5.11
(another approximation), the entire characteristics at the output section can be replaced by
–
a controlled source whose magnitude is beta times the base current as shown in Fig. 5.11.
Because all the input and output parameters of the original configuration are now present, the
FIG. 5.10 equivalent network for the common-emitter configuration has been established in Fig. 5.12.
Equivalent circuit for the input side
of a BJT transistor. IC
IB6

IB5
Ic
IB4
+
IB3
β Ib
Constant β
Ib
IB2
Vce
+ Ie
IB1
Vbe

0 VCE – –

FIG. 5.11 FIG. 5.12

Constant b characteristics. BJT equivalent circuit.

The equivalent model of Fig. 5.12 can be awkward to work with due to the direct con-
nection between input and output networks. It can be improved by first replacing the diode
by its equivalent resistance as determined by the level of IE, as shown in Fig. 5.13. Recall
from Section 1.8 that the diode resistance is determined by rD = 26 mV>ID. Using the sub-
script e because the determining current is the emitter current will result in re = 26 mV>IE.
Vi Vbe
β Ib Now, for the input side: Zi = =
Ib Ib Ib
Solving for Vbe: Vbe = Iere = (Ic + Ib)re = (bIb + Ib)re
+ + Ie
= (b + 1)Ibre
Vi Vbe Zi re
Vbe (b + 1)Ibre
and Zi = =
– – Ib Ib

FIG. 5.13
Zi = (b + 1)re ⬵ bre (5.1)
Defining the level of Zi.
The result is that the impedance seen “looking into” the base of the network is a resistor THE r e TRANSISTOR 259
equal to beta times the value of re, as shown in Fig. 5.14. The collector output current is MODEL
still linked to the input current by beta as shown in the same figure.

Ib Ic
b c

β re β Ib

e e

FIG. 5.14
Improved BJT equivalent circuit.

The equivalent circuit has therefore been defined for the ideal characteristics of Fig. 5.11,
but now the input and output circuits are isolated and only linked by the controlled source—a
form much easier to work with when analyzing networks.

Early Voltage
We now have a good representation for the input circuit, but aside from the collector out-
put current being defined by the level of beta and IB, we do not have a good representation
for the output impedance of the device. In reality the characteristics do not have the ideal
appearance of Fig. 5.11. Rather, they have a slope as shown In Fig. 5.15 that defines the
output impedance of the device. The steeper the slope, the less the output impedance and
the less ideal the transistor. In general, it is desirable to have large output impedances to
avoid loading down the next stage of a design. If the slope of the curves is extended until
they reach the horizontal axis, it is interesting to note in Fig. 5.15 that they will all intersect
at a voltage called the Early voltage. This intersection was first discovered by James M.
Early in 1952. As the base current increases the slope of the line increases, resulting in an
increase in output impedance with increase in base and collector current. For a particular
collector and base current as shown in Fig. 5.15, the output impedance can be found using
the following equation:

V VA + VCEQ
ro = = (5.2)
I ICQ

IC (mA)
1
Slope = ro
1
ΔIC
ΔVCE

1 ICQ
Slope = ro
2
ΔIC
ΔVCE

VA 0 VCEQ VCE (V)

VA + VCEQ

FIG. 5.15
Defining the Early voltage and the output impedance of a transistor.
260 BJT AC ANALYSIS Typically, however, the Early voltage is sufficiently large compared with the applied
collector-to-emitter voltage to permit the following approximation.

VA
ro ⬵ (5.3)
ICQ

Clearly, since VA is a fixed voltage, the larger the collector current, the less the output
impedance.
For situations where the Early voltage is not available the output impedance can be found
from the characteristics at any base or collector current using the following equation:
⌬y ⌬IC 1
Slope = = =
⌬x ⌬VCE r o

⌬VCE
and ro = (5.4)
⌬IC

For the same change in voltage in Fig. 5.15 the resulting change in current ¢ IC is signifi-
cantly less for ro2 than ro1, resulting in ro2 being much larger than ro1.
In situations where the specification sheets of a transistor do not include the Early volt-
age or the output characteristics, the output impedance can be determined from the hybrid
parameter hoe that is normally plotted on every specification sheet. It is a quantity that will
be described in detail in Section 5.19.
In any event, an output impedance can now be defined that will appear as a resistor in
parallel with the output as shown in the equivalent circuit of Fig. 5.16.

FIG. 5.16
re model for the common-emitter transistor configuration
including effects of ro.

The equivalent circuit of Fig. 5.16 will be used throughout the analysis to follow for the
common-emitter configuration. Typical values of beta run from 50 to 200, with values of
bre typically running from a few hundred ohms to a maximum of 6 k⍀ to 7 k⍀. The output
resistance r is typically in the range of 40 k⍀ to 50 k⍀.

Common-Base Configuration
The common-base equivalent circuit will be developed in much the same manner as
applied to the common-emitter configuration. The general characteristics of the input and
output circuit will generate an equivalent circuit that will approximate the actual behavior
of the device. Recall for the common-emitter configuration the use of a diode to represent
the connection from base to emitter. For the common-base configuration of Fig. 5.17a the
pnp transistor employed will present the same possibility at the input circuit. The result is
the use of a diode in the equivalent circuit as shown in Fig. 5.17b. For the output circuit, if
we return to Chapter 3 and review Fig. 3.8, we find that the collector current is related to
the emitter current by alpha a. In this case, however, the controlled source defining the
collector current as inserted in Fig. 5.17b is opposite in direction to that of the controlled
source of the common-emitter configuration. The direction of the collector current in the
output circuit is now opposite that of the defined output current.
 Ii Ie Ic Io Ii Ie Ic Io

+ +

Vi Vo
Zi Zo Zi Zo

− −

(a) (b)

FIG. 5.17
(a) Common-base BJT transistor; (b) equivalent circuit for configuration of (a).

For the ac response, the diode can be replaced by its equivalent ac resistance determined
by re = 26 mV>IE as shown in Fig. 5.18. Take note of the fact that the emitter current
continues to determine the equivalent resistance. An additional output resistance can be
determined from the characteristics of Fig. 5.19 in much the same manner as applied to the
common-emitter configuration. The almost horizontal lines clearly reveal that the output
resistance ro as appearing in Fig. 5.18 will be quite high and certainly much higher than that
for the typical common-emitter configuration.
The network of Fig. 5.18 is therefore an excellent equivalent circuit for the analysis of
most common-base configurations. It is similar in many ways to that of the common-emitter
configuration. In general, common-base configurations have very low input impedance
because it is essentially simply re. Typical values extend from a few ohms to perhaps 50 .
The output impedance ro will typically extend into the megohm range. Because the output
current is opposite to the defined Io direction, you will find in the analysis to follow that
there is no phase shift between the input and output voltages. For the common-emitter
configuration there is a 180° phase shift.

Ii Ie Ic Io

+ +

ro
Vi Zi Zo Vo

– –

FIG. 5.18
Common base re equivalent circuit.

IC (mA) 1
Slope = ro
IE = 4 mA
4

IE = 3 mA
3

IE = 2 mA
2

IE = 1 mA
1

IE = 0 mA
0 VCB

FIG. 5.19
Defining Zo.
261
262 BJT AC ANALYSIS Common-Collector Configuration
For the common-collector configuration, the model defined for the common-emitter configu-
ration of Fig. 5.16 is normally applied rather than defining a model for the common-collector
configuration. In subsequent chapters, a number of common-collector configurations will be
investigated, and the effect of using the same model will become quite apparent.

npn versus pnp

The dc analysis of npn and pnp configurations is quite different in the sense that the currents
will have opposite directions and the voltages opposite polarities. However, for an ac analy-
sis where the signal will progress between positive and negative values, the ac equivalent
circuit will be the same.

5.5 COMMON-EMITTER FIXED-BIAS

CONFIGURATION
●
The transistor models just introduced will now be used to perform a small-signal ac analy-
sis of a number of standard transistor network configurations. The networks analyzed rep-
resent the majority of those appearing in practice. Modifications of the standard
configurations will be relatively easy to examine once the content of this chapter is reviewed
and understood. For each configuration, the effect of an output impedance is examined for
completeness.
The computer analysis section includes a brief description of the transistor model em-
ployed in the PSpice and Multisim software packages. It demonstrates the range and depth
of the available computer analysis systems and how relatively easy it is to enter a complex
network and print out the desired results. The first configuration to be analyzed in detail is
the common-emitter fixed-bias network of Fig. 5.20. Note that the input signal Vi is applied
to the base of the transistor, whereas the output Vo is off the collector. In addition, recognize
that the input current Ii is not the base current, but the source current, and the output current
Io is the collector current. The small-signal ac analysis begins by removing the dc effects
of VCC and replacing the dc blocking capacitors C1 and C2 by short-circuit equivalents,
resulting in the network of Fig. 5.21.

VCC

RC
RB Io C Vo
C Vo
Ii Ii Io
C2 B
B Vi
Vi
RC
C1 Zo
Zo
RB E
E Zi
Zi

FIG. 5.20 FIG. 5.21

Common-emitter fixed-bias configuration. Network of Fig. 5.20 following the removal
of the effects of VCC, C1, and C2.

Note in Fig. 5.21 that the common ground of the dc supply and the transistor emitter
terminal permits the relocation of RB and RC in parallel with the input and output sections
of the transistor, respectively. In addition, note the placement of the important network
parameters Zi, Zo, Ii, and Io on the redrawn network. Substituting the re model for the
common-emitter configuration of Fig. 5.21 results in the network of Fig. 5.22.
The next step is to determine b, re, and ro. The magnitude of b is typically obtained
from a specification sheet or by direct measurement using a curve tracer or transistor
 COMMON-EMITTER 263
Ii Ib Ic FIXED-BIAS
CONFIGURATION
+Z b c +
i Io

Vi Vo
RB β re β Ib ro RC
– –
Zo

FIG. 5.22
Substituting the re model into the network of Fig. 5.21.

testing instrument. The value of re must be determined from a dc analysis of the system,
and the magnitude of ro is typically obtained from the specification sheet or characteristics.
Assuming that b, re, and ro have been determined will result in the following equations for
the important two-port characteristics of the system.

Zi Figure 5.22 clearly shows that

Zi = RB 7 bre ohms (5.5)

For the majority of situations RB is greater than bre by more than a factor of 10 (recall
from the analysis of parallel elements that the total resistance of two parallel resistors is
always less than the smallest and very close to the smallest if one is much larger than the
other), permitting the following approximation:

Zi ⬵ bre ohms (5.6)

RB Ú 10bre

Zo Recall that the output impedance of any system is defined as the impedance Zo
determined when Vi  0. For Fig. 5.22, when Vi  0, Ii = Ib = 0, resulting in an open-
Zo
circuit equivalence for the current source. The result is the configuration of Fig. 5.23.
ro RC
We have

Zo = RC 7 ro ohms (5.7)

If ro Ú 10RC, the approximation RC 7 ro ⬵ RC is frequently applied, and FIG. 5.23

Determining Zo for the network
Zo ⬵ RC (5.8) of Fig. 5.22.
ro Ú 10RC

Av The resistors ro and RC are in parallel, and

Vo = -bIb(RC 7 ro)
Vi
but Ib =
bre
Vi
so that Vo = -ba b (RC 7 ro)
bre

Vo (RC 7 ro)
and Av = = - (5.9)
Vi re

If ro Ú 10RC, so that the effect of ro can be ignored,

RC
Av = - (5.10)
re
ro Ú 10RC

Note the explicit absence of b in Eqs. (5.9) and (5.10), although we recognize that b must
be utilized to determine re.
264 BJT AC ANALYSIS Phase Relationship The negative sign in the resulting equation for Av reveals that a 180°
phase shift occurs between the input and output signals, as shown in Fig. 5.24. The is a
result of the fact that bIb establishes a current through RC that will result in a voltage across
RC, the opposite of that defined by Vo.

VCC

Vo
RC
RB
Vi Vo 0 t

0 t Vi

FIG. 5.24
Demonstrating the 180° phase shift between input and output waveforms.

EXAMPLE 5.1 For the network of Fig. 5.25:

a. Determine re.
b. Find Zi (with ro =  ).
c. Calculate Zo (with ro =  ).
d. Determine Av (with ro =  ).
e. Repeat parts (c) and (d) including ro = 50 k in all calculations and compare results.

12 V

3 kΩ
470 kΩ Io
Ii Vo
10 μ F
Vi
10 μ F β = 100 Zo
ro = 50 kΩ
Zi

FIG. 5.25
Example 5.1.

Solution:
a. DC analysis:
VCC - VBE 12 V - 0.7 V
IB = = = 24.04 mA
RB 470 k
IE = (b + 1)IB = (101)(24.04 mA) = 2.428 mA
26 mV 26 mV
re = = = 10.71 ⍀
IE 2.428 mA
b. bre = (100)(10.71 ) = 1.071 k
Zi = RB 7 bre = 470 k 7 1.071 k = 1.07 k⍀
c. Zo = RC = 3 k⍀
RC 3 k
d. Av = - = - = ⴚ280.11
re 10.71 
e. Zo = ro 7 RC = 50 k 7 3 k = 2.83 k⍀ vs. 3 k VOLTAGE-DIVIDER BIAS 265
ro 7 RC 2.83 k
Av = - = = ⴚ264.24 vs. -280.11
re 10.71 

5.6 VOLTAGE-DIVIDER BIAS

●
The next configuration to be analyzed is the voltage-divider bias network of Fig. 5.26.
Recall that the name of the configuration is a result of the voltage-divider bias at the input
side to determine the dc level of VB.
Substituting the re equivalent circuit results in the network of Fig. 5.27. Note the absence
of RE due to the low-impedance shorting effect of the bypass capacitor, CE. That is, at the
frequency (or frequencies) of operation, the reactance of the capacitor is so small compared
to RE that it is treated as a short circuit across RE. When VCC is set to zero, it places one
end of R1 and RC at ground potential as shown in Fig. 5.27. In addition, note that R1 and
R2 remain part of the input circuit, whereas RC is part of the output circuit. The parallel
combination of R1 and R2 is defined by

R1R2
R = R1 7 R2 = (5.11)
R1 + R2

Zi From Fig. 5.27

Zi = R 7 bre (5.12)

VCC

Io

RC
R1
C Vo
Ii C2
B
Vi
C1 Zo

E
Zi R2
RE CE

FIG. 5.26
Voltage-divider bias configuration.

Ii
b Ib c

+ Io +
Zi
Vi R1 R2 β re β Ib ro RC Vo

– e e Zo –

R'

FIG. 5.27
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.26.
266 BJT AC ANALYSIS Zo From Fig. 5.27 with Vi set to 0 V, resulting in Ib = 0 mA and bIb = 0 mA,

Zo = RC 7 ro (5.13)

If ro Ú 10RC,

Zo ⬵ RC (5.14)
ro Ú 10RC

Av Because RC and ro are in parallel,

Vo = -(bIb)(RC 7 ro)
Vi
and Ib =
bre
Vi
so that Vo = -ba b (RC 7 ro)
bre

Vo -RC 7 ro
and Av = = (5.15)
Vi re

which you will note is an exact duplicate of the equation obtained for the fixed-bias con-
figuration.
For ro Ú 10RC,

Vo RC
Av = ⬵ - (5.16)
Vi re
ro Ú 10RC

Phase Relationship The negative sign of Eq. (5.15) reveals a 180° phase shift between
Vo and Vi.

EXAMPLE 5.2 For the network of Fig. 5.28, determine:

a. re.
b. Zi.
c. Zo (ro =  ).
d. Av (ro =  ).
e. The parameters of parts (b) through (d) if ro = 50 k and compare results.

22 V

Io

6.8 kΩ
56 kΩ 10 μF
Vo
10 μ F
Vi β = 90 Zo

Ii

8.2 kΩ
Zi 20 μ F
1.5 kΩ

FIG. 5.28
Example 5.2.
Solution: CE EMITTER-BIAS 267
CONFIGURATION
a. DC: Testing bRE 7 10R2,
(90)(1.5 k) 7 10(8.2 k)
135 k 7 82 k (satisfied)
Using the approximate approach, we obtain
R2 (8.2 k)(22 V)
VB = V = = 2.81 V
R1 + R2 CC 56 k + 8.2 k
VE = VB - VBE = 2.81 V - 0.7 V = 2.11 V
VE 2.11 V
IE = = = 1.41 mA
RE 1.5 k
26 mV 26 mV
re = = = 18.44 ⍀
IE 1.41 mA
b. R = R1 7 R2 = (56 k) 7 (8.2 k) = 7.15 k
Zi = R 7 bre = 7.15 k 7 (90)(18.44 ) = 7.15 k 7 1.66 k
= 1.35 k⍀
c. Zo = RC = 6.8 k⍀
RC 6.8 k
d. Av = - = - = ⴚ368.76
re 18.44 
e. Zi = 1.35 k⍀
Zo = RC 7 ro = 6.8 k 7 50 k = 5.98 k⍀ vs. 6.8 k
RC 7 ro 5.98 k
Av = - = - = ⴚ324.3 vs. -368.76
re 18.44 
There was a measurable difference in the results for Zo and Av, because the condition
ro Ú 10RC was not satisfied.

5.7 CE EMITTER-BIAS CONFIGURATION

●
The networks examined in this section include an emitter resistor that may or may not be
bypassed in the ac domain. We first consider the unbypassed situation and then modify the
resulting equations for the bypassed configuration.

Unbypassed
The most fundamental of unbypassed configurations appears in Fig. 5.29. The re equiva-
lent model is substituted in Fig. 5.30, but note the absence of the resistance ro. The effect
of ro is to make the analysis a great deal more complicated, and considering the fact that in

VCC Ii
b c
Ib
+ +
RC β re β Ib
Zi Io
RB Io
Vo Zb Zo
Ii C2 Vi RB RC Vo
Vi e
C1 Ie = ( β + 1)Ib
Zo RE
RE
– –
Zi

FIG. 5.29 FIG. 5.30

CE emitter-bias configuration. Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.29.
268 BJT AC ANALYSIS most situations its effect can be ignored, it will not be included in the present analysis.
However, the effect of ro will be discussed later in this section.
Applying Kirchhoff’s voltage law to the input side of Fig. 5.30 results in
Vi = Ibbre + IeRE
or Vi = Ibbre + (b + I)IbRE
and the input impedance looking into the network to the right of RB is
Vi
Zb = = bre + (b + 1)RE
Ib
The result as displayed in Fig. 5.31 reveals that the input impedance of a transistor with
an unbypassed resistor RE is determined by

re β Zb = bre + (b + 1)RE (5.17)

Because b is normally much greater than 1, the approximate equation is

Zb
RE Zb ⬵ bre + bRE

and Zb ⬵ b(re + RE) (5.18)

FIG. 5.31
Defining the input impedance of a Because RE is usually greater than re, Eq. (5.18) can be further reduced to
transistor with an unbypassed
emitter resistor. Zb ⬵ bRE (5.19)

Zi Returning to Fig. 5.30, we have

Zi = RB 7 Zb (5.20)

Zo With Vi set to zero, Ib = 0, and bIb can be replaced by an open-circuit equivalent.

The result is

Zo = RC (5.21)

Av
Vi
Ib =
Zb
and Vo = -Io RC = -bIbRC
Vi
= -ba b RC
Zb

Vo bRC
with Av = = - (5.22)
Vi Zb

Substituting Zb ⬵ b(re + RE) gives

Vo RC
Av = ⬵ - (5.23)
Vi re + RE

and for the approximation Zb ⬵ bRE,

Vo RC
Av = ⬵ - (5.24)
Vi RE

Note the absence of b from the equation for Av demonstrating an independence in variation
of b.

Phase Relationship The negative sign in Eq. (5.22) again reveals a 180° phase shift
between Vo and Vi.
Effect of ro The equations appearing below will clearly reveal the additional complexity CE EMITTER-BIAS 269
resulting from including ro in the analysis. Note in each case, however, that when certain CONFIGURATION
conditions are met, the equations return to the form just derived. The derivation of each
equation is beyond the needs of this text and is left as an exercise for the reader. Each
equation can be derived through careful application of the basic laws of circuit analysis
such as Kirchhoff’s voltage and current laws, source conversions, Thévenin’s theorem,
and so on. The equations were included to remove the nagging question of the effect of ro
on the important parameters of a transistor configuration.

Zi

(b + 1) + RC>ro
Zb = bre + c dR (5.25)
1 + (RC + RE)>ro E

Because the ratio RC>ro is always much less than (b + 1),

(b + 1)RE
Zb ⬵ bre +
1 + (RC + RE)>ro
For ro Ú 10(RC + RE),
Zb ⬵ bre + (b + 1)RE
which compares directly with Eq. (5.17).
In other words, if ro Ú 10(RC + RE), all the equations derived earlier result. Because
b + 1 ⬵ b, the following equation is an excellent one for most applications:

Zb ⬵ b(re + RE) (5.26)

ro Ú 10(RC + RE)

Zo

b(ro + re)
Zo = RC 储 £ ro + (5.27)
bre §
1 +
RE

However, ro W re, and

b
Zo ⬵ RC 储 ro £ 1 +
bre §
1 +
RE

which can be written as

1
Zo ⬵ RC 储 ro £ 1 +
1 re §
+
b RE

Typically 1>b and re>RE are less than one with a sum usually less than one. The result
is a multiplying factor for ro greater than one. For b = 100, re = 10 , and RE = 1 k,
1 1 1
= = = 50
1 re 1 10  0.02
+ +
b RE 100 1000 
and Zo = RC 7 51ro
which is certainly simply RC. Therefore,

Zo ⬵ RC (5.28)
Any level of ro

which was obtained earlier.

270 BJT AC ANALYSIS Av

bRC re RC
- c1 + d +
Vo Zb ro ro
Av = = (5.29)
Vi RC
1 +
ro
re
The ratio V 1, and
ro
bRC RC
- +
Vo Zb ro
Av = ⬵
Vi RC
1 +
ro
For ro Ú 10RC,

Vo bRC
Av = ⬵ - (5.30)
Vi Zb ro Ú 10RC

as obtained earlier.

Bypassed
If RE of Fig. 5.29 is bypassed by an emitter capacitor CE, the complete re equivalent model
can be substituted, resulting in the same equivalent network as Fig. 5.22. Equations (5.5)
to (5.10) are therefore applicable.

EXAMPLE 5.3 For the network of Fig. 5.32, without CE (unbypassed), determine:
a. re.
b. Zi. 20 V
c. Zo.
d. Av.
Io

2.2 kΩ
10 μ F
470 kΩ
Vo
C2
10 μ F Zo
Vi β = 120, ro = 40 kΩ
Ii C1

Zi 0.56 kΩ CE
10 μ F

FIG. 5.32
Example 5.3.

Solution:
a. DC:
VCC - VBE 20 V - 0.7 V
IB = = = 35.89 mA
RB + (b + 1)RE 470 k + (121)0.56 k
IE = (b + 1)IB = (121)(35.89 mA) = 4.34 mA
26 mV 26 mV
and re = = = 5.99 ⍀
IE 4.34 mA
b. Testing the condition ro Ú 10(RC + RE), we obtain CE EMITTER-BIAS 271
CONFIGURATION
40 k Ú 10(2.2 k + 0.56 k)
40 k Ú 10(2.76 k) = 27.6 k (satisfied)
Therefore,
Zb ⬵ b(re + RE) = 120(5.99  + 560 )
= 67.92 k
and Zi = RB Zb = 470 k 7 67.92 k
7
= 59.34 k⍀
c. Zo = RC = 2.2 k⍀
d. ro Ú 10RC is satisfied. Therefore,
Vo bRC (120)(2.2 k)
Av = ⬵ - = -
Vi Zb 67.92 k
= ⴚ3.89
compared to -3.93 using Eq. (5.20): Av ⬵ -RC>RE.

EXAMPLE 5.4 Repeat the analysis of Example 5.3 with CE in place.

Solution:
a. The dc analysis is the same, and re = 5.99 .
b. RE is “shorted out” by CE for the ac analysis. Therefore,
Zi = RB 7 Zb = RB 7 bre = 470 k 7 (120)(5.99 )
= 470 k 7 718.8  ⬵ 717.70 ⍀
c. Zo = RC = 2.2 k⍀
RC
d. Av = -
re
2.2 k
= - = ⴚ367.28 (a significant increase)
5.99 

EXAMPLE 5.5 For the network of Fig. 5.33 (with CE unconnected), determine (using
appropriate approximations):
a. re.
b. Zi.
c. Zo.
d. Av.

16 V

Io

2.2 kΩ
90 kΩ

+
C2
Vi β = 210, ro = 50 kΩ
Ii C1
Zo
Vo
Zi 10 kΩ
0.68 kΩ CE

FIG. 5.33
Example 5.5.
272 BJT AC ANALYSIS Solution:
a. Testing bRE 7 10R2,
(210)(0.68 k) 7 10(10 k)
142.8 k 7 100 k (satisfied)
we have
R2 10 k
VB = VCC = (16 V) = 1.6 V
R1 + R2 90 k + 10 k
VE = VB - VBE = 1.6 V - 0.7 V = 0.9 V
VE 0.9 V
IE = = = 1.324 mA
RE 0.68 k
26 mV 26 mV
re = = = 19.64 ⍀
IE 1.324 mA
b. The ac equivalent circuit is provided in Fig. 5.34. The resulting configuration is differ-
ent from Fig. 5.30 only by the fact that now
RB = R = R1 7 R2 = 9 k

Ii +
+ Io
Zo
Zi 2.2 kΩ Vo
Vi 10 kΩ 90 kΩ
0.68 kΩ
– –

R'

FIG. 5.34
The ac equivalent circuit of Fig. 5.33.

The testing conditions of ro Ú 10(RC + RE) and ro Ú 10RC are both satisfied. Using
the appropriate approximations yields
Zb ⬵ bRE = 142.8 k
Zi = RB 7 Zb = 9 k 7 142.8 k
= 8.47 k⍀
c. Zo = RC = 2.2 k⍀
RC 2.2 k
d. Av = - = - = ⴚ3.24
RE 0.68 k

EXAMPLE 5.6 Repeat Example 5.5 with CE in place.

Solution:
a. The dc analysis is the same, and re = 19.64 ⍀.
b. Zb = bre = (210)(19.64 ) ⬵ 4.12 k
Zi = RB 7 Zb = 9 k 7 4.12 k
= 2.83 k⍀
c. Zo = RC = 2.2 k⍀
RC 2.2 k
d. Av = - = - = ⴚ112.02 (a significant increase)
re 19.64 

Another variation of an emitter-bias configuration is shown in Fig. 5.35. For the dc

analysis, the emitter resistance is RE1 + RE2, whereas for the ac analysis, the resistor RE in
the equations above is simply RE1 with RE2 bypassed by CE.
 VCC EMITTER-FOLLOWER 273
CONFIGURATION
Io
RC
RB C2
Vo
C1
Vi

Ii

RE Zo
1
Zi

RE CE
2

FIG. 5.35
An emitter-bias configuration with a
portion of the emitter-bias resistance
bypassed in the ac domain.

5.8 EMITTER-FOLLOWER CONFIGURATION

●
When the output is taken from the emitter terminal of the transistor as shown in Fig. 5.36,
the network is referred to as an emitter-follower. The output voltage is always slightly less
than the input signal due to the drop from base to emitter, but the approximation Av ⬵ 1
is usually a good one. Unlike the collector voltage, the emitter voltage is in phase with the
signal Vi. That is, both Vo and Vi attain their positive and negative peak values at the same
time. The fact that Vo “follows” the magnitude of Vi with an in-phase relationship accounts
for the terminology emitter-follower.

VCC

RB C
Ii
B
Vi
C1 C2
E Vo
Io
Zi RE

Zo

FIG. 5.36
Emitter-follower configuration.

The most common emitter-follower configuration appears in Fig. 5.36. In fact, because
the collector is grounded for ac analysis, it is actually a common-collector configuration.
Other variations of Fig. 5.36 that draw the output off the emitter with Vo ⬵ Vi will appear
later in this section.
The emitter-follower configuration is frequently used for impedance-matching pur-
poses. It presents a high impedance at the input and a low impedance at the output, which
is the direct opposite of the standard fixed-bias configuration. The resulting effect is much
the same as that obtained with a transformer, where a load is matched to the source imped-
ance for maximum power transfer through the system.
Substituting the re equivalent circuit into the network of Fig. 5.36 results in the network
of Fig. 5.37. The effect of ro will be examined later in the section.
274 BJT AC ANALYSIS Ii
b c
Ib
+
β re β Ib

Zi
Vi RB

e
+
Io

Zb Zo Vo
RE
– Ie = ( β + 1) Ib –

FIG. 5.37
Substituting the re equivalent circuit into the ac
equivalent network of Fig. 5.36.

Zi The input impedance is determined in the same manner as described in the preceding
section:

Zi = RB 7 Zb (5.31)

with Zb = bre + (b + 1)RE (5.32)

or Zb ⬵ b(re + RE) (5.33)

and Zb ⬵ bRE RE W re
(5.34)

Zo The output impedance is best described by first writing the equation for the current Ib,
Vi
Ib =
Zb
and then multiplying by (b + 1) to establish Ie. That is,
Vi
Ie = (b + 1)Ib = (b + 1)
Zb
Substituting for Zb gives
(b + 1)Vi
Ie =
bre + (b + 1)RE
Vi
or Ie =
[bre >(b + 1)] + RE
but (b + 1) ⬵ b
bre bre
and ⬵ = re
b + 1 b
re
Vo
Vi
+ Ie so that Ie ⬵ (5.35)
re + RE
Vi RE
Zo
– If we now construct the network defined by Eq. (5.35), the configuration of Fig. 5.38
results.
To determine Zo, Vi is set to zero and
FIG. 5.38
Defining the output impedance for
Zo = RE 7 re (5.36)
the emitter-follower configuration.
Because RE is typically much greater than re, the following approximation is often applied: EMITTER-FOLLOWER 275
CONFIGURATION
Zo ⬵ r e (5.37)

Av Figure 5.38 can be used to determine the voltage gain through an application of the
voltage-divider rule:
REVi
Vo =
RE + re

Vo RE
and Av = = (5.38)
Vi RE + re

Because RE is usually much greater than re, RE + re ⬵ RE and

Vo
Av = ⬵1 (5.39)
Vi

Phase Relationship As revealed by Eq. (5.38) and earlier discussions of this section, Vo
and Vi are in phase for the emitter-follower configuration.

Effect of ro
Zi

(b + 1)RE
Zb = bre + (5.40)
RE
1 +
ro

If the condition ro Ú 10RE is satisfied,

Zb = bre + (b + 1)RE
which matches earlier conclusions with

Zb ⬵ b(re + RE) ro Ú 10RE

(5.41)

Zo

bre
Zo = ro 储 RE 储 (5.42)
(b + 1)

Using b + 1 ⬵ b, we obtain
Zo = ro 7 RE 7 re
and because ro W re,

Zo ⬵ RE 7 re Any ro
(5.43)

Av

(b + 1)RE>Zb
Av = (5.44)
RE
1 +
ro

If the condition ro Ú 10RE is satisfied and we use the approximation b + 1 ⬵ b, we find

bRE
Av ⬵
Zb
276 BJT AC ANALYSIS But Zb ⬵ b(re + RE)
bRE
so that Av ⬵
b(re + RE)

RE
and Av ⬵ (5.45)
re + RE ro Ú 10RE

EXAMPLE 5.7 For the emitter-follower network of Fig. 5.39, determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) with ro = 25 k and compare results.
12 V

RB 220 kΩ
10 μ F
Vi β = 100, ro = ∞ Ω

Ii 10 μ F
Vo

Io

Zi RE 3.3 kΩ

Zo

FIG. 5.39
Example 5.7.
Solution:
VCC - VBE
a. IB =
RB + (b + 1)RE
12 V - 0.7 V
= = 20.42 mA
220 k + (101)3.3 k
IE = (b + 1)IB
= (101)(20.42 mA) = 2.062 mA
26 mV 26 mV
re = = = 12.61 ⍀
IE 2.062 mA
b. Zb = bre + (b + 1)RE
= (100)(12.61 ) + (101)(3.3 k)
= 1.261 k + 333.3 k
= 334.56 k ⬵ bRE
Zi = RB 7 Zb = 220 k 7 334.56 k
= 132.72 k⍀
c. Zo = RE 7 re = 3.3 k 7 12.61 
= 12.56 ⍀ ⬵ re
Vo RE 3.3 k
d. Av = = =
Vi RE + re 3.3 k + 12.61 
= 0.996 @ 1
e. Checking the condition ro Ú 10RE, we have COMMON-BASE 277
CONFIGURATION
25 k Ú 10(3.3 k) = 33 k
which is not satisfied. Therefore,
(b + 1)RE (100 + 1)3.3 k
Zb = bre + = (100)(12.61 ) +
RE 3.3 k
1 + 1 +
ro 25 k
=
1.261 k + 294.43 k
=
295.7 k
with RB 7 Zb = 220 k 7 295.7 k
Zi =
=
126.15 k⍀ vs. 132.72 k obtained earlier
RE 7 re = 12.56 ⍀ as obtained earlier
Zo =
(b + 1)RE >Zb (100 + 1)(3.3 k)>295.7 k
Av = =
RE 3.3 k
c1 + d c1 + d
ro 25 k
= 0.996 @ 1
matching the earlier result.

In general, therefore, even though the condition ro Ú 10RE is not satisfied, the results
for Zo and Av are the same, with Zi only slightly less. The results suggest that for most ap-
plications a good approximation for the actual results can be obtained by simply ignoring
the effects of ro for this configuration.
The network of Fig. 5.40 is a variation of the network of Fig. 5.36, which employs
a voltage-divider input section to set the bias conditions. Equations (5.31) to (5.34) are
changed only by replacing RB by R = R1 7 R2.
The network of Fig. 5.41 also provides the input/output characteristics of an emitter-
follower, but includes a collector resistor RC. In this case RB is again replaced by the parallel
combination of R1 and R2. The input impedance Zi and output impedance Zo are unaffected
by RC because it is not reflected into the base or emitter equivalent networks. In fact, the
only effect of RC is to determine the Q-point of operation.

VCC VCC

RC
R1 R1

Ii C1
Vi Vi
C1 C2 C2
Vo Vo
R2 R2 Io
Zi Io Zi
RE RE
Zo Zo

FIG. 5.40 FIG. 5.41

Emitter-follower configuration with a Emitter-follower configuration with
voltage-divider biasing arrangement. a collector resistor RC.

5.9 COMMON-BASE CONFIGURATION

●
The common-base configuration is characterized as having a relatively low input and a high
output impedance and a current gain less than 1. The voltage gain, however, can be quite
large. The standard configuration appears in Fig. 5.42, with the common-base re equivalent
model substituted in Fig. 5.43. The transistor output impedance ro is not included for the
 Ic
Ii Ie Ic e Ie c

+ E C + + Ii Io
+
Io
RE RC Vi RE re α Ie RC Vo Zo
Vi Zi Vo Zo Zi
+ B – – –
V EE VCC
– – + –

FIG. 5.42 FIG. 5.43

Common-base configuration. Substituting the re equivalent circuit into the ac equivalent network
of Fig. 5.44.

common-base configuration because it is typically in the megohm range and can be ignored
in parallel with the resistor RC.
Zi
Zi = RE 7 re (5.46)
Zo
Zo = RC (5.47)

Av
Vo = -Io RC = -(-Ic)RC = aIe RC
Vi
with Ie =
re
Vi
so that Vo = a a bR
re C

Vo aRC RC
and Av = = ⬵ (5.48)
Vi re re

Ai Assuming that RE W re yields

Ie = Ii
and Io = -aIe = -aIi

Io
with Ai = = -a ⬵ -1 (5.49)
Ii

Phase Relationship The fact that Av is a positive number shows that Vo and Vi are in
phase for the common-base configuration.

Effect of ro For the common-base configuration, ro = 1>hob is typically in the megohm

range and sufficiently larger than the parallel resistance RC to permit the approximation
ro 7 RC ⬵ RC.

EXAMPLE 5.8 For the network of Fig. 5.44, determine:

a. re.
10 μ F Ie ⬵ Ii 10 μF
b. Zi.
c. Zo. + Io +
d. Av. Ii
RE 1 kΩ α = 0.98 RC 5 kΩ
e. Ai. Vi ro = 1 MΩ Vo
Zi + – Zo
2V 8V
– – + –

FIG. 5.44
Example 5.8.
278
Solution: COLLECTOR FEEDBACK 279
CONFIGURATION
VEE - VBE 2 V - 0.7 V 1.3 V
a. IE = = = = 1.3 mA
RE 1 k 1 k
26 mV 26 mV
re = = = 20 ⍀
IE 1.3 mA
b. Zi = RE 7 re = 1 k 7 20 
= 19.61 ⍀ ⬵ re
c. Zo = RC = 5 k⍀
RC 5 k
d. Av ⬵ = = 250
re 20 
e. Ai = ⴚ0.98 ⬵ -1

5.10 COLLECTOR FEEDBACK CONFIGURATION

●
The collector feedback network of Fig. 5.45 employs a feedback path from collector to
base to increase the stability of the system as discussed in Section 4.6. However, the sim-
ple maneuver of connecting a resistor from base to collector rather than base to dc supply
has a significant effect on the level of difficulty encountered when analyzing the network.
Some of the steps to be performed below are the result of experience working with
such configurations. It is not expected that a new student of the subject would choose
the sequence of steps described below without taking a wrong step or two. Substituting the
equivalent circuit and redrawing the network results in the configuration of Fig. 5.46. The
effects of a transistor output resistance ro will be discussed later in the section.

VCC

RC
RF Io
Vo
C2
C
B – RF + C Io
Ii
B + Ii Ib Ic +
Vi I'
Zo
C1 Vi β re β Ib RC Zo V
o
Zi
E
Zi – –

FIG. 5.45 FIG. 5.46

Collector feedback configuration. Substituting the re equivalent circuit into the ac
equivalent network of Fig. 5.45.

Zi
Io = I + bIb
Vo - Vi
and I =
RF
but Vo = -Io RC = -(I + bIb)RC
with Vi = Ibbre
(I + bIb)RC - Ibbre IRC bIb RC Ibbre
so that I = - = - - -
RF RF RF RF
which when rearranged in the following:
RC (RC + re)
Ia 1 + b = -bIb
RF RF
280 BJT AC ANALYSIS (RC + re)
and finally, I = -bIb
RC + RF
Vi
Now Zi = :
Ii
(RC + re)
and Ii = Ib - I = Ib + bIb
RC + RF
(RC + re)
or Ii = Ib a 1 + b b
RC + RF
Substituting for Vi in the above equation for Zi leaves
Vi Ibbre bre
Zi = = =
Ii (RC + r e) (RC + re)
Ib a 1 + b b 1 + b
RC + RF RC + RF

Since RC W re
bre
Zi =
bRC
1 +
RC + RF

re
or Zi = (5.50)
1 RC
+
b RC + RF

Zo If we set Vi to zero as required to define Zo, the network will appear as shown in Fig. 5.47.
The effect of bre is removed, and RF appears in parallel with RC and

Zo ⬵ RC 7 RF (5.51)

RF

Ib = 0 A

Vi = 0 β re β Ib = 0 A RC Zo

FIG. 5.47
Defining Zo for the collector feedback configuration.

Av
Vo = -Io RC = -(I + bIb)RC
(RC + re)
= - a -bIb + bIb b RC
RC + RF
(RC + re
or Vo = -bIb a 1 - bR
RC + RF C
Then
(RC + re)
-bIb a 1 - b RC
Vo RC + RF
Av = =
Vi bre Ib
(RC + re) RC
= - a1 - b
RC + RF re
For RC W re
RC RC
Av = - a 1 - b
RC + RF re
 (RC + RF - RC) RC COLLECTOR FEEDBACK 281
or Av = - CONFIGURATION
RC + RF re

RF RC
and Av = - a b (5.52)
RC + RF re

For RF W RC

RC
Av ⬵ - (5.53)
re

Phase Relationship The negative sign of Eq. (5.52) indicates a 180° phase shift between
Vo and Vi.

Effect of ro
Zi A complete analysis without applying approximations results in

RC 7 ro
1 +
RF
Zi = (5.54)
1 1 RC 储 ro RC 储 ro
+ + +
bre RF bre RF RFre

Applying the condition ro Ú 10RC, we obtain

RC RC
1 + re c 1 + d
RF RF
Zi = =
1 1 RC RC 1 1 RC
+ + + + cr + + RC d
bre RF bre RF RFre b RF e b
RC
Applying RC W re and ,
b
RC RF + RC
re c 1 + d re c d
RF RF re
Zi ⬵ = =
1 RC RF + bRC 1 RF RC
+ a b +
b RF bRF b RF + RC RC + RF
RF
but, since RF typically W RC, RF + RC ⬵ RF and = 1
RF + RC
re
Zi ⬵ (5.55)
1 RC
+
b RC + RF ro W RC, RF 7 RC

as obtained earlier.

Zo Including ro in parallel with RC in Fig. 5.47 results in

Zo = ro 7 RC 7 RF (5.56)

For ro Ú 10RC,

Zo ⬵ RC 7 RF ro Ú 10RC
(5.57)

as obtained earlier. For the common condition of RF W RC,

Zo ⬵ RC ro Ú 10RC,RF W RC
(5.58)
282 BJT AC ANALYSIS Av

RF RC 储 ro
Av = - a b (5.59)
RC 储 ro + RF re

For ro Ú 10RC,

RF RC
Av ⬵ - a b (5.60)
RC + RF re
ro Ú 10RC

and for RF W RC

RC
Av ⬵ - (5.61)
re
ro Ú 10RC, RF Ú RC

as obtained earlier.

EXAMPLE 5.9 For the network of Fig. 5.48. determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) with ro = 20 k and compare results.

9V

2.7 kΩ

180 kΩ Io
Vo
Ii 10 μF
Vi β = 200, ro = ∞ Ω
10 μF
Zo
Zi

FIG. 5.48
Example 5.9.

Solution:
VCC - VBE 9 V - 0.7 V
a. IB = =
RF + bRC 180 k + (200)2.7 k
= 11.53 mA
IE = (b + 1)IB = (201)(11.53 mA) = 2.32 mA
26 mV 26 mV
re = = = 11.21 ⍀
IE 2.32 mA
re 11.21  11.21 
b. Zi = = =
1 RC 1 2.7 k 0.005 + 0.0148
+ +
b RC + RF 200 182.7 k
11.21 
= = 566.16 ⍀
0.0198
c. Zo = RC 7 RF = 2.7 k 7 180 k = 2.66 k⍀
RC 2.7 k
d. Av = - = - = ⴚ240.86
re 11.21 
e. Zi: The condition ro Ú 10RC is not satisfied. Therefore, COLLECTOR FEEDBACK 283
CONFIGURATION
RC 7 ro 2.7 k 7 20 k
1 + 1 +
RF 180 k
Zi = =
1 1 RC 兩兩ro RC 兩兩 ro 1 1 2.7 k 兩兩 20 k 2.7 k 兩兩 20 k
+ + + + + +
bre RF breRF RFre (200)(11.21) 180 k (200)(11.21 )(180 k) (180 k)(11.21 )
2.38 k
1 +
180 k 1 + 0.013
= =
-3 -3
0.45 * 10 + 0.006 * 10 + 5.91 * 10 + 1.18 * 10 -6 -3
1.64 * 10-3
= 617.7 ⍀ vs. 566.16  above
Zo:
Zo = ro 7 RC 7 RF = 20 k 7 2.7 k 7 180 k
= 2.35 k⍀ vs. 2.66 k above
Av:
RF RC 储 ro 180 k 2.38 k
= -a b = -c d
RC 储 ro + RF re 2.38 k + 180 k 11.21
= - 3 0.987 4 212.3
= ⴚ209.54

For the configuration of Fig. 5.49, Eqs. (5.61) through (5.63) determine the variables of
interest. The derivations are left as an exercise at the end of the chapter.

VCC

RC
RF Io
Vo
Ii C2
Vi
C1
Zo
Zi
RE

FIG. 5.49
Collector feedback configuration with an emitter resistor RE.

Zi

RE
Zi ⬵ (5.62)
1 (RE + RC)
c + d
b RF

Zo

Zo = RC 7 RF (5.63)

Av

RC
Av ⬵ - (5.64)
RE
284 BJT AC ANALYSIS 5.11 COLLECTOR DC FEEDBACK CONFIGURATION
●
The network of Fig. 5.50 has a dc feedback resistor for increased stability, yet the capacitor
C3 will shift portions of the feedback resistance to the input and output sections of the net-
work in the ac domain. The portion of RF shifted to the input or output side will be deter-
mined by the desired ac input and output resistance levels.

VCC

RC
RF RF Io
1 2
Vo
C2
C3
C1
Vi
Zo
Ii

Zi

FIG. 5.50
Collector dc feedback configuration.

At the frequency or frequencies of operation, the capacitor will assume a short-circuit

equivalent to ground due to its low impedance level compared to the other elements of the
network. The small-signal ac equivalent circuit will then appear as shown in Fig. 5.51.

Ii
Ib
+ Io +
Zi RF β re β Ib ro RF RC
Vi 1 2 Vo

Zo
– –

R'

FIG. 5.51
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.50.

Zi

Zi = RF1 7 bre (5.65)

Zo

Zo = RC 7 RF2 7 ro (5.66)

For ro Ú 10RC,

Zo ⬵ RC 7 RF2 (5.67)
ro Ú 10RC

Av
R = ro 7 RF2 7 RC
and Vo = -bIbR
Vi
but Ib =
bre
 Vi COLLECTOR 285
and Vo = -b R DC FEEDBACK
bre
CONFIGURATION
so that

Vo ro 7 RF2 7 RC
Av = = - (5.68)
Vi re

For ro Ú 10RC,

Vo RF2 7 RC
Av = ⬵ - (5.69)
Vi re
ro Ú 10RC

Phase Relationship The negative sign in Eq. (5.68) clearly reveals a 180° phase shift
between input and output voltages.

EXAMPLE 5.10 For the network of Fig. 5.52, determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Vo if Vi  2 mV

12 V

3 kΩ

120 kΩ 68 kΩ Io
Vo
10 μF
0.01 μF
Ii Zo
Vi β = 140, ro = 30 k Ω
10 μF

Zi

FIG. 5.52
Example 5.10.

Solution:
VCC - VBE
a. DC: IB =
RF + bRC
12 V - 0.7 V
=
(120 k + 68 k) + (140)3 k
11.3 V
= = 18.6 mA
608 k
IE = (b + 1)IB = (141)(18.6 mA)
= 2.62 mA
26 mV 26 mV
re = = = 9.92 ⍀
IE 2.62 mA
b. bre = (140)(9.92 ) = 1.39 k
The ac equivalent network appears in Fig. 5.53.
Zi = RF1 7 bre = 120 k 7 1.39 k
⬵ 1.37 k⍀
286 BJT AC ANALYSIS Ib
+ Ii Io +
β re β Ib ro
120 kΩ 68 kΩ 3 kΩ
Vi 1.395 kΩ 140 Ib 30 kΩ Vo

Zi
Zo
– –

FIG. 5.53
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.52.

c. Testing the condition ro Ú 10RC, we find

30 k Ú 10(3 k) = 30 k
which is satisfied through the equals sign in the condition. Therefore,
Zo ⬵ RC 7 RF2 = 3 k 7 68 k
= 2.87 k⍀
d. ro Ú 10RC; therefore,
RF2 7 RC 68 k 7 3 k
Av ⬵ - = -
re 9.92 
2.87 k
⬵ -
9.92 
⬵ ⴚ289.3
Vo
e. 兩 Av 兩 = 289.3 =
Vi
Vo = 289.3Vi = 289.3(2 mV) = 0.579 V

5.12 EFFECT OF RL AND RS

●
All the parameters determined in the last few sections have been for an unloaded amplifier
with the input voltage connected directly to a terminal of the transistor. In this section the
effect of applying a load to the output terminal and the effect of using a source with an
internal resistance will be investigated. The network of Fig. 5.54a is typical of those inves-
tigated in the previous section. Because a resistive load was not attached to the output ter-
minal, the gain is commonly referred to as the no-load gain and given the following
notation:

Vo
AvNL = (5.70)
Vi

In Fig. 5.54b a load has been added in the form of a resistor RL, which will change the
overall gain of the system. This loaded gain is typically given the following notation:

Vo
AvL = (5.71)
Vi
with RL

In Fig. 5.54c both a load and a source resistance have been introduced, which will have
an additional effect on the gain of the system. The resulting gain is typically given the fol-
lowing notation:

Vo
Avs = (5.72)
Vs
with RL and Rs

The analysis to follow will show that:

The loaded voltage gain of an amplifier is always less than the no-load gain.
 VCC VCC VCC

RC RC RC
RB RB RB

+ + +

+ + Rs
Vo
RL
Vo + RL
Vo
Vi Vi Vs
–
– – – – –

Vo Vo Vo
Av = Av = Av =
NL Vi L Vi s Vs

(a) (b) (c)

FIG. 5.54
Amplifier configurations: (a) unloaded; (b) loaded; (c) loaded with a source resistance.

In other words, the addition of a load resistor RL to the configuration of Fig. 5.54a will
always have the effect of reducing the gain below the no-load level.
Furthermore:
The gain obtained with a source resistance in place will always be less than that
obtained under loaded or unloaded conditions due to the drop in applied voltage across
the source resistance.
In total, therefore, the highest gain is obtained under no-load conditions and the lowest
gain with a source impedance and load in place. That is:
For the same configuration AvNL + AvL + Avs.
It will also be interesting to verify that:
For a particular design, the larger the level of RL, the greater is the level of ac gain.
In other words, the larger the load resistance, the closer it is to an open-circuit approxi-
mation that would result in the higher no-load gain.
In addition:
For a particular amplifier, the smaller the internal resistance of the signal source, the
greater is the overall gain.
In other words, the closer the source resistance is to a short-circuit approximation, the
greater is the gain because the effect of Rs will essentially be eliminated.
For any network, such as those shown in Fig. 5.54 that have coupling capacitors, the
source and load resistance do not affect the dc biasing levels.
The conclusions listed above are all quite important in the amplifier design process.
When one purchases a packaged amplifier, the listed gain and all the other parameters are
for the unloaded situation. The gain that results due to the application of a load or source
resistance can have a dramatic effect on all the amplifier parameters, as will be demon-
strated in the examples to follow.
In general, there are two directions one can take to analyze networks with an applied
load and/or source resistance. One approach is to simply insert the equivalent circuit, as
was demonstrated in Section 5.11, and use methods of analysis to determine the quantities
of interest. The second is to define a two-port equivalent model and use the parameters
determined for the no-load situation. The analysis to follow in this section will use the first
approach, leaving the second method for Section 5.14.
For the fixed-bias transistor amplifier of Fig. 5.54c, substituting the re equivalent circuit
for the transistor and removing the dc parameters results in the configuration of Fig. 5.55.
287
288 BJT AC ANALYSIS Ib
+ Rs + +
Zo
Vs Vi RB β re β Ib ro RC RL Vo
Zi
–
– –
–
RL = ro RC RL ≅ RC RL

FIG. 5.55
The ac equivalent network for the network of Fig. 5.54c.

It is particularly interesting that Fig. 5.55 is exactly the same in appearance as Fig. 5.22
except that now there is a load resistance in parallel with RC and a source resistance has
been introduced in series with a source Vs.
The parallel combination of
RL = ro 7 RC 7 RL ⬵ RC 7 RL
and Vo = -bIbRL = -bIb(RC 7 RL)
Vi
with Ib =
bre
Vi
gives Vo = -ba b (RC 7 RL)
bre

Vo RC 7 RL
so that AvL = = - (5.73)
Vi re

The only difference in the gain equation using Vi as the input voltage is the fact that RC
of Eq. (5.10) has been replaced by the parallel combination of RC and RL. This makes good
sense because the output voltage of Fig. 5.55 is now across the parallel combination of the
two resistors.
The input impedance is

Zi = RB 7 bre (5.74)

as before, and the output impedance is

Zo = RC 7 ro (5.75)

as before.
If the overall gain from signal source Vs to output voltage Vo is desired, it is only neces-
sary to apply the voltage-divider rule as follows:
ZiVs
Vi =
Zi + Rs
Vi Zi
and =
Vs Zi + Rs

or AvS =
Vo
= # = AvL Zi
Vo Vi
Vs Vi Vs Zi + Rs

Zi
so that AvS = A (5.76)
Zi + Rs vL

Because the factor Zi >(Zi + Rs) must always be less than one, Eq. (5.76) clearly supports
the fact that the signal gain AvS is always less than the loaded gain AvL.
 EFFECT OF R L AND R S 289
EXAMPLE 5.11 Using the parameter values for the fixed-bias configuration of Example 5.1
with an applied load of 4.7 k and a source resistance of 0.3 k, determine the following
and compare to the no-load values:
a. AvL.
b. Avs.
c. Zi.
d. Zo.

Solution:
RC 7 RL 3 k 7 4.7 k 1.831 k
a. Eq. (5.73): AvL = - = - = - = ⴚ170.98
re 10.71  10.71 
which is significantly less than the no-load gain of -280.11.
Zi
b. Eq. (5.76): Avs = A
Zi + Rs vL
With Zi = 1.07 k from Example 5.1, we have
1.07 k
Avs = (-170.98) = ⴚ133.54
1.07 k + 0.3 k
which again is significantly less than AvNL or AvL.
c. Zi = 1.07 k⍀ as obtained for the no-load situation.
d. Zo = RC = 3 k⍀ as obtained for the no-load situation.
The example clearly demonstrates that AvNL 7 AvL 7 Avs.

For the voltage-divider configuration of Fig. 5.56 with an applied load and series source
resistor the ac equivalent network is as shown in Fig. 5.57.

VCC

RC
C2
R1

Ib
+
Rs

C1
+
+ RL Vo
R2 Zo
Vs Vi
– Zi RE CE
– –

FIG. 5.56
Voltage-divider bias configuration with Rs and RL.

Ii
Rs Io
b Ib c
+ + +
Zi
Vs Vi R1 R2 β re β Ib ro RC RL Vo

– – e e Zo –

R'

FIG. 5.57
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.56.
290 BJT AC ANALYSIS First note the strong similarities with Fig. 5.55, with the only difference being the par-
allel connection of R1 and R2 instead of just RB. Everything else is exactly the same. The
following equations result for the important parameters of the configuration:

Vo RC 7 RL
AvL = = - (5.77)
Vi re

Zi = R1 7 R2 7 bre (5.78)

Zo = RC 7 ro (5.79)

For the emitter-follower configuration of Fig. 5.58 the small-signal ac equivalent net-
work is as shown in Fig. 5.59. The only difference between Fig. 5.59 and the unloaded
configuration of Fig. 5.37 is the parallel combination of RE and RL and the addition of the
source resistor Rs. The equations for the quantities of interest can therefore be determined
by simply replacing RE by RE 7 RL wherever RE appears. If RE does not appear in an equation,
the load resistor RL does not affect that parameter. That is,

Vo RE 7 RL
AvL = = (5.80)
Vi RE 7 RL + re

VCC

RB C

Ii
B

Rs C1
+ C2 Io
+ Vo
Vs Vi
Zi
– RE RL
Zo
–

FIG. 5.58
Emitter-follower configuration with Rs and RL.

Ii
b c
Ib
Rs +
β re βIb
Zi

+
Vs Vi RB
Io
– e +
Zo
RE RL Vo
–
–

FIG. 5.59
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.58.
 DETERMINING THE 291
Zi = RB 7 Zb (5.81) CURRENT GAIN

Zb ⬵ b(RE 7 RL) (5.82)

Zo ⬵ r e (5.83)

The effect of a load resistor and a source impedance on the remaining BJT configura-
tions will not be examined in detail here, although Table 5.1 in Section 5.14 will review
the results for each configuration.

5.13 DETERMINING THE CURRENT GAIN

●
You may have noticed in the previous sections that the current gain was not determined for
each configuration. Earlier editions of this text did have the details of finding that gain, but
in reality the voltage gain is usually the gain of most importance. The absence of the deri-
vations should not cause concern because:
For each transistor configuration, the current gain can be determined directly from the
voltage gain, the defined load, and the input impedance.
The derivation of the equation linking the voltage and current gains can be derived using
the two-port configuration of Fig. 5.60.

Ii Io

+ +
Zi Zo
Vi System Vo RL

– –

FIG. 5.60
Determining the current gain using the voltage gain.

The current gain is defined by

Io
Ai = (5.84)
Ii
Applying Ohm’s law to the input and output circuits results in
Vi Vo
Ii = and Io = -
Zi RL
The minus sign associated with the output equation is simply there to indicate that the polar-
ity of the output voltage is determined by an output current having the opposite direction. By
definition, the input and output currents have a direction entering the two-port configuration.
Substituting into Eq. (5.84) then results in
Vo
-
= - #
Io RL Vo Zi
AiL = =
Ii Vi Vi RL
Zi
and the following important equation:

Zi
AiL = -AvL (5.85)
RL

The value of RL is defined by the location of Vo and Io.

292 BJT AC ANALYSIS To demonstrate the validity of Eq. (5.82), consider the voltage-divider bias configura-
tion of Fig. 5.28.
Using the results of Example 5.2, we find
Vi Vi Vo Vo
Ii = = and Io = - = -
Zi 1.35 k⍀ RL 6.8 k⍀

Vo
a- b
Io 6.8 k⍀ Vo 1.35 k⍀
so that AiL = = = -a ba b
Ii Vi Vi 6.8 k⍀
1.35 k⍀
1.35 k⍀
= -(-368.76)a b = 73.2
6.8 k⍀
Zi 1.35 k⍀
Using Eq. 5.82: AiL = -AvL = -(-368.76)a b = 73.2
RL 6.8 k⍀
which has the same format as the resulting equation above and the same result.
The solution to the current gain in terms of the network parameters will be more com-
plicated for some configurations if a solution is desired in terms of the network parameters.
However, if a numerical solution is all that is desired, it is simply a matter of substituting
the value of the three parameters from an analysis of the voltage gain.
As a second example, consider the common-base bias configuration of Section 5.9. In
this case the voltage gain is
RC
AvL ⬵
re
and the input impedance is
Zi ⬵ RE 7 re ⬵ re
with RL defined as RC due to the location of Io.
The result is the following:
Zi RC re
AiL = -AvL = a - b a b ⬵ -1
RL r e RC
which agrees with the solution of that section because Ic ⬵ Ie. Note, in this case, that the
output current has the opposite direction to that appearing in the networks of that section
due to the minus sign.

5.14 SUMMARY TABLES

●
The last few sections have included a number of derivations for unloaded and loaded BJT
configurations. The material is so extensive that it seemed appropriate to review most of
the conclusions for the various configurations in summary tables for quick comparisons.
Although the equations using the hybrid parameters have not been discussed in detail at
this point, they are included to make the tables complete. The use of hybrid parameters
will be considered in a later section of this chapter. In each case the waveforms included
demonstrate the phase relationship between input and output voltages. They also reveal the
relative magnitude of the voltages at the input and output terminals.
Table 5.1 is for the unloaded situation, whereas Table 5.2 includes the effect of Rs and RL.

5.15 TWO-PORT SYSTEMS APPROACH

●
In the design process, it is often necessary to work with the terminal characteristics of a
device rather then the individual components of the system. In other words, the designer is
handed a packaged product with a list of data regarding its characteristics but has no access
to the internal construction. This section will relate the important parameters determined
for a number of configurations in the previous sections to the important parameters of this
packaged system. The result will be an understanding of how each parameter of the
 TABLE 5.1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k) Medium (2 k) High (- 200) High (100)
VCC
Io = RB 7 bre = RC 7 r o (RC 7 ro) bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ ⬵ bre ⬵ RC
Vo RC ⬵ b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) ⬵ -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k) Medium (2 k) High (- 200) High (50)

bias: VCC
Io RC = R1 7 R2 7 bre = RC 7 r o RC 7 r o b(R1 7 R2)ro
R1 = - =
Ii
re (ro + RC)(R1 7 R2 + bre)
+ ⬵ RC
+ Zo RC b(R1 7 R2)
Vo (ro Ú 10RC) ⬵ - ⬵
Vi Zi R2 re R1 7 R2 + bre
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k) Medium (2 k) Low (- 5) High (50)

emitter bias: VCC
= RB 7 Zb = RC RC bRB
Io RC = - ⬵ -
RB r e + RE RB + Zb
Ii Zb ⬵ b(re + RE) (any level of ro)
+
+ Zo ⬵ RB 7 bRE ⬵ -
RC
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k) Low (20 ) Low ( ⬵1) High (- 50)
follower: VCC
= RB 7 Zb = RE 7 r e RE bRB
Ii RB = ⬵ -
RE + r e RB + Zb
Zb ⬵ b(re + RE)
+ ⬵ re
⬵ RB 7 bRE ⬵ 1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k) High (200) Low (- 1)
Ii
= RE 7 r e = RC RC ⬵ -1
⬵
+ Io RC + re
Vi Zi
RE
Vo ⬵ re
Zo
VEE VCC
– – (RE W re)

Collector Medium (1 k) Medium (2 k) High (- 200) High (50)

feedback: VCC
Io
RC re ⬵ RC 7 RF RC bRF
RF = ⬵ - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) ⬵
(RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

- (RL 储 RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre RC 7 r o
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre RC 7 r o
re

RE = RL 7 RE Rs = Rs 7 R1 7 R2
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

Including ro:
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

- (RL 7 RC) RE 7 r e RC
⬵
re

Including ro:

- (RL 7 RC 7 ro)
⬵ RE 7 r e RC 7 r o
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:
Zo
- (RL 7 RC)
+ RL R1 7 R2 7 b(re + Re) ⬵ RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

VCC

- (RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:
+ RE1 RL
Zi - (RL 7 RC)
Vs RB 7 b(re + RE) ⬵ RC
– REt
RE2 CE

VCC

- (RL 7 RC) RF
RC bre 储 RC
re 兩 Av 兩
RF
Vo

Rs Vi
Zo
Including ro:
+ RL
- (RL 7 RC 7 ro) RF
Vs bre 储 RC 7 RF 7 r o
– Zi re 0 Av 0

VCC

- (RL 7 RC) RF
RC bRE 储 ⬵ RC 7 RF
RE 0 Av 0
RF
Vo

Rs Vi
Zo Including ro:

+ RL - (RL 7 RC) RF
⬵ ⬵ bRE 储 ⬵ RC 7 RF
Vs
Zi RE
L
RE 0 Av 0
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295
296 BJT AC ANALYSIS For the two-port system of Fig. 5.61 the polarity of the voltages and the direction of
the currents are as defined. If the currents have a different direction or the voltages have
a different polarity from that appearing in Fig. 5.61, a negative sign must be applied.
Note again the use of the label AvNL to indicate that the provided voltage gain will be the
no-load value.
For amplifiers the parameters of importance have been sketched within the boundaries
of the two-port system as shown in Fig. 5.62. The input and output resistance of a packaged
amplifier are normally provided along with the no-load gain. They can then be inserted as
shown in Fig. 5.62 to represent the seated package.

AvNLVi

FIG. 5.62
Substituting the internal elements for the two-port system of Fig. 5.61.

For the no-load situation the output voltage is

Vo = AvNLVi (5.86)

due to the fact that I  0A, resulting in Io Ro = 0V.

The output resistance is defined by Vi  0V. Under such conditions the quantity AvNLVi
is zero volts also and can be replaced by a short-circuit equivalent. The result is

Zo = Ro (5.87)

Finally, the input impedance Zi simply relates the applied voltage to the resulting input
current and

Zi = Ri (5.88)

For the no-load situation, the current gain is undefined because the load current is zero.
There is, however, a no-load voltage gain equal to AvNL.
The effect of applying a load to a two-port system will result in the configuration of
Fig. 5.63. Ideally, all the parameters of the model are unaffected by changing loads and
levels of source resistance. However, for some transistor configurations the applied load
can affect the input resistance, whereas for others the output resistance can be affected by
the source resistance. In all cases, however, by simple definition, the no-load gain is unaf-
fected by the application of any load. In any case, once AvNL, Ri, and Ro are defined for a
particular configuration, the equations about to be derived can be employed.

Av NLVi

FIG. 5.63
Applying a load to the two-port system of Fig. 5.62.
 Applying the voltage-divider rule to the output circuit results in TWO-PORT SYSTEMS 297
RLAvNLVi APPROACH
Vo =
RL + Ro

Vo RL
and AvL = = A (5.89)
Vi RL + Ro vNL

Because the ratio RL >(RL + Ro) is always less than 1, we have further evidence that the
loaded voltage gain of an amplifier is always less than the no-load level.
The current gain is then determined by
Io -Vo >RL Vo Zi
AiL = = = -
Ii Vi >Zi Vi RL

Zi
and AiL = -AvL (5.90)
RL

as obtained earlier. In general, therefore, the current gain can be obtained from the voltage
gain and impedance parameters Zi and RL. The next example will demonstrate the useful-
ness and validity of Eqs. (5.89) and (5.90).
Our attention will now turn to the input side of the two-port system and the effect of an
internal source resistance on the gain of an amplifier. In Fig. 5.64, a source with an internal
resistance has been applied to the basic two-port system. The definitions of Zi and AvNL are
such that:
The parameters Zi and AvNL of a two-port system are unaffected by the internal resis-
tance of the applied source.

Is Ii Io

+ + +
Vs Vi A␷NLVi Vo
Zo
– Zi
– –

FIG. 5.64
Including the effects of the source resistance Rs.

However:
The output impedance may be affected by the magnitude of Rs.
The fraction of the applied signal reaching the input terminals of the amplifier of Fig. 5.64
is determined by the voltage-divider rule. That is,

RiVs
Vi = (5.91)
Ri + Rs

Equation (5.91) clearly shows that the larger the magnitude of Rs, the lower is the voltage
at the input terminals of the amplifier. In general, therefore, as mentioned earlier, for a
particular amplifier, the larger the internal resistance of a signal source, the lower is the
overall gain of the system.
For the two-port system of Fig. 5.64,
Vo = AvNLVi
RiVs
and Vi =
Ri + Rs
298 BJT AC ANALYSIS Ri
so that Vo = AvNL V
Ri + Rs s

Vo Ri
and Avs = = Av (5.92)
Vs Ri + Rs NL

The effects of Rs and RL have now been demonstrated on an individual basis. The next
natural question is how the presence of both factors in the same network will affect the
total gain. In Fig. 5.65, a source with an internal resistance Rs and a load RL have been
applied to a two-port system for which the parameters Zi, AvNL, and Zo have been specified.
For the moment, let us assume that Zi and Zo are unaffected by RL and Rs, respectively.

Is Ii Io

+
+ Zo
Vs RL Vo
–
–

FIG. 5.65
Considering the effects of Rs and RL on the gain of an amplifier.

At the input side we find

RiVs
Eq. (5.91): Vi =
Ri + Rs

Vi Ri
or = (5.93)
Vs Ri + Rs

and at the output side,

RL
Vo = A V
RL + Ro vNL i
Vo RLAvNL RL
or AvL = = = A (5.94)
Vi RL + Ro RL + Ro vNL
For the total gain Avs = Vo >Vs, the following mathematical steps can be performed:

Avs =
Vo
= #
Vo Vi
(5.95)
Vs Vi Vs

and substituting Eqs. (5.93) and (5.94) results in

Avs =
Vo
=
Ri
# RL AvNL (5.96)
Vs Ri + Rs RL + Ro

Because Ii = Vi >Ri, as before,

Ri
AiL = -AvL (5.97)
RL

or, using Is = Vs >(Rs + Ri),

Rs + Ri
Ais = -Avs (5.98)
RL
However, Ii = Is, so Eqs. (5.97) and (5.98) generate the same result. Equation (5.96) TWO-PORT SYSTEMS 299
clearly reveals that both the source and the load resistance will reduce the overall gain of APPROACH
the system.
The two reduction factors of Eq. (5.96) form a product that has to be carefully consid-
ered in any design procedure. It is not sufficient to ensure that Rs is relatively small if the
effect of the magnitude of RL is ignored. For instance, in Eq. (5.96), if the first factor is 0.9
and the second factor is 0.2, the product of the two results in an overall reduction factor
equal to (0.9)(0.2)  0.18, which is close to the lower factor. The effect of the excellent
0.9 level was completely wiped out by the significantly lower second multiplier. If both
were 0.9-level factors, the net result would be (0.9)(0.9)  0.81, which is still quite high.
Even if the first were 0.9 and the second 0.7, the net result of 0.63 would still be respect-
able. In general, therefore, for good overall gain the effects of Rs and RL must be evaluated
individually and as a product.

EXAMPLE 5.12 Determine AvL and Avs for the network of Example 5.11 and compare
solutions. Example 5.1 showed that AvNL = -280, Zi = 1.07 k, and Zo = 3 k. In
Example 5.11, RL = 4.7 k and Rs = 0.3 k.
Solution:
RL
a. Eq. (5.89): AvL = A
RL + Ro vNL
4.7 k
= (-280.11)
4.7 k + 3 k
= ⴚ170.98
as in Example 5.11.
b. Eq. (5.96): Avs =
Ri
# RL AvNL
Ri + Rs RL + Ro

=
1.07 k # 4.7 k (-280.11)
1.07 k + 0.3 k 4.7 k + 3 k
= (0.781)(0.610)(-280.11)
= ⴚ133.45
as in Example 5.11.

EXAMPLE 5.13 Given the packaged (no-entry-possible) amplifier of Fig. 5.66:

a. Determine the gain AvL and compare it to the no-load value with RL = 1.2 k.
b. Repeat part (a) with RL = 5.6 k and compare solutions.
c. Determine Avs with RL = 1.2 k.
Io Io
d. Find the current gain Ai = = with RL = 5.6 k.
Ii Is

Is Rs Ii Io

0.2 kΩ + +
+ Av
NL
= – 480
Vs Vi Zi = 4 kΩ RL Vo
– Zo = 2 kΩ
– –

FIG. 5.66
Amplifier for Example 5.13.
300 BJT AC ANALYSIS Solution:
RL
a. Eq. (5.89): AvL = Av
RL + Ro NL
1.2 k⍀
= (-480) = (0.375)(-480)
1.2 k⍀ + 2 k⍀
= ⴚ180
which is a dramatic drop from the no-load value.
RL
b. Eq. (5.89): AvL = A
RL + Ro vNL
5.6 k⍀
= (-480) = (0.737)(-480)
5.6 k⍀ + 2 k⍀
= ⴚ353.76
which clearly reveals that the larger the load resistor, the better is the gain.
c. Eq. (5.96): Avs =
Ri
# RL AvNL
Ri + Rs RL + Ro

=
4 k⍀ # 1.2 k⍀ (-480)
4 k⍀ + 0.2 k⍀ 1.2 k⍀ + 2 k⍀
= (0.952)(0.375)(-480)
= ⴚ171.36
which is fairly close to the loaded gain Av because the input impedance is considerably
more than the source resistance. In other words, the source resistance is relatively
small compared to the input impedance of the amplifier.
Io Io Zi
d. AiL = = = -AvL
Ii Is RL
4 k⍀
= -(-353.76)a b = -(-353.76)(0.714)
5.6 k⍀
= 252.6

It is important to realize that when using the two-port equations in some configurations
the input impedance is sensitive to the applied load (such as the emitter-follower and collec-
tor feedback) and in some the output impedance is sensitive to the applied source resistance
(such as the emitter-follower). In such cases the no-load parameters for Zi and Zo have to
first be calculated before substituting into the two-port equations. For most packaged sys-
tems such as op-amps this sensitivity of the input and output parameters to the applied load
or source resistance is minimized to eliminate the need to be concerned about changes from
the no-load levels when using the two-port equations.

5.16 CASCADED SYSTEMS

●
The two-port systems approach is particularly useful for cascaded systems such as that
appearing in Fig. 5.67, where Av1, Av2, Av3, and so on, are the voltage gains of each stage
under loaded conditions. That is, Av1 is determined with the input impedance to Av2 acting
as the load on Av1. For Av2, Av1 will determine the signal strength and source impedance at
the input to Av2. The total gain of the system is then determined by the product of the indi-
vidual gains as follows:

AvT = Av1 # Av2 # Av3 . . . . (5.99)

and the total current gain is given by

Zi 1
AiT = -AvT (5.100)
RL
 No matter how perfect the system design, the application of a succeeding stage or load CASCADED SYSTEMS 301
to a two-port system will affect the voltage gain. Therefore, there is no possibility of a
situation where Av1, Av2, and so on, of Fig. 5.67 are simply the no-load values. The no-load
parameters can be used to determine the loaded gains of each stage, but Eq. (5.99) requires
the loaded values. The load on stage 1 is Zi2, on stage 2 Zi3, on stage 3 Zin, and so on.

Vo = Vi Vo = Vi
1 2 2 3

+ +
Vi Av 1 Av 2 Av 3 Av n RL Vo

– –
Zi = Zi Zo Zi Zo Zi Zo Z in Zon = Zo
1 1 2 2 3 3

FIG. 5.67
Cascaded system.

EXAMPLE 5.14 The two-stage system of Fig. 5.68 employs a transistor emitter-follower
configuration prior to a common-base configuration to ensure that the maximum percentage
of the applied signal appears at the input terminals of the common-base amplifier. In Fig.
5.68, the no-load values are provided for each system, with the exception of Zi and Zo for the
emitter-follower, which are the loaded values. For the configuration of Fig. 5.68, determine:
a. The loaded gain for each stage.
b. The total gain for the system, Av and Avs.
c. The total current gain for the system.
d. The total gain for the system if the emitter-follower configuration were removed.

+
RL Vo
–

FIG. 5.68
Example 5.14.

Solution:
a. For the emitter-follower configuration, the loaded gain is (by Eq. (5.94))
Zi 2 26 
Vo1 = A V = (1) Vi1 = 0.684 Vi1
Zi2 + Zo1 vNL i1 26  + 12 
Vo1
and AVi = = 0.684
Vi1
For the common-base configuration,
RL 8.2 k
Vo2 = AvNL Vi2 = (240) Vi2 = 147.97 Vi2
RL + Ro2 8.2 k + 5.1 k
Vo2
and Av2 = = 147.97
Vi2
b. Eq. (5.99): AvT = Av1Av2
= (0.684)(147.97)
= 101.20
302 BJT AC ANALYSIS Zi 1 (10 k⍀)(101.20)
Eq. (5.91): Avs = AvT =
Zi1 + Rs 10 k⍀ + 1 k⍀
= 92
Zi 1 10 k⍀
c. Eq. (5.100): AiT = -AvT = -(101.20) a b
RL 8.2 k⍀
= ⴚ123.41
ZiCB 26 ⍀
d. Eq. (5.91): Vi = Vs = V = 0.025 Vs
ZiCB + Rs 26 ⍀ + 1 k⍀ s
Vi Vo
and = 0.025 with = 147.97 from above
Vs Vi

and Avs =
Vo
= # = (0.025)(147.97) = 3.7
Vi Vo
Vs Vs Vi
In total, therefore, the gain is about 25 times greater with the emitter-follower configuration
to draw the signal to the amplifier stages. Note, however, that it is also important that the
output impedance of the first stage is relatively close to the input impedance of the second
stage, otherwise the signal would have been “lost” again by the voltage-divider action.

RC-Coupled BJT Amplifiers

One popular connection of amplifier stages is the RC-coupled variety shown in Fig. 5.69 in
the next example. The name is derived from the capacitive coupling capacitor Cc and the
fact that the load on the first stage is an RC combination. The coupling capacitor isolates
the two stages from a dc viewpoint but acts as a short-circuit equivalent for the ac response.
The input impedance of the second stage acts as a load on the first stage, permitting the
same approach to the analysis as described in the last two sections.

EXAMPLE 5.15
a. Calculate the no-load voltage gain and output voltage of the RC-coupled transistor
amplifiers of Fig. 5.69.
b. Calculate the overall gain and output voltage if a 4.7 k⍀ load is applied to the second
stage, and compare to the results of part (a).
c. Calculate the input impedance of the first stage and the output impedance of the second
stage.
+20 V

2.2 kΩ 15 kΩ 2.2 kΩ
15 kΩ CC
Vo
10 μF 10 μF
Vi = 25 μV
Q1 β = 200 Q2 β = 200
10 μF

4.7 kΩ + 4.7 kΩ +
1 kΩ 20 μ F 1 kΩ 20 μ F

FIG. 5.69
RC-coupled BJT amplifier for Example 5.15.

Solution:
a. The dc bias analysis results in the following for each transistor:
VB = 4.8 V, VE = 4.1 V, VC = 11 V, IE = 4.1 mA
 At the bias point, CASCADED SYSTEMS 303
26 mV 26 mV
re = = = 6.34 ⍀
IE 4.1 mA
The loading of the second stage is
Zi2 = R1 7 R2 7 bre
which results in the following gain for the first stage:
RC 7 (R1 7 R2 7 bre)
Av1 = -
re
(2.2 k⍀) 7 [15 k⍀ 7 4.7 k⍀ 7 (200)(6.34 ⍀)]
= -
6.34 ⍀
659.2 ⍀
= - = -104
6.34 ⍀
For the unloaded second stage the gain is
RC 2.2 k⍀
Av2(NL) = - = - = -347
re 6.34 ⍀
resulting in an overall gain of
AvT(NL) = Av1Av2(NL) = (-104)(-347) ⬵ 36.1 : 103
The output voltage is then
Vo = AvT(NL)Vi = (36.1 * 103)(25 mV) ⬵ 902.5 mV
b. The overall gain with the 10-k⍀ load applied is
Vo RL 4.7 k⍀
AvT = = AvT(NL) = (36.1 * 103) ⬵ 24.6 : 103
Vi RL + Zo 4.7 k⍀ + 2.2 k⍀
which is considerably less than the unloaded gain because RL is relatively close to RC.
Vo = AvTVi
= (24.6 * 103)(25 mV)
= 615 mV
c. The input impedance of the first stage is
Zi1 = R1 7 R2 7 bre = 4.7 k⍀ 7 15 k⍀ 7 (200)(6.34 ⍀) = 0.94 k⍀
whereas the output impedance for the second stage is
Zo2 = RC = 2.2 k⍀

Cascode Connection
The cascode configuration has one of two configurations. In each case the collector of the
leading transistor is connected to the emitter of the following transistor. One possible
arrangement appears in Fig. 5.70; the second is shown in Fig. 5.71 in the following example.

Vo

Vi

FIG. 5.70
Cascode configuration.
304 BJT AC ANALYSIS The arrangements provide a relatively high-input impedance with low voltage gain for the
first stage to ensure the input Miller capacitance (to be discussed in Section 9.9) is at a
minimum, whereas the following CB stage provides an excellent high-frequency response.

EXAMPLE 5.16 Calculate the no-load voltage gain for the cascode configuration of Fig. 5.71.

VCC = 18 V

RC
RB 1.8 kΩ
1
6.8 kΩ Vo 2
C1 C = 5 μF
Q2
10 μF
RB
2 Vo 1 (β1 = β2= 200)
5.6 kΩ

Vi 1 Q1
Cs = 5 μF

RB
3
4.7 kΩ RE
CE = 20 μF
1.1 kΩ

FIG. 5.71
Practical cascode circuit for Example 5.16.

Solution: The dc analysis results in

VB1 = 4.9 V, VB2 = 10.8 V, IC1 ⬵ IC2 = 3.8 mA
because IE1 ⬵ IE2 the dynamic resistance for each transistor is
26 mV 26 mV
re = ⬵ = 6.8 
IE 3.8 mA
The loading on the transistor Q1 is the input impedance of the Q2 transistor in the CB
configuration as shown by re in Fig 5.72.
The result is the replacement of RC in the basic no-load equation for the gain of the CB
configuration, with the input impedance of a CB configuration as follows:
RC re
Av1 = - = - = -1
re re
with the voltage gain for the second stage (common base) of
RC 1.8 k
Av2 = = = 265
re 6.8 

Vo2
Vo1 Q2
re

Vi1
Q1

FIG. 5.72
Defining the load of Q1.
The overall no-load gain is
AvT = Av1 Av2 = (-1)(265) = ⴚ265
As expected, in Example 5.16, the CE stage provides a higher input impedance than can
be expected from the CB stage. With a voltage gain of about 1 for the first stage, the
Miller-effect input capacitance is kept quite low to support a good high-frequency response.
A large voltage gain of 265 was provided by the CB stage to give the overall design a good
input impedance level with desirable gain levels.

5.17 DARLINGTON CONNECTION

●
A very popular connection of two bipolar junction transistors for operation as one “super-
beta” transistor is the Darlington connection shown in Fig. 5.73. The main feature of the
Darlington connection is that the composite transistor acts as a single unit with a current
gain that is the product of the current gains of the individual transistors. If the connection
is made using two separate transistors having current gains of b1 and b2, the Darlington American (Pittsburgh, PA; Exeter, NH)
(1906–1997)
connection provides a current gain of
Department Head at Bell Laboratories
bD = b1b2 (5.101) Professor, Department of Electrical and
Computer Engineering, University of
New Hampshire

Dr. Sidney Darlington earned his B.S. in

physics at Harvard, his B.S. in electrical
communication at MIT, and his Ph.D. at
Columbia University. In 1929 he joined
Bell Laboratories, where he was head of
the Circuits and Control Department. Dur-
ing that period he became good friends
with other important contributors such as
Edward Norton and Hendrik Bode. A
holder of 24 U.S. patents, he was awarded
the Presidential Medal of Freedom, the
FIG. 5.73 highest civilian honor in the United States,
in 1945 for his contributions to network
Darlington combination.
design during World War II. An elected
The configuration was first introduced by Dr. Sidney Darlington in 1953. A short biog- member of the National Academy of
Engineering, he also received the IEEE
raphy appears as Fig 5.74.
Edison Medal in 1975 and the IEEE
Medal of Honor in 1981. His U.S. patent
Emitter-Follower Configuration 2 663 806 titled “Semiconductor Signal
Translating Device” was issued on Decem-
A Darlington amplifier used in an emitter-follower configuration appears in Fig. 5.75. The ber 22, 1953, describing how two transis-
primary impact of using the Darlington configuration is an input impedance much larger than tors could be constructed in the Darlington
configuration on the same substrate—
often looked upon as the beginnings of
compound IC construction. Dr. Darlington
was also responsible for the introduction
and development of the Chirp technique,
used throughout the world in waveguide
transmission and radar systems. He is a
primary contributor to the Bell Laborato-
ries Command Guidance System that
guides most of the rockets used today to
Vi β1 place satellites in orbit. It uses a combina-
C1 IB1
+ tion of radar tracking on the ground with
VBE1– β2 inertial control in the rocket itself. Dr.
+ Darlington was an avid outdoorsman as a
VBE2 – Vo
hiker and member of the Appalachian
IE2 C2 Mountain Club. One of his proudest
accomplishments was being able to climb
Mt. Washington at the age of 80.

FIG. 5.74
Sidney Darlington (Courtesy of
AT&T Archives and History Center.)
FIG. 5.75
Emitter-follower configuration with a Darlington amplifier.
305