Valliammai Engineering College: Question Bank
Valliammai Engineering College: Question Bank
com
VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203
QUESTION BANK
EC 8392 DIGITAL ELECTRONICS
Regulation 2017
Prepared by
QUESTION BANK
PART A
Q.
Questions BT Level Domain
No
1. State De-Morgan’s theorem and mention its use. BTL 1 Remembering
2. Express the function Y A BC in canonical POS. BTL 3 Applying
3. Convert the given decimal numbers to their binary equivalent
BTL 2 Understanding
108.364, 268.025.
4. Why totem pole outputs cannot be connected together? BTL 1 Remembering
5. Simplify the following Boolean expression into one literal.
BTL 4 Analyzing
W’X(Z’+YZ) + X(W+Y’Z).
6. Convert (115)10 and (235)10 into hexadecimal numbers. BTL 2 Understanding
7. Define ‘Minterm’ and ‘ Maxterm’. BTL 1 Remembering
8. Draw an active high tri-state Gate & write its truth table. BTL 3 Applying
9. Show how to connect NAND gates to get an AND gate and
BTL 2 Understanding
OR gate?
10. State Distributive law and Duality principle. BTL 1 Remembering
11. What is meant by Prime Implicant and Essential prime
BTL 1 Remembering
implicants?
12. Find the minimized Boolean expression of this function
BTL 1 Remembering
F=XY+X(Y+Z) +Y(Y+Z).
13. Implement the given function using NAND gates only.
F(X, Y, Z) = m(0,6) .
BTL 6 Creating
BTL 5 Evaluating
19.
Interpret the truth table of EX- OR gate. BTL 2 Understanding
BTL 4 Analyzing
11. (i) Given Y(A,B,C,D)= (8) M (0,1,3,5,6,7,10,14,15) , Draw the
K-Map and Obtain the simplified expression. Design the
minimum expression using basic gates. (8)
(ii) Construct the expression Y (A, B, C) = M (0,2,4,5,6) using BTL 6 Creating
Only NOR-NOR logic. (5)
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12. What are the advantages of using tabulation method? Develop the
following Function using Tabulation method
F= (1,2,3,7,8,9,10,11,14,15) and implement using only NAND BTL 3 Applying
(13)
13. i. Convert (725.25)8 to its decimal, binary and Hexadecimal
equivalent. (6)
ii. Find 1’s and 2’s Complement of 8 digit binary numbers BTL 2 Understanding
10101101 (7)
PART C
1. Design the given function using Prime implicant method and
Verify your result using K map F= m(0,1,2,4,5,6,8,9,12,13,14) BTL 6 Creating
(15)
2. A staircase light is controlled by two switches , one is at the top
of the stairs and the other is at the bottom of the stairs :
i. Make a truth table for this system. (3)
ii. Write the logic function in SOP form. (3) BTL 5 Evaluating
iii. Realize the circuit using AOI logic. (4)
Realise the circuit using minimum number of NAND and
NORgates. (5)
11. (i) Give a combinational circuit that converts 4 bit Gray Code to a 4 bit
binary number. Implement the circuit. (8) BTL 1 Remembering
(ii) Develop a Full adder using decoder. (5) BTL 3 Applying
12. (i) How would you design a 3:8 decoder using basic gates? (7) BTL 1 Remembering
(ii) How would you design a binary to gray code convertor? (6) BTL 4 Analyzing
13. (ii) Describe the design of Binary Multiplier using Shift Add method.
(6)
(ii) Show the design of excess 3 to BCD code converter using minimum BTL 1 Remembering
number of NAND gates (7)
14. (i) Estimate the logic diagram of BCD-Decimal decoder and explain its
operations. (7)
(ii) Interpret the design of a BCD to seven segment decoder with neat BTL 5 Evaluating
diagrams. (6)
PART C
1. With necessary diagrams, explain in detail about the working of a 4-bit look
ahead carry adder. Also mention its advantages over conventional adder.(15) BTL 5 Evaluating
BTL 1 Remembering
2. (i) Compare the diagram of a 4-bit SISO SIPO, PIPO and PISO shift
register and draw its waveforms. (8) BTL5 Evaluating
(ii) Realize D flip-flop using SR flip-flop. (5) BTL 2 Understanding
BTL 4 Analyzing
6. (i)Show the operation of universal shift register with neat block diagram. BTL 1 Remembering
(7)
(ii)Estimate the design a counter to count the sequence 0, 1, 2, 4, 5, 6 BTL 5 Evaluating
,…..using SR FF’s. (6)
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7.
(i) Interpret design of a 3 bit synchronous counter using JK flip-flop.
(10) BTL 3 Applying
(ii) Differentiate between a state table, characteristic table and an BTL 2 Understanding
excitation table for D Flip Flop. (3)
8. How would you describe the design of following:
(i) Synchronous counter with states 0, 1, 2, 3, 0, 1, .... using JK flip flop.
(7) BTL 1 Remembering
(ii) Write short notes on Mealy and Moore sequential circuits . (6)
9. (i) Use T flip-flop to design counter with the following repeated binary
sequence 0, 4, 7, 2, 3. (8) BTL 2 Understanding
(ii) Realize JK Flip Flop using SR Flip Flop (5) BTL 2 Understanding
10. (i) Illustrate with diagram an asynchronous decade counter & its
operation with neat waveforms. (7) BTL 1 Remembering
(ii) Predict the design of a synchronous 3-bit counter which counts in the BTL 2 Understanding
sequence 1, 3, 2, 6, 7, 5, 4, (repeat ) 1, 3..... using T FF . (6)
11. Using SR flipflops design a parallel counter which counts in the sequence
000,111,101,110,001,010,000,… (13) BTL 6 Creating
12. (i) Discuss in detail about the pulse- triggered S-R Flip Flop with
necessary diagrams. (7)
(ii) Deduce a clocked synchronous sequential machine using T flip flops
for the following state diagram. Use state reduction if possible .Also
use straight binary state assignment. (6) BTL 2 Understanding
BTL 4 Analyzing
13. (i) Using D flip-flop, Design a synchronous counter which counts in the
sequence 000,001,010,011,100,101,110,111,000. (10) BTL 3 Applying
(ii) Discuss the working of 4 bit Johnson counter with neat diagram. (3) BTL 1 Remembering
14. (i) Point out a sequence detector design which detects the sequence BTL 4 Analyzing
01110 using D flip flop. (7) BTL 1 Remembering
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(ii) Enumerate about Triggering of Flip-Flop. (6)
PART C
1. Design a J-K counter that goes through states 3,4, 6 , 7 and 3….. Is the
counter self – starting ? Modify the circuit such that whenever it goes to an BTL 6 Creating
invalid state it comes back to state 3. (15)
2. Explain the functions with the state diagram and characteristics equation of T
FF, D FF and JK FF and compare and contrast among the FFs? (15) BTL 5 Evaluating
3. A sequential machine has one input line where 0’s and 1’s are being
incident. The machine has to produce the output of ‘1’ only when exactly
two ’0’s are followed by ‘1’ or exactly two ‘1’s are followed by a ‘0’. Using BTL 6 Creating
any statement assignment in JK flipflop, synthesize the machine. (15)
4. Determine the design of a clocked sequential machine using JK Flip Flops
for the state diagram shown in figure. Use state reduction if possible and
make proper state assignment. (15)
BTL 5 Evaluating
Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments,
Hazards, Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.
PART A
BT
Q. No Questions Domain
Level
1. Mention the steps for the design of asynchronous sequential circuit? BTL 1 Remembering
2. Classify Asynchronous sequential circuits. BTL 2 Understanding
Bring out the difference between fundamental mode and pulse mode
3. sequential circuits BTL 4 Analyzing
12. Compile fundamental mode and pulse mode asynchronous sequential BTL 6 Creating
circuits.
13. Analyze the causes of essential Hazard. BTL 4 Analyzing
14. Construct a combinational Hazard free circuits. BTL 6 Creating
15. Explain the analysis procedure of asynchronous sequential circuits. BTL 5 Evaluating
16. List the different techniques used in State assignment. BTL 1 Remembering
17. Model a Stable circuit and give one example. BTL 3 Applying
Identify the types of Hazards that exist in asynchronous sequential
18. BTL 1 Remembering
circuits.
Interpret critical race and give the methods for critical-race free state
19. BTL 5 Evaluating
assignment.
20. How can a race in digital circuits can be avoided? BTL 1 Remembering
PART – B
1.
Design an asynchronous sequential circuit with 2 inputs T and C. The
output attains a value of 1 when T=1 and C moves from 1 to 0. BTL 6 Creating
Otherwise the output is 0. (13)
2. (i) What are the types of hazards? Check whether the following circuit
contains a hazard or not Y = X1X2 + X2′X3.If the hazard is present,
BTL 1 Remembering
Demonstrate its removal. (13)
Y= X1X2+(X1+X2) Y, Z=Y.
11.
Explain with neat diagram the different hazards and the
way to eliminate them. (13) BTL 3 Applying
13. Classify the methods of Race Free State assignment and explain in
BTL 2 Understanding
detail. (13)
14. Design an Asynchronous sequential circuit with input A and B and an output
Y. Initially at any time if both the inputs are 0, the output, Y=0 . When A or B
= 1, Y =1. When the other input also become 1, Y=0. The output stays at 0
BTL 3 Applying
until circuit goes back to initial state.
(13)
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PART – C
1. Design a asynchronous sequential circuit with two inputs X and Y and
with one output Z. Whenever Y is one, input X is transferred to Z. When
BTL 6 Creating
Y is zero, the output does not change for any change in X.
(15)
2. Design a asynchronous D- type latch with two inputs C and D and BTL 5 Evaluating
output Q. Assume fundamental mode of operation. (15)
3. EAssess a circuit with primary inputs A and B to give an output Z equal
xto 1 when A becomes 1 if B is already 1. Once Z = 1 it will remain so
until A goes to 0. Draw timing diagram, state diagram, Primitive flow
table for designing the circuit. BTL 6 Creating
(15)
4. Construct an asynchronous circuit that will output only the first pulse
BTL 5 Evaluating
received and will ignore other pulses. (15)
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UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS
Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static and dynamic
RAM - Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic
(PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using
PLA, PAL. Digital integrated circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-in,
noise margin, logic families and their characteristics-RTL, TTL, ECL, CMOS
PART A
z 2 ace
z3 bc de cd e bd and
z 4 ace ce
using a 5*8*4 PLA. (7)
(ii) Write short notes on EPROM and EEPROM. (6) BTL 1 Remembering
11. (i) Compare types of logic families and explain a short note on
CMOS logic gate. (8) BTL 4 Analyzing
(ii) Implement the following function using PLA F1=∑ (0, 1, 2, 4)
and F2 = ∑ (0, 5, 6, 7). (5) BTL 5 Evaluating
12. Recognize the implementation of the following Boolean functions
using 4 × 3 × 4 PAL. (13)
(i) W(A,B,C,D)= ∑ (0,2, 6,7,8,9,12,13)
(ii) X(A,B,C,D)= ∑ (0, 2, 6, 7, 8, 9, 12, 13, 14) BTL 1 Remembering
(iii)Y(A, B, C, D) = ∑ ( 2, 3, 8, 9, 10, 12, 13)
(iv) Z(A,B,C,D)= ∑ (1, 3, 4, 6, 9, 12, 14)
(i) Examine
i. 2 the structure of ECL and TTL (7)
13. (ii) Outline about Tri state inverter configuration with neat BTL 1 Remembering
diagram. (6)
14. (i) Explain EAPROM and static RAM cell using MOSFET? (5)
(ii) Recognize 512 X 8 ROM using eight 64x8 ROM chips with an BTL 1 Remembering
enable input and a decoder? (8)
PART C
1. Design a combinational circuit using CMOS logic. The circuit
accepts a three bit number and outputs a binary number equal to the BTL 6 Creating
square of the input number. (15)
2. Develop the code converters using PROM devices. (15)
(i) Binary to gray code BTL 5 Evaluating
(ii) Gray to Binary code
3. (i) Interpret how does Programmable logic devices differ from
FPGA? (8)
(ii) Formulate the implementation of the following functions with
PLA having three inputs, four product terms, and two outputs. BTL 5 Evaluating
F1 (A, B, C) = (3, 5, 6, 7)
F2 (A, B, C) = (0, 2, 4, 7) (7)
4. Build the structure of PAL and PLA. How a combinational logic
function is implemented in PAL and PLA? Explain with an example BTL 6 Creating
for each. (15)