HPC MCQ List

1) A collection of lines that connects several devices is called

A. Bus

B. Peripheral connection wires

C. Both a and b

D. internal wires

2) Conventional architectures coarsely comprise of a

A. Processor

B. Memory System

C. Data path

D. All of the above

3) VLIW processors rely on

A. Compile time analysis

B. Initial time analysis

C. Final time analysis

D. id time analysis

4) HPC is not used in high span bridges

A. True

B. False

5) The access time of memory is …………… the time required for performing any single CPU operation.

A. longer than

B. shorter than

C. negligible than

D. same as

6) Data intensive applications utilize_

A. High aggregate throughput

B. High aggregate network bandwidth

C. high processing and memory system performance

D. none of above
7) Memory system performance is largely captured by_

A. Latency

B. bandwidth

C. both a and b

D. none of above

8) A processor performing fetch or decoding of different instruction during the execution of another
instruction is called.

A. Super-scaling

B. Pipe-lining

C. Parallel Computation

D. none of above
9) For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?

A. ISA

B. ANSA

C. Super-scalar

D. All of the above

10) HPC works out to be economical.

A. True

B. False

11) High Performance Computing of the Computer System tasks are done by

A. Node Cluster

B. Network Cluster

C. Beowulf Cluster

D. Stratified Cluster

12) Octa Core Processors are the processors of the computer system that contains

A. 2 Processors

B. 4 Processors

C. 6 Processors

D. 8 Processors
13) Parallel computing uses _ execution

A. sequential

B. unique

C. simultaneous

D. None of above

14) Which of the following is NOT a characteristic of parallel computing?

A. Breaks a task into pieces

B. Uses a single processor or computer

C. Simultaneous execution

D. May use networking

15) Which of the following is true about parallel computing performance?

16) ________ leads to concurrency.

A. Serialization

B. Parallelism

C. Serial processing

D. Distribution

17) Which MIMD systems are best scalable with respect to the number of processors

A. Distributed memory computers

B. ccNUMA systems

C. Symmetric multiprocessors

D. None of above

18) To which class of systems does the von Neumann computer belong?

A. SIMD (Single Instruction Multiple Data)

B. MIMD (Multiple Instruction Multiple Data)

C. MISD (Multiple Instruction Single Data)

D. SISD (Single Instruction Single Data)

A. RISC

B. CISC

C. ISA

D. IANA

20) The computer architecture aimed at reducing the time of execution of instructions is __.

A. RISC

B. CISC

C. ISA

D. IANA

21) Type of microcomputer memory is

A. processor memory

B. primary memory

C. secondary memory

D. All of above

22) A pipeline is like_

A. Overlaps various stages of instruction execution to achieve performance.

B. House pipeline

C. Both a and b

D. A gas line

23) Scheduling of instructions is determined_______

A. True Data Dependency

B. Resource Dependency

C. Branch Dependency

D. All of above

24) The fraction of data references satisfied by the cache is called_______

A. Cache hit ratio

B. Cache fit ratio

C. Cache best ratio

D. none of above
25) A single control unit that dispatches the same Instruction to various processors is__

A. SIMD

B. SPMD

C. MIMD

D. none of above

26) The primary forms of data exchange between parallel tasks are_

A. Accessing a shared data space

B. Exchanging messages.

C. Both A and B

D. none of above

27) Switches map a fixed number of inputs to outputs.

A. True

B. False
28) computers in which each processing element is capable of executing a different program
independent of the other processing elements are called __________ computers

A. SIMD

B. SPMD

C. MIMD

D. none of above

29) If the time taken by a processor to access any memory word in the system (global or local) is
identical, the platform is classified as a ____________ multicomputer.
A. UMA (uniform memory access)
B. NUMA (nonuniform memory access)
C. Both A and B
D. none of above

30) The issue of multiple copies of a single memory word being manipulated by two or more
processors at the same time is referred as ____________

A. cache coherence

B. Cache fit ratio

C. Cache miss

D. None of these
31) __________ consist of point-to-point communication links among processing nodes and are also
referred to as direct networks.

A. Static networks

B. Dynamic networks

C. Both A and B

D. none of above

32) "Dynamic networks are also

referred to as___________ networks"

A. indirect networks

B. direct networks

C. Both A and B

D. none of above

33) In a ____________ network, one processor acts as the central processor.

A. star-connected

B. bus

C. mesh

D. none of above

34) The ____________ of a network is the maximum distance between any two processing nodes in
the network.

A. diameter

B. connectivity

C. bisection

D. none of above