Digital Signal Processors - 2021

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DIGITAL SIGNAL

PROCESSORS
Prof. Anjan Rakshit and Prof. Amitava Chatterjee
Electrical Measurement and Instrumentation Laboratory,
Electrical Engineering Department,
Jadavpur University, Kolkata, India.
Processor Architecture
Categorized by memory organization

 Von Neumann architecture -> Microprocessors

 Harvard architecture -> Digital Signal


Processors
 Modified Harvard architecture ->
Processor Architecture
Categorized by memory organization

Program and Data


memory

Von Neumann architecture

The Von Neumann architecture is a design model for a stored-program digital computer
that uses a processing unit and a single separate storage structure to hold both instructions
and data.
Processor Architecture
Categorized by memory organization

Program memory Data memory

Harvard architecture

The Harvard architecture is a computer architecture with physically separate storage and
signal pathways for instructions and data.
Von Neumann versus Harvard
Processor Architecture
Categorized by memory organization

Program/Data
Program memory
memory

Modified Harvard architecture

The Modified Harvard architecture is very much like the Harvard architecture but
provides a pathway between the data memory and the CPU that allows some words
from the data memory to be treated as instructions.
Processor Architecture of TMS320C25
A second generation Digital Signal Processor from Texas Instruments
with Modified Harvard architecture

 Single-cycle Multiply/Accumulate Instructions


 Bit-reversed Indexed-Addressing Mode for Radix-2 FFT
Single-cycle Multiply/Accumulate Instructions are
necessary for a Digital Signal Processor to implement
FIR/IIR digital filters and FFT algorithms for real-time
applications.

x1 g1
Computation of butterfly
for radix-2 FFT w41
x3 g1/
w43 = - w41
TMS320C25 Multiply/Accumulate Operation

16-bit data bus 16-bit instruction bus


16

16
Multiplier X MUX

32

Left/right shift 16-bit data bus


32 32

32-bit ALU
32

MUX
16 16
HI LO

16-bit data bus


TMS320C25 Multiply/Accumulate Operation
TMS320C25 Benchmarks (40 MHz Clock)

 FIR filter tap ~ 100 nano Sec per tap

 256 tap FIR filter sample rate ~ 37 KHz

 Second order IIR filter sample rate ~ 1 MHz

 8-point FFT sample rate ~ 50 KHz

 Single PID control loop sample rate ~ 750 KHz

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