ANALOG

EXPERIMENTS
CIRCUIT DIAGRAM:
Expt. No.:
DESIGN OF REGULATED POWER SUPPLIES
Date:

AIM:
To design a regulated power supply which can convert unregulated an AC(alternating
current or voltage) to a constant DC(direct current or voltage).

APPARATUS REQUIRED:
Sl.N Name of the Apparatus Specificatio
o. ns
1 Diodes IN 4001
230V/
2 Transformer(Step Down)
(12-0-
12)V
4 Ammeter (0- 10) V
5 Resistor 4K, 1K
5 Capacitor 0.1μF,470μF
6 BreadBoard
7 Connecting Wires and Probes

INTRODUCTION:
Today almost every electronic device needs a DC supply for its smooth operation
and they need to be operated within certain power supply limits. This required DC voltage or
DC supply is derived from single phase ac mains.

A regulated power supply can convert unregulated AC (alternating current or voltage) to

constant DC (direct current or voltage). A regulated power supply is used to ensure that the
output remains constant even if the input changes. A regulated DC power supply is also called a
linear power supply, it is an embedded circuit and consists of various blocks. The regulated
power supply will accept an AC input and give a constant DC output.

A regulated power supply consists of an ordinary power supply and voltage regulating
device. The output of an ordinary power supply is fed to the voltage regulator which produces
the final output. The output voltage remains constant whether the load current changes or there
are fluctuations in the input AC voltage. the regulated power supply is a combination of three
circuits
:

TABULATION:
Voltage across the Capacitor::

Load Resistance
Voltage Current Current
(RL) Iz IL
across
RL (mA) (mA)
 (i) bridge rectifier (ii) a capacitor filter C and (iii) zener voltage regulator. The bridge rectifier
converts the transformer secondary AC voltage (pointP) into pulsating voltage (pointQ). The
pulsating DC voltage is applied to the capacitor filter. This filter reduces the pulsations in the
rectifier DC output voltage (pointR). Finally, the zener voltage regulator performs two
functions. Firstly, it reduces the variations in the filtered output voltage. Secondly, it keeps the
output voltage (Vout) nearly constant whether the load current changes or there is change in
input AC voltage. Note that bridge rectifier and capacitor filter constitute an ordinary power
supply. However, when a voltage regulating device is added to this ordinary power supply, it
turns into a regulated power supply.

Due to the offset voltage VZ, there is a specific range of resistor values (and therefore load
current) which will ensure that the Zener is in the “on'' state. Too small a load resistance RL will
result in a voltage VL across the load resistor less than VZ, and the Zener device will be in
the“off” state. To determine the minimum load resistance of Fig. 2.106 that will turn the Zener
diode on, simply calculate the value of RL that will result in a load voltage VL=VZ.
That is,

Solving for RL, we have

Any load resistance value greater than the R L obtained from the above equation will ensure that
the Zener diode is in the“on”state and the diode can be replaced by its VZ source equivalent.
The condition defined by above equation establishes the minimum R Lbut in turn specifies the
maximum ILas

Once the diode is in the“on”state,the voltage across R remains fixed at

and IR remains fixed at

The Zener current

resulting in a minimum IZ when IL is a maximum and a maximum IZ when ILis a minimum

value since IRis constant. Since IZ is limited to IZM as provided on the data sheet, it does affect
the range of RL and therefore IL. Substituting IZM for IZ establishes the minimum IL as

and the maximum load resistance

.
RESULT:
Thus the output of Half Wave and Full Wave Rectifiers were obtained and the curves were
plotted.
CIRCUIT DIAGRAM:

COMMON EMITTER AMPLIFIER:

R147 RC
CC2 O
K 2.2K
10uF

CC115
uF
BC107

RL8
V
20
+

R210
RE CE
K
620 1uF
-

COMMON BASE AMPLIFIER:

VCC=20V

50K
10K
1uF

BC107
1uF

VO
10uF
VIN
20K 5K 50mV
1KHz
Expt.No.: FREQUENCY RESPONSE OF COMMON EMITTER,
Date: COMMON BASE & COMMON COLLECTOR
AMPLIFIER

AIM:
To implement the CE, CB & Cc amplifiers with voltage divider bias and to calculate
The following parameters
1. Cut-off frequencies
2. Bandwidth
3. Midband gain

APPARATUS REQUIRED:

Sl.No Name of the Apparatus Specification

.
1. Power supply (0-30)V
2. Multi-meter -
3. Function generator (0-1)MHz
4. 47K,10K,2.2K,620,52K,
Resistors 22K,4.7K,10K, 33K,3.3K
5. Capacitors 1μF,10μF,15μF
6. Bread board & wires -
7. Transistor BC107

THEORY:
COMMON EMITTER AMPLIFIER:

The single stage common emitter amplifier circuit shown in the figure uses what is
commonly called “Voltage Divider Biasing''. This type of biasing arrangement uses two
resistors as a potential divider network across the supply with their centre point supplying the
required Base bias voltage to the transistor. Voltage divider biasing is commonly used in the
design of bipolar transistor amplifier circuits. This method of biasing the transistor greatly
reduces the effects of varying Beta, (β) by holding the Base bias at a constant steady voltage
level allowing for best stability. The quiescent Base voltage (Vb) is determined by the potential
divider network formed by the two resistors, R1, R2and the power supply voltage Vcc as shown
with the current flowing through both resistors. Then the total resistance RT will be equal to R1
+ R2 giving the current as i = Vcc/RT. The voltage level generated at the junction of resistors
R1and R2 holds the Base voltage (Vb) constant at a value below the supply voltage. Then the
potential divider network used in the common emitter amplifier circuit divides the input signal
in proportion to the resistance.
COMMON COLLECTOR AMPLIFIER:
+VCC=12V

R122K

CC110uF

BC107
CC210uF

+
+
R233K
Vs =100mV RE
VO
f=1Khz 3.3K
-

TABULATION:
VIN=
OUTPUT GAIN (dB) =20
Sl. FRE
N Q( VOLTAGE LOG
o. Hz) (Vo) (Vo/Vin)
CE CB C CE C CC
C B
COMMON BASE AMPLIFIER:
It is called the common-base configuration because (DC power source aside), the signal
source and the load share the base of the transistors common connection point.This
configuration is used for high frequency applications because the base separates the input and
output, minimizing oscillations at high frequency.It has a high voltage gain, relatively low input
impedance and high output impedance compared to the common collector.

Perhaps the most striking characteristic of this configuration is that the input signal
source must carry the full emitter current of the transistor, as indicated by the heavy arrows in
the first illustration. As we know, the emitter current is greater than any other current in the
transistor, being the sum of base and collector currents. In the last two amplifier configurations,
the signal source was connected to the base lead of the transistor, thus handling the least current
possible.

COMMON COLLECTOR AMPLIFIER:

Emitter follower is a popular name for a common collector amplifier. Its voltage gain is
unity; current gain and power gain are greater than1. By virtue of high input impedance and low
output impedance of this amplifier configuration, it is useful for impedance matching
applications.

Since the collector is directly connected to the dc source, the collector appears to be
grounded for ac signals. The output is taken from the emitter terminal with respect to ground.
This output voltage is in phase and approximately equal to the input voltage. The name emitter
follower came from the fact that phase of the output signal at the emitter follows the phase of
the input signal at the base. Voltage divider bias is commonly used to bias the emitter follower
amplifier.

PROCEDURE:
1. Check the hfe of the transistor using a multimeter (hfe> 100).
2. Connect the circuit as per the circuit diagram.
3. Connect the dc power supply, verify the dc condition VCE= 6 V.
4. Set Vs=50mVatf=1KHz in the signal generator and then connect it to the circuit.
5. If 50mV is not possible, use the attenuation switch present in the signal generator.
6. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in
regular steps and note down the corresponding output voltage.
7. Plot the graph: gain (dB) Vs frequency.
8. In the graph find the 3dB point (maximum gain–3) and draw an intersecting line.
Calculate the Midband gain, Cut-off frequencies, band width, from the graph.

COMMON EMITTER AMPLIFIER:

Design:
Given data: VCC=12V,IC=IE=2mA,hfe=100,Requird gain of amplifier=50
1. VCE=50 % of VCC= 6V
2. VRE=10% of VCC= 1.2V
3. VRC=40% ofVCC=4.8V
4. VRC=IC*RCRC=VRC/IC=4.8/
(2*10-3)=2.4kΩ
 RC=2.4kΩuse2.2kΩ

5. VRE=IE*RERE=VRE/IE=1.2/
(2*10-
3)=600ΩRE=600Ωuse620 Ω

6.IB=IC/hfe=(2*10-3)/100=20µA

7. Assume:Current through
R1=IR1=10IBCurrent through
R2=IR2=9IB

8. Voltage drop across

R2=VR2=VBE+VRE=0.7+1.2=1.9VByOhm’slawVR2=IR2
*R2
From This,R2=VR2/IR2=1.9/9IB=1.9/(9*20µA)=10.6kΩ
R2=10.6 kΩ use10kΩ

9. Voltage drop across R1=VR1=VCC-VR2=12-

1.9=10.1VBy Ohm’s law:
VR1=IR1*R1R1=VR1/IR1=10.1/10IB=10.1/(10*20µA)=50
kΩR1=50kΩuse47 kΩ

10. The gain of the common emitter amplifier is given by the expression Av=-(rc/re)
Where rc=RC||RL
re=25mV/IE=25mV/2mA=12.5Ω
Since required gain= 50,substituting we get RL=845
RL=845use820Ω

11. XC1≤ Rin/10. Here Rin= R1|| R2||R3|| hfere

We get Rin=1.1kΩ then XC1≤110Ω
So,CC1≥1/(2∏FL*110),where FL=100Hz
CC1=14 µFuse15 uF

12. XC2≤Rout/10.Here
Rout=RCThenXC2≤240Ω
So,CC2≥ 1/(2∏FL*240),where FL=100Hz
CC2=6.6 µFuse10uF

13. XCE≤
RE/10Then
XCE≤62Ω
So,CCE≥1/(2∏FL*62),where FL=100 Hz
CCE=0.25µFuse1uF
 GAIN
(dB)

-3dB

FREQUENCY
B.W

FL FH

CALCULATION:
Paramet C C C
er E B C
Lower cut-off frequency FL
Uppercut-off frequency FH
Bandwidth B.W=FH-FL
COMMON COLLECTOR AMPLIFIER:
Design:
Given data:VCC=12V,IC=IE=2mA,hfe=100
1. VRE=50 % of VCC= 6V

2. VRE=IE*RERE=VRE/IE=6/
(2*10-
3)=3kΩRE=3kΩuse3.3kΩ

3.IB=IC/hfe=(2*10-3)/100=20µA

4. Assume: Current through

R1=IR1=10IBCurrent through
R2=IR2=9IB

5. Voltage drop across

R2=VR2=VBE+VRE=0.6+6=6.6VByOhm’slawVR2=IR2
*R2
From This,R2=VR2/IR2=6.6/9IB=6.6/(9*20µA)=37kΩ
R2=10.6 kΩ use10kΩ

6. Voltage drop across R1=VR1=VCC-VR2=12-

6.6=5.4VBy Ohm’s law:
VR1=IR1*R1R1=VR1/IR1=5.4/10IB=5.4/(10*20µA)=27k
ΩR1=27kΩuse22 kΩ

7. Since the output is taken across RE,takeRL=RE

8. XC1≤ Rin/10. Here Rin= R1|| R2||

hfereWe get Rin=13kΩ
thenXC1≤1.3kΩ
So,CC1≥1/(2∏FL*1.3kΩ),whereFL=100Hz
CC1=11 µFuse10 µF

9. Take CC1=CC2= 10 µF
RESULT:
Thus CE,CB CC amplifiers are implemented and all the important parameters are determined from the
graph.
 CIRCUIT DIAGRAM:
COMMON SOURCE AMPLIFIER:

RD
2.7K
CC2
0.022uF
C1 C
0.022uF

BFW10

+ RL
V
RG1M RS1K 4.7K
CS15uF
-

TABULATION: Vin =

FREQUENCY (Hz) Vo(volts) GAIN (dB)=20log (Vo/Vs)

Expt No: FREQUENCY RESPONSE OF COMMON SOURCE
AMPLIFIER

Date:

AIM:
To implement the common source amplifier with voltage divider bias and to calculate
The following parameters.
1. Cut-off frequencies
2. Bandwidth
3. Midband gain

APPARATUS REQUIRED

Sl. Name of the Apparatus Specifications

No.
1 Power Supply (0-30)V
2 Multi-meter -
3 Function generator (0-1)MHz
4 Resistors 2.7K,4.7K,1M
5 Capacitors 0.022µF,15µF
6 Breadboard Wires -
7 Transistor BFW10

THEORY:

Junction field effect transistor (JFET) is a unipolar voltage controlled device. The drain
current is controlled by the voltage at the gate. Like transistors, JFET amplifiers can also be set
upin three configurations namely Common drain, common source and common gate. Common
source configuration is similar to common emitter configuration of transistors.
JFETs can be biased as voltage divider bias or self-bias. A self-bias circuit is shown int
he circuit diagram. Self-bias maintains drain current and Gm relatively constant. Constant gm
results in constant voltage gain. The design of the circuit is done in such a way that the gate
source junction is reverse biased. The reverse biased junction provides high input impedance.
The applied input voltage slightly changes the gate potential and in turn, the drain current
varies. The output voltage varies with the drain current.

DESIGN:

Given Data:ID= IS= 2 mA ; R0= 40 K; gm= 2.5 mA/V; VDD= 12 V; VGS= -2 V; Vg= 0 V;gainAV=
10;RG= 1 M;

1. VRS= VG- VGS

= 0 – (-2 V)
 MODELGRAPH:

GAIN
(dB)

-3dB

FREQUENCY
B.W
FL FH

CALCULATION:

Paramet C
er S
Lower cut-off frequency FL
Uppercut-off frequency FH
Bandwidth B.W=FH-FL
 VRS=2 V
2. RS= VRS/IS= 2 /2mA= 1 K

RS=1 KΩ

3. RD= VRD/ID=5.4 /2 mA=2.7 KΩ

RD=2.7 KΩ

4.A=gm(RD||RL)
FromthisRL=4.7 KΩ

5. XC1≤RG/10
ThenXC1≤0.01MΩ
So, CC1≥1 /(2πFL* 0.01 MΩ), whereFL= 100Hz.
CC1= 0.016 µF, use 0.022
µFTakeCC1=CC2=0.022 µF

6.XCS≤ RS/
10ThenXCS≤
100Ω
So,CS≥1/(2πFL*100), whereFL= 100Hz
CS= 16 µF, use 15 µF

PROCEDURE:
1. Check all the components using a multimeter.
2. Connect The Circuit As per the circuit diagram.
3. Connected Power supply, verify the dc condition VRD= 5.4V.
4. Set Vs =100mVatf=1KHz in the signal generator and then connect it to the circuit.
5. If100mV is not possible, use the attenuation switch present in the signal generator.
6. Keeping the input voltage constant, vary the frequency from 0Hzto1MHz in regular
steps and note down the corresponding output voltage.
7. Plot the graph: gain(dB)Vs Frequency.
8. In the graph find the 3dBpoint(maximum gain–3)and draw an intersecting line.
9. Calculate the Mid-band gain, Cut-off frequencies,& bandwidth, from the graph.

RESULT:

Thus a common source amplifier is implemented and all the important parameters are
determined from the graph.
DARLINGTON AMPLIFIER:
+VCC=12V

R122K

CC110uF

BC107

BC107
+ CC210uF
Vs=100mV
f=1Khz +
-
R2
33 K
RE
VO
3.3K

MODELGRAPH:

GAIN
(dB)

-3dB

FREQUENCY
B.W

FL FH

TABULATION: Vin =
FREQUE V GAIN(dB)=
NCY o 20log (Vo/Vs)
(Hz) (
m
V
)
Expt. No..: FREQUENCY RESPONSE OF DARLINGTON
AMPLIFIER
Date:

AIM:
To implement the Darlington amplifier with voltage divider bias and to calculate the follo

1. Cut-off frequencies
2. Bandwidth
3. Midband gain

APPARATUS REQUIRED:

S. No. Name of the Apparatus Specification

1 Power Supply (0-30)V
2 Multi-meter -
3 Function generator (0-1)MHz
4 Resistors 22K,33K,3.3K
5 Capacitors 10μF
6 Breadboard Wires -
7 Transistor BC107

THEORY:

In electronics, the Darlington transistor (often called a Darlington pair) is a compound

structure consisting of two bipolar transistors (either integrated or separated devices) connected
in such a way that the current amplified by the first transistor is amplified further by the second
one. This configuration gives a much higher common/emitter current gain than each transistor
taken separately and, in the case of integrated devices, can take less space than two individual
transistors because they can use a shared collector. Integrated Darlington pairs come packaged
singly in transistor-like packages or as an array of devices (usually eight) in an integrated
circuit. The Darlington configuration was invented by Bell Laboratories engineer Sidney
Darlington in 1953. He patented the idea of having two or three transistors on a single chip
sharing collector.
A Darlington pair is like a set of feeders with a high current gain (approximately the
product of the gains of the two transistors). In fact ,integrated devices have three leads (B,
CandE), broadly equivalent to those of a standard transistor.

PROCEDURE:
1. Check Hfe Of The Transistor Using Multimeter (hfe>100).
2. Connect The Circuit As per the circuit diagram.
3. Connected Power supply, verify the dc condition VRE=6V.
DESIGN:
Given Data:VCC= 12V, IC=IE=2 mA, hfe= 100

1. VRE= 50% of VCC= 6V

2. VRE= IE* RE
RE= VRE/IE= 6 /(2*10-3) =3 KΩ
RE=3 KΩ,use3.3KΩ

3.IB= IC/hfe= (2*10-3) /100 = 20 µA

4. Assume : Current through R1= IR1= 10

Current through R2= IR2= 9 IB

5. Voltage drop across R2= VR2= VBE+ VRE= 0.6 + 6 =

6.6VByOhm’slaw:VR2= IR2*R2
From This, R2=VR2/IR2=6.6/9IB= 6.6/(9*20µA)=37KΩ
R2=37KΩ,use33KΩ

6. Voltage drop across R1=VR1=VCC-VR2=12-

6.6=5.4VByOhm’slaw:VR1= IR1* R1
R1= VR1/IR1= 5.4 /10 IB=5.4 /(10*20µA) = 27 KΩ
R1=27 KΩ,use22KΩ

7. Since The Output Is Taken across RE, takeRL= RE

8. XC1≤Rin/ 10. Here Rin= R1|| R2||

hfereWegetRin=13KΩ,thenXC1≤1.3K
Ω
So,CC1≥1/(2∏FL*1.3K),whereFL=100Hz
CC1=11 µF,use10µF

9. TakeCC1=CC2= 10 µF

CALCULATION:

Paramet
er
Lower cutoff frequency FL
Upper cutoff frequency FH
Bandwidth B.W=FH-FL
 4. Set Vs =100mV atf=1KHz in the signal generator and then connect it to the circuit.

5. If 100mV is not possible, use the attenuation switch present in the signal generator.
6. Keeping the input voltage constant, vary the frequency from 0Hzto1MHz in regular
steps and note down the corresponding output voltage.
7. Plot The Graph: gain(dB)Vs Frequency.
8. In the graphfindthe3dBpoint(maximum gain–3)and draw an intersecting line.
9. Calculate the Midband Gain, Cut-off frequencies,& bandwidth, from the graph.
10. To measure the input impedance ZI, connect a 10 K resistor in series with the signal
generator and note down the potential difference across the resistor. Calculate the
current through the resistor. The input impedance is equal to the ratio of the voltage at
the right side of 10 K resistor to the current through it.(use the multimeter in ac mode
for measuring voltage)

RESULT:

Thus the Darlington amplifier is implemented and all the important parameters are determined from
the graph.
DIFFERENTIAL MODE:

COMMONMODE:
Expt No: DIFFERENTIAL AMPLIFIER

Date:

AIM:
To implement the differential amplifier and to calculate the CMRR.

APPARATUS REQUIRED:

Sl. Name of the Apparatus Specifications

No.
1 Power Supply (0-30)V
2 Multi-meter -
3 Functiongenerator (0-1)MHz
4 Resistors 22Ω,1.5K, 4.7K
5 Capacitors 10μF
6 Breadboard Wires -
7 Transistor BC107

THEORY:

The Differential amplifier amplifies the difference between two input voltage
signals.Hence it is called differential amplifier.V1 and V2 are input voltages, Vo is proportional
to difference between two input signals.
If we apply two input voltages equal in all respects then in ideal case output should be
zero. But output voltage depends on the average common level of the inputs. Such an average
level of two input signals is called common mode signal.
Higher the value of C.M.R.R, better the performance of the differential amplifier. To
improve C.M.R.R we have to increase differential mode gain and decrease common mode gain.
TABULATION:

DIFFERENTIAL MODE:
Vin=( V1 -
V1 (Volts) V2 (Volts) Vo (Volts) Ad=Vo /Vin
V2 )
(Volts)

COMMON MODE:
Vin=( V1 +V2 ) /2
V1 =V2(Volts) Vo (Volts) Ac=Vo /Vin
(Volts)

CALCULATION:

Differential gain
AD=Common mode gain AC
=CMRR=20log(AD/AC)=
RESULT:

Thus the differential amplifier is implemented and it’s CMRR= dB.

 +VCC=12
V

1. +

i. Vs=50mV
ii. f=1Khz

2. -
Expt No: FREQUENCY RESPONSE OF CASCADE & CASCODE
AMPLIFIER

Date:

AIM:

To implement the cascade & cascode amplifiers with voltage divider bias and to
calculate the following parameters
1. Cut-off frequencies
2. Bandwidth
3. Midband gain

APPARATUS REQUIRED:

Sl.N Name of the Apparatus Specifications

o.
1 Power Supply (0-30)V
2 Multi-meter -
3 Function generator (0-1)MHz
47K,10K,2.2K,620,33K,
4 Resistors
22K,12K,1.2K,560,330
5 Capacitors 1μF,10μF,15μF,22μF
6 Breadboard Wires -
7 Transistor BC107

THEORY:
CASCADED AMPLIFIERS:
Number of amplifier stages connected to each other with the output of the previous
stage to the input of the next stage. The most important parameters of an amplifier are its input
impedance,voltage gain, bandwidth and output resistance. It is not possible for a single stage
amplifier to fulfill all the requirements. Hence we have to use a multistage amplifier which
deals with these requirements. In a multistage amplifier the input stage takes care of the input
impedance while the output stage takes care of the output impedance matching requirements
and the middle stages will fulfill the high voltage gain requirements.
In multistage amplifiers the output of preceding stage is to be connected to the input of
the next stage. This is called as interstage coupling. This can be achieved by using any one of
the following coupling technique.
1. RCcoupling
2. Transformer Coupling
3. Direct Coupling

35
CIRCUITDIAGRAM:
CASCODE AMPLIFIER:

+VCC=12V

R13 RC
3K 1.2K CC31
5uF

CC1 +
15uF

BC107T1

R22
2K

CC2
15uF RL VO
330
BC107T2

+
Vs=50 mV
f=1Khz R31
2K RE CE2
- 560 2uF

36
 In RC coupled amplifiers the output of the first stage is being coupled to the input of the
second stage through a coupling capacitor and a resistive load at the output of the first stage. It
is used in public address systems, tape recorders, TV, VCR, CD player and stereo amplifiers.

CASCODE AMPLIFIER:
A cascode amplifier comprises a common emitter and a common base amplifier stages
cascade. In the circuit diagram shown in the figure, the transistor T2 is in CE configuration and
T1 in CB configuration. Principal advantage of this circuit is its low input capacitance which is
a limiting factor of voltage gain at high frequencies. Cascode amplifiers are able to amplify
higher frequencies than are possible with CE amplifiers because no high frequency feedback
occurs from the output back to input through the miller capacitance as it occurs in CE
amplifiers. Cascode amplifiers provide a smaller voltage gain than CE amplifiers but in wide
range of frequencies. The advantage of CE and CB stages are put together in cascode
connection

DESIGN: (CASCADE AMPLIFIER)

Given Data:VCC=12V,IC=IE=2mA,hfe=100,required gain of amplifier=2

1. VCE= 50% of VCC= 6 V

2. VRE= 10% ofVCC= 1.2V

3. VRC= 40% ofVCC= 4.8V

4. VRC= IC* RC
RC= VRC/IC= 4.8 /(2*10-3)= 2.4 KΩ
Rc=2.4 KΩ,use2.2 KΩ

5. VRE= IE* RE
RE=VRE/IE= 1.2 /(2*10-3) = 600 Ω
RE=600Ω,use620Ω

6.IB= IC/hfe= (2*10-3) /100 = 20 µA

7. Assume :Current through R1=IR1= 10IB

Current throughR2=IR2=9IB

37
8. Voltage drop across R2= VR2= VBE+ VRE= 0.7 + 1.2 = 1.9
VByOhm’sLaw:VR2= IR2* R2
R2= VR2/IR2=1.9 /9 IB= 1.9/(9*20 µA) = 10.6 KΩ
R2=10.6 KΩ,use10 KΩ

9. Voltage drop across R1= VR1= VCC-VR2= 12 - 1.9 = 10.1

VByOhm’sLaw:VR1= IR1*R1
R1= VR1/IR1= 10.1 /10IB=10.1 /(10*20µA) =50 KΩ
R1=50 KΩ,use47 KΩ

10. The gain of the common emitter amplifier is given by AV= (RC|| RL) /
reWhere,re= 25 mV/IE= 2 mA= 12.5 Ω
Since required gain =2, substituting we getRL=23Ω,use22Ω

11. XC1≤ Rin/ 10. Here Rin= R1|| R2||

hfereWegetRin= 1.1 KΩ,thenXC1≤110
Ω
So,CC1≥1 /(2πFL* 110), whereFL= 100Hz.
TakeCC1=14 µF,use15µF

12. XC2≤ Rout/ 10. Here Rout=

RCThenXC2≤240 Ω
So,CC2≥1 /(2πFL* 240), whereFL= 100Hz.
TakeCC2=CC3=6.6 µF, use10 µF

13. XCE≤ RE/

10ThenXCE≤62
Ω
So, CE≥1 /(2πFL* 62), whereFL= 100Hz.
CE=0.25 µF, use1 µF
DESIGN: (CASCODE AMPLIFIER)

Given Data:VCC=12V,IC=IE=2mA,hfe=100,Required Gain Of Amplifier=20

1. VCE1= VCE1* 35% ofVCC= 4.2V

2. VRE= 10% of VCC= 1.2V

3. VRC= 20% of VCC= 2.8V

4. VRC=IC*RC
RC= VRC/IC=2.8 /(2*10-3)= 1.2 KΩ
Rc=1.2 KΩ

5. VRE=IE*RE
RE=VRE/IE= 1.2 /(2*10-3) = 600 Ω
RE=600Ω,use560Ω

6.IB= IC/hfe= (2*10-3) /100= 20 µA

7. Assume : Current through R1= IR1= 10

Current through R2= IR2=9 IB
Current Through R3= IR3= 8 IB

8. From the circuit we can

obtain :VCC–VR1–VBE2–VCE1–
VRE=0VR1= VCC – VBE2– VCE1–
VRE VR1= 12– 0.6 – 4.2 – 1.2
VR1=6 V

9. By Ohm’s Law :VR1=IR1* R1

R1=VR1/IR1=6/10 IB= 6/(10*20µA) =30KΩ
R1=30 KΩ,use33KΩ

10. From the circuit we can

obtain: VCC – VR1-VR2-VBE2-
VRE= 0VR2= VCC– VR1-VBE2-
VRE
VR2= 12– 6– 0.6 – 1.2
VR2=4.2V

11. By Ohm’s law :VR2=IR2*R2

R2= VR2/IR2= 4.2 /9IB= 4.2/(9*20 µA)= 23.3 KΩ
R2=23.3 KΩ, use22 KΩ
12. VR3=VBE2+VRE
= 0.6 +1.2
VR3=1.8V

13. By Ohm’s law:VR3=IR3*R3

R3= VR3/IR3=1.8 /8 IB=1.8/(8*20 µA) = 11.2 KΩ
R2=11.2 KΩ,use12 KΩ

14. Gain AV=gm(RC||RL)

Where,gm=IC/VT=2mA /26mV
Since Required gain= 20,substituting we getRL=330 Ω

15. XC1≤Rin/10. HereRin= R2||R3||

hfeREWegetRin= 1 KΩ,then XC1≤0.1
KΩ
So,CC1≥1/(2πFL*0.1 K), whereFL= 100Hz.
TakeCC1=CC2=CC3=15 µF

16. XCE≤ RE/

10ThenXCE≤60
Ω
So,CE≥1 /(2πFL* 60), whereFL= 100Hz.
CE=22µF
PROCEDURE:

1. Check Hfe Of The Transistor Using Multimeter(hfe> 100).

2. Connect The Circuit As per the circuit diagram.
3. Connect The Dc Power Supply, verify the condition VCE= 6 V.
4. Set Vs=50mVatf= 1KHz in the signal generator and then connect it to the circuit.
5. If 50mV isn't possible, use the attenuation switch present in the signal generator.
6. Keeping the in put voltage constant, vary the frequency from 0Hz to 1MHz in regular
steps and note down the corresponding output voltage.
7. Plot The Graph: gain (dB)Vs Frequency.
8. In the graph find the 3dB point (maximum gain–3) and draw an intersecting line.
Calculate the Midband Gain, Cut-off frequencies,& bandwidth, from graph.
TABULATION:
VIN= 50 mv
GAIN(dB)=20
OUTPUT(Vo)
Sl.N FREQUENC log
o. Y (Vo/Vin)
CASCAD CASCOD CASCAD CASCOD
E E E E

CALCULATION:

Paramet Cascade Cascode

er
Lower cut off frequency FL

Upper cutoff frequency FH

Bandwidth B.W=FH-FL
RESULT:
Thus the cascade & cascade amplifiers are implemented and all the important
parameters are determined from the graph.
CIRCUIT DIAGRAM:
SINGLE STAGE AMPLIFIER:
+VCC=12V

R147K RC
CC2
2.2K
10uF

+
CC115uF

BC107

RL820
VO
+
Vs=50mV
f =1Khz R210K
- RE CE
620 1uF

MULTISTAGE AMPLIFIER:

MODELGRAPH:

GAIN
(dB)

-3 dB

FREQUENCY
B.W

FL FH
 SINGLE STAGE & MULTISTAGE AMPLIFIERS WITH VOLTAGE DIVIDER BIAS

AIM:

To implement the single stage & multistage amplifiers with voltage divider bias and to
calculate the following parameters.
1. Cut-off frequencies
2. Bandwidth
3. Midband Gain

APPARATUS REQUIRED:

Sl. Name of the Apparatus Specifications

No.
1 Power Supply (0-30)V
2 Multi-meter -
3 Functiongenerator (0-1)MHz
4 Resistors 47K,10K,2.2K,620
5 Capacitors 1μF,10μF,15μF
6 Breadboard Wires -
7 Transistor BC107

THEORY:

The output from a single stage amplifier is usually insufficient to drive an output device.
In other words, the gain of a single amplifier is inadequate for practical purposes.
Consequently, additional amplification over two or three stages is necessary. To achieve this,
the output of each amplifier stage is coupled in some way to the input of the next stage. The
resulting system is referred to as a multi stage amplifier .It may be emphasized here that
practical amplifiers are always multistage amplifiers. For example, in a transistor radio receiver,
the number of amplification stages may be six or more.
In a multistage amplifier, a number of single amplifiers are connected in cascade
arrangement i.e. output of first stage is connected to the input of the second stage through a
suitable coupling device and soon. The Purpose Coupling device(e.g. a capacitor, transformer
etc.) is (i) to transfer a.c. output of one stage to the input of the next stage and (ii) to isolate the
d.c. conditions of one stage from the next stage.
TABULATION:
VIN= 50 mV

Gain(dB)
Output (Vo)
Sl.N Frequency =20log(Vo/V
o. in)
Single Multi Single Multi

CALCULATION:

Paramet Sing Mu
er le lti
Lower cut off frequency FL
Upper Cutoff Frequency FH
Band width B.W=FH-FL
PROCEDURE:
Check Hfe Of The Transistor Using Multimeter(hfe> 100).
1. Connect the circuit as per the circuit diagram.
2. Connect The Dc Power supply, verify the dc condition VCE=6 V.
3. Set Vs =50mVatf= 1KHz in the signal generator and then connect it to the
circuit.
4. If 50mV is not possible, use the attenuation switch present in the signal
generator.
5. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz
in regular steps and note down the corresponding output voltage.
6. Plot The Graph:gain(dB)Vs Frequency.
7. In the graph find the 3dB point (maximum gain–3) and draw an
intersecting line. Calculate the Mid-band gain, Cut-off frequencies, &
bandwidth, from graph.

RESULT:

Thus the cascade & cascade amplifiers are implemented and all the important
parameters are determined from the graph.
CIRCUIT DIAGRAM
BJT FIXED BIAS:

DC ANALYSIS OF BJT FIXED BIAS OUTPUT:

Expt.No.: ANALYSIS OF BJT WITH FIXED BIAS AND VOLTAGE DIVIDER BIAS US
Date:

AIM:
To analyse BJT with Fixed bias and Voltage divider bias using Spice.

APPARATUS REQUIRED:

Sl.N Components Ran Quanti

o. ge ty
1 Personal - -
. computers
2 PSPICE Software - -
.

THEORY:
DC ANALYSIS OF VOLTAGE DIVIDER BIAS CIRCUIT:
The Thevenin voltage is given
by 𝑅2𝑉𝐶𝐶
𝑉𝑇 =
𝑅+𝑅
Thevenin Resistance Is Given
By 𝑅𝐵
𝑅1𝑅2
=
𝑅+𝑅
The Base Current Is given by

𝐼𝐵 =𝑉𝑇−𝑉𝐵𝐸−𝐼𝐶𝑅𝐸
𝑅𝐵+𝑅𝐸
The Collector-emitter voltage is given by

𝑉𝐶𝐸=𝑉𝐶𝐶−𝐼𝐶𝑅𝐶−𝐼𝐸𝑅𝐸

In this, biasing is provided by three resistors R1, R2 and RE. The resistors R1& R2 act as a
potential divider giving a fixed voltage to base. If collector current increases due to change in
temperature or change in β, emitter current IE also increases and voltage drop across RE
increases thus reducing the voltage difference between base and emitter. Due to reduction in
base emitter voltage, base current and collector current reduces. So we can say that negative
feedback exists in the emitter bias circuit. This reduction in collector current compensates for
the original change in IC.
CIRCUIT DIAGRAM:
BJT VOLTAGE DIVIDER BIAS:

DC ANALYSIS BJT VOLTAGE DIVIDER BIAS OUTPUT:

DC ANALYSIS OF FIXED BIAS CIRCUIT:

The dc analysis of the BJT fixed bias circuit yield the following equation
Apply KVL around the base emitter loop

𝑉𝐶𝐶=𝐼𝐵𝑅𝐵+𝑉𝐵𝐸

The Base Current Is given by

𝑉 −𝑉
𝐼𝐵 = 𝑐𝑐 𝐵𝐸
𝑅𝐵
The Collector –emitter voltage
𝑉𝐶𝐸=𝑉𝐶𝐶−𝐼𝑐𝑅𝑐

For a given transistor, VBE does not vary significantly during use. As V CCis of fixed value, on
selection of RB, the base current IBis fixed. Therefore this type is called a fixed bias type of
circuit.

APPLICATIONS:

Due to the above inherent drawbacks, fixed bias is rarely used in linear
circuits (i.e., those circuits which use the transistor as a current source). Instead, it is often used
in circuits where the transistor is used as a switch. However, one application of fixed bias is to
achieve crude automatic gain control in the transistor by feeding the base resistor from a
DCsignalderived from AC output of a later stage.

RESULT:

Thus the Analysis of BJT with Fixed bias and Voltage divider bias using Spices Are simulated
and the outputs are calculated.
FET FIXED BIAS:

DC ANALYSIS OF FET FIXED BIAS OUTPUT:

Expt. No.: CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTERAND

Expt.No.: ANALYSIS OF FET, MOSFET WITH FIXED BIAS, SELF BIASANDVOLTA
Date:

AIM:
To analyse the FET, MOSFET with Fixed bias, Self bias and Voltage divider bias
Using Spice.

APPARATUS REQUIRED:

Sl.N Components Ran Quanti

o. ge ty
1 Personal - -
. computers
2 PSPICE Software - -
.

THEORY:
FET FIXED BIAS:

DC analysis of the FET Fixed circuit yield the following equation

The gate to source voltage is
𝑉𝐺𝑆=𝑉𝐺-𝑉𝑆=−𝑉𝐺𝐺

The Drain current is

𝐼𝐷 =𝑉𝐷𝐷−𝑉𝐷𝑆
𝑅𝐷

Where 𝑅𝐷 is the drain resistance

IDQ= IDss(1- VGS /Vp) 2

DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain
currentID. For a JFET drain current is limited by the saturation current IDS. Since the FET has
such a high input impedance that no gate current flows and the dc voltage of the gate set by a
voltage divider or affixed battery voltage is not affected or loaded by the FET.
Fixed dc bias is obtained using a battery VGG. This battery ensures that the gate is always
negative with respect to source and no current flows through the resistor RG and gate terminal
that is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but no resulting
current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied
through capacitor C to develop across RG. While any ac signal will develop across RG, the dc
voltage drop across RG is equal to IGRG i.e. 0 volt.
FET SELF BIAS:

DC ANALYSIS OFFETSELFBIAS OUTPUT:

FET SELF BIAS CIRCUIT:

DC analysis of the FET Self bias circuit yield the following equation
The Drain Voltage,
𝑉𝐷=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷
The Drain Source Voltage,

𝑉𝐷𝑆=𝑉𝐷−𝑉𝑆=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷−𝐼𝐷𝑅𝑆

The Gate To Source Voltage

𝑉𝐺𝑆=𝑉𝐺𝐺−𝑉𝑆=−𝐼𝐷𝑅𝑆

The drain current is given by

IDQ=IDss(1-VGS/Vp)2

Self-biasing of a JFET stabilizes its quiescent operating point against any change in its
parameters like transconductance. Any increase in voltage drop across RS, therefore, gate-
source voltage, VGS becomes more negative and thus increase in drain current is reduced.
CIRCUIT DIAGRAM:
FET VOLTAGE DIVIDER BIAS:

DC ANALYSIS OF FET VOLTAGE DIVIDER BIAS OUTPUT:

FET VOLTAGE DIVIDER BIAS CIRCUIT:

The resistors RGl and RG2 form a potential divider across drain supply VDD. The voltage
V2across RG2 provides the necessary bias. The additional gate resistor RGl from gate to supply
voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued RS.

The coupling capacitors assumed be open circuit for D analysis

1) The gate is reverse biased so that IG= 0 and gate voltage

The Gate Voltage

𝑅2
𝑉 = 𝑉
𝐺𝐺 𝐷𝐷
𝑅1+𝑅2

𝑅1𝑅2
𝑅𝐺 =
𝑅+𝑅

2) Applying KVL to the input circuit we get

The Drain Source Voltage, 𝑉𝐷=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷−𝐼𝐷𝑅𝑠

The Gate To Source Voltage, 𝑉𝐺𝑆=𝑉𝐺𝐺−𝐼𝐷𝑅𝑆

The operating point of a JFET amplifier using the Voltage -Divider Bias is determined by
DC analysis of the FET Voltage-Divider Bias yield the following equation

The drain current is IDQ= IDSS(1-VGS/VP)2

CIRCUIT DIAGRAM:
MOSFET FIXED BIAS:
DC ANALYSIS OF MOSFET FIXED BIAS OUTPUT:
MOSFET FIXED BIAS:

DC analysis of the MOSFET Fixed Bias yield the following equation

The Gate To Source Voltage Is

𝑉𝐺𝑆=𝑉𝐺-𝑉𝑆=−𝑉𝐺𝐺

The Drain current is

𝐼𝐷
=𝑉𝐷𝐷−𝑉𝐷𝑆
𝑅𝐷

Where 𝑅𝐷 is the drain resistance

Assuming that 𝑉𝐺𝑆>𝑉𝑇𝑁 and the MOSFET is biased in saturation region ,the drain current is

𝐼𝐷=𝐾𝑁(𝑉𝐺𝑆−𝑉𝑇𝑁)2

The Drain Source Voltage, 𝑉𝐷𝑆=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷

If 𝑉𝐷𝑆>𝑉𝐷𝑆(𝑠𝑎𝑡)=𝑉𝐺𝑆−𝑉𝑇𝑁 the MOSFET is biased in saturation region

MOSFET SELF BIAS:

DC ANALYSIS OF MOSFET SELF BIAS OUTPUT:

MOSFET SELF BIAS:

DC analysis of the MOSFET self-bias circuit yield following equation

The Drain Voltage,
𝑉𝐷=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷
The Drain Source Voltage,
𝑉𝐷𝑆=𝑉𝐷−𝑉𝑆=𝑉
𝐷𝐷−𝐼𝐷𝑅𝐷−𝐼𝐷𝑅𝑆
The Gate To Source Voltage

𝑉𝐺𝑆=𝑉𝐺𝐺−𝑉𝑆=
−𝐼𝐷𝑅𝑆

Assuming that 𝑉𝐺𝑆>𝑉𝑇𝑁 and the MOSFET is biased in saturation region, the drain current is
𝐼𝐷=𝐾𝑁(𝑉𝐺𝑆−𝑉𝑇𝑁)2

The Drain Source Voltage, 𝑉𝐷𝑆=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷

If 𝑉𝐷𝑆>𝑉𝐷𝑆(𝑠𝑎𝑡)=𝑉𝐺𝑆−𝑉𝑇𝑁 the MOSFET is biased in saturation region.

CIRCUIT DIAGRAM:
MOSFET VOLTAGE DIVIDER BIAS:

DC ANALYSIS OF MOSFET VOLTAGE DIVIDER BIAS OUTPUT:

MOSFET VOLTAGE DIVIDER BIAS:

DC analysis of the MOSFET Voltage divider bias circuit yield the following equation
The Gate Voltage
𝑅2
𝑉 = 𝑉
𝐺𝐺 𝐷𝐷
𝑅1+𝑅2

And Gate To Source

Voltage Is
𝑉𝐺𝑆=𝑉𝐷𝐷−𝑉𝐺

Assuming that 𝑉𝐺𝑆>𝑉𝑇𝑁 and the MOSFET is biased in saturation region,the drain current is

𝐼𝐷=𝐾𝑁(𝑉𝐺𝑆−𝑉𝑇𝑁)2

The Drain Source Voltage, 𝑉𝐷𝑆=𝑉𝐷𝐷−𝐼𝐷𝑅𝐷

If 𝑉𝐷𝑆>𝑉𝐷𝑆(𝑠𝑎𝑡)=𝑉𝐺𝑆−𝑉𝑇𝑁 the MOSFET is biased in saturation region.

PROCEDURE:

1. Perform Circuit connection in new simulation profile using PSPICE Software

2. Enter the simulation setting parameters.
3. Finally run the simulation and view the output.

RESULT:

Thus the FET, MOSFET with Fixed bias, Self bias & Voltage divider bias was analysed
and simulated using Spice.
.
CIRCUIT DIAGRAM:
CASCADE AMPLIFIER:

FREQUENCY RESPONSE OF CASCADE AMPLIFIER:

Expt.No.: ANALYSIS OF CASCADE &CASCODE AMPLIFIER USING SPICE
Date:
AIM:
To analyse the frequency response of cascade and cascode amplifiers using Spice

APPARATUS REQUIRED:

Sl.N Components Ran Quanti

o. ge ty
1 Personal - -
. computers
2 PSPICE Software - -
.

THEORY:
CASCADE AMPLIFIERS:

Number of amplifier stages connected to each other with the output of the previous
stage to the input of the next stage. The most important parameters of an amplifier are its input
impedance, voltage gain, bandwidth and output resistance. It is not possible for a single stage
amplifier to fulfill all the requirements. Hence we have to use a multistage amplifier which
deals with these requirements. In a multistage amplifier the input stage takes care of the input
impedance while the output stage takes care of the output impedance matching requirements
and the middle stages willful fill the high voltage gain requirements.
In multistage amplifiers the output of preceding stage is to be connected to the input of
the next stage. This is called as interstage coupling. This can be achieved by using any one of
the following coupling technique.
1. RC coupling
2. Transformer Coupling
3. Direct Coupling
In RC coupled amplifiers the output of the first stage is being coupled to the input of the
second stage through coupling capacitor and a resistive load at the output of the first stage. It is
used in public address systems,tape recorders, TV, VCR, CD players and stereo amplifiers.
CIRCUIT DIAGRAM:
CASCODE AMPLIFIER:

FREQUENCY RESPONSE OF CASCODE AMPLIFIER:

CASCODE AMPLIFIER:

A cascode amplifier comprises a common emitter and common base amplifier stages
cascade.In the circuit diagram shown in the figure, transistor T2 is in CE configuration and T1
in CB configuration. Principal advantage of this circuit is its low input capacitance which is a
limiting factor of voltage gain at high frequencies. Cascode amplifiers are able to amplify
higher frequencies than are possible with CE amplifiers because no high frequency feedback
occurs from the output back to input through the miller capacitance as it occurs in CE
amplifiers. Cascode amplifiers provide a smaller voltage gain than CE amplifiers butin wide
range of frequencies. The advantage of CE and CB stages are put together in cascode
connection

PROCEDURE:

1. Perform Circuit connection in new simulation profile using PSPICE Software

2. Enter the simulation setting parameters.
3. Finally Run the simulation and view the output.

RESULT:

Thus the frequency response of cascade and cascode amplifiers was analysed and
simulated using Spice.
CIRCUIT DIAGRAM:
COMMON EMITTER AMPLIFIER:

FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER:

Expt.No.: ANALYSIS OF FREQUENCY RESPONSE OF BJT AND FET USING SPICE
Date:

AIM:
To analyse the frequency response of the BJT-CE amplifier and FET-CS amplifier,
using Spice.

APPARATUS REQUIRED:

Sl.N Components Ran Quanti

o. ge ty
1 Personal - -
. computers
2 PSPICE Software - -
.

THEORY:
COMMON EMITTER AMPLIFIER:

The single stage common emitter amplifier circuit shown in the figure uses what is
commonly called “Voltage Divider Biasing”. This type of biasing arrangement uses two
resistors as a potential divider network across the supply with their centre point supplying the
required Base bias voltage to the transistor. Voltage divider biasing is commonly used in the
design of bipolar transistor amplifier circuits. This method of biasing the transistor greatly
reduces the effects of varying Beta, (β) by holding the Base bias at a constant steady voltage
level allowing for best stability. The quiescent Base voltage (V b) is determined by the potential
divider network formed by the two resistors, R1, R2 and the power supply voltage Vcc as shown
with the current flowing through both resistors.Then the total resistance RT will be equal to R1
+ R2 Giving the current as i = Vcc/R T. The voltage level generated at the junction of resistors
R1and R2 holds the Base voltage (Vb) constant at a value below the supply voltage. Then the
potential divider network used in the common emitter amplifier circuit divides the input signal
in proportion to the resistance.
CIRCUIT DIAGRAM:
COMMON SOURCE AMPLIFIER:

FREQUENCY RESPONSE OF COMMON SOURCE AMPLIFIER:

COMMON SOURCE AMPLIFIER:

Junction field effect transistor (JFET) is a unipolar voltage controlled device. The drain
current is controlled by the voltage at the gate. Like transistors, JFET amplifiers can also be set
upin three configurations namely Common drain, common source and common gate. Common
source configuration is similar to common emitter configuration of transistors.
JFETs can be biased as voltage divider bias or self-bias. A self-bias circuit is shown
inthe circuit diagram. Self-bias maintains drain current and Gm relatively constant. Constant
gm results in constant voltage gain. The design of the circuit is done in such a way that the gate
to source junction is reverse biased. The reverse biased junction provides high input
impedance.The applied input voltage slightly changes the gate potential and in turn,the drain
current varies. The output voltage varies with the drain current.

RESULT:

Thus the common emitter and common source amplifiers are simulated and the outputs
are plotted.
DIGITAL EXPERIMENTS
AND GATE:
SYMBOL: PIN DIAGRAM:

OR GATE:
Expt. No.:
STUDY OF LOGIC
Date: GATES

AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
Sl.N Name of the Apparatus Specificati Quantity
o. on
1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 NAND Gate 2I/P IC 7400 1
5 NOR Gate IC 7402 1
6 X-OR Gate IC 7486 1
7 NAND Gate3I/P IC 7410 1
8 Digital IC Trainer Kit - 1
9 Patch Cords - As
Required

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate
has one more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR are known as universal gates. Basic
Gates from these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are
low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output
is low when the input is high.
NOT GATE:
SYMBOL: PIN DIAGRAM:

EX-OR GATE:
SYMBOL: PIN DIAGRAM:
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the inputs is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT . The output is high when both inputs are low.
The output is low when one or both inputs are high.
EX-OR GATE:
The output is high when anyone of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs Are given as per circuit diagram.
3. Observe the output and verify the truth table.
2- INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:

NOR GATE:

3- INPUT NAND GATE:

RESULT:
Thus the logic gate truth tables and Boolean expressions are verified.
BINARY TO GRAY CODE CONVERTER:
TRUTH TABLE:
Binary Gray Code Output
Input
B B2 B B G G2 G G0
3 1 0 3 1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1
Date: 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAP FOR BINARY TO GRAY CODE CONVERTER:

K-Map for G0: K-Map for G1:

G0=B1⊕B0 G1=B1⊕B2

K-Map for G3 K-Map for G2

 Expt. No.: DESIGN AND IMPLEMENTATION
Date: OF CODE CONVERTER

AIM:
To design and implement 4-bit
(i) Binary to gray code converter (iii) BCD to excess-3 code converter
(ii) Gray to binary code converter (iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No. Name of the Apparatus Specificati Quantity

on
1 X-OR Gate IC 7486 1
.
2 AND Gate IC 7408 1
.
3 OR Gate IC 7432 1
.
4 NOT Gate IC 7404 1
.
5 IC Trainer Kit - 1
.
6 Patch Cords - AsRequire
. d

THEORY:
Code Converters:

The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for the same in formation.Thus, code
converter is a circuit that makes the two systems compatible even though each uses different
binary code.
Gray Code:

To obtain a different gray code, one can start with any bit information and proceed to
obtain the next bit combination by changing only one bit from 0 to 1(or) 1 to 0 in any desired
random fashion provided any two numbers do not have identical code assignments.Gray code is
a non-weighted code.
LOGIC DIAGRAM:

****************************************************************************

GRAY CODE TO BINARY CONVERTER:

TRUTH TABLE:
GrayInp Binary Code Output
ut
G G G G0 B3 B2 B B0
3 2 1 1

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Binary to Gray Code Conversion Steps:
To convert from binary code to Gray code, the input lines must supply the bit combination
of elements as specified by the code and the output lines generate the corresponding bit
combination of code. Each one of the four maps represents one of the four outputs of the
circuits function of the four input variables.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs.
The input variables are designated as B3, B2,B1, B0 and the output variables are
designated as G3, G2, G1, Go. From the truth table, the combinational circuit is designed. The
Boolean Functions Obtained from K-Map for each output variable.

In the conversion process the most significant bit (MSB) of the binary code is taken
as the MSB of the Gray code. The bit positions G2, G1 and G0 are obtained by adding
(B3,B2),(B2, B1) and (B1, B0) respectively, ignoring the carry generated. From the K-Map
Simplification for binary to Gray code conversion the following Boolean expressions are
obtained,

G3=B3 G2=B3⊕B2 G1=B2⊕B1 G0=B1⊕B0

Gray to Binary Code Conversion Steps:
The example shows the steps involved in conversion of a Gray code to binary code.Gray
code taken for the example is 1110.

In the conversion process the most significant bit(MSB) of the Gray code is taken as
theMSB of the binary code. The bit positions B2,B1 and B0is obtained by adding (B3,G2),
(B2,G1) and (B1,G0) respectively,ignoring the carry generated.From the K-Map simplification
for Gray Code to binary code conversion the following Boolean expressions are obtained,
B3 =G3 B2 =G3⊕G2 B1=G3⊕G2⊕G1 B0 =G3⊕G2
⊕G1⊕G0

Excess-3 Code:
This is an unweighted code. Its code assignment is obtained from the corresponding
value of BCD after the addition of (0011)2.
K-MAP FOR GRAY TO BINARY CODE CONVERTER:

LOGIC DIAGRAM:

****************************************************************************
BCD to Excess-3 (or) Excess-3 to BCD:
Since each code uses four bits to represent a decimal digit, there must be four inputs and
four output variables. Four binary variables have sixteen different input combinations, only ten
of the input combinations are listed in the truth table. The six bit combinations not listed for the
input variables are don’t care combination. For BCD to Excess-3, the input variable are
designated as B3,B2,B1,B0 and the output variables are designated as X3,X2,X1,X0 in the truth
table. The Boolean functions are obtained from K-Map for each output variable.

Boolean Expression for BCD to Excess-3 Code Conversion:

X3=B0B2+B1B2+B3 X =B⊕B X =B

X2=B0B2+B1B2+B0B1B2
1 1 0 0 0

PROCEDURE:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table
4. For all input combinations the outputs are verified with the truth table.
 BCD TOEXCESS-3 CODE CONVERTER:
TRUTH TABLE:
Binary Excess-3 Code Output
Input
B B2 B B E3 E2 E1 E0
3 1 0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

K-MAP FOR BCD TO EXCESS-3CODECONVERTER:

K-Map for E3: K-Map for E2

E3=B3+B2(B0+B1)
K-Map for E1: K-Map for E0:

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTER:
TRUTH TABLE:

Excess-3 Input Binary Code Output

E3 E2 E1 E B3 B2 B1 B0
0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-MAP FOR EXCESS-3TOBCDCODECONVERTER:

K-Map for B0 K-Map for B1

B0=X0’ B1=X1⊕X0

K-Map for B2 K-Map for B3

B2=X2’X0’+X2’X1’+X2X1X0 B3=X3X1X0+X3X2
***************************************************************
RESULT:
Thus the Binary to Gray code converter, Gray to Binary code converter, BCD to
Excess-3 code converter and Excess-3 to BCD code converter was designed and implemented.
LOGIC DIAGRAM:
4- BIT BINARY ADDER:

4- BIT BINARY SUBTRACTOR:

Expt. No.: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER/ SUBTRAC

Date:

AIM:
To design and implement a 4-bit adder/ subtractor and BCD adder using IC7483.

APPARATUS REQUIRED:

Sl.N Name of the Specificati Quantit

o. Apparatus on y
1. IC IC7483 1
2. EX-OR Gate IC7486 1
3. NOT Gate IC7404 1
3. IC Trainer Kit - 1
4. Patch Cords - As
Required

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. Itcan be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain.The augends bits of
‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits.The carries are connected in chain through the full
adder. The input carry to the adder is C0 and it ripples through the full adder to the
outputcarryC4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0,the circuit is an
adder circuit. When M=1 ,it becomes a subtractor.
4-BIT BINARY ADDER/SUBTRACTOR:

TRUTH TABLE:
Input DataA Input DataB Addition Subtraction
A A A A B B B B C S S S S B D D D D
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be
represented in BCD and should appear in the form listed in the columns.

ABCD adder that adds 2 BCD digits and produces a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.

PIN DIAGRAM FOR IC 7483:

PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table.
3. Observe the logical output and verify with the truth tables.

.
LOGIC DIAGRAM:
BCD ADDER:

K-Map

Y=S4(S3 +S2)
TRUTH TABLE:

Input Data A Input Data B BCD output

A A A A B B B B Car S S S S
4 3 2 1 4 3 2 1 ry 4 3 2 1
1 0 0 0 0 0 1 0 1 0 0 0 0

1 0 0 0 1 0 0 0 1 0 1 1 0

1 0 0 1 1 0 0 1 1 1 0 0 0

0 1 1 1 0 0 0 1 0 1 0 0 0
 RESULT:

Thus the 4-bit adder subtractor and BCD adder using IC7483 was designed and implemented
 PIN DIAGRAM:IC7411
BLOCK
DIAGRAM:4:1
MULTIPLEXER:

FUNCTION TABLE:

S S INPUTSY
1 0

0 0 D0→D0S1'S0'
0 1 D1→D1S1'S0
1 0 D2→D2S1S0'
1 1 D3→D3S1S0

Y=D0S1'S0'+D1S1'S0+D2S1S0'+D3S1S0

LOGIC DIAGRAM FOR MULTIPLEXER:

Expt. No.: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEX

Date:

AIM:
To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:

Sl.N Name of the Apparatus Specificati Quantity

o. on
1 3I/P AND Gate IC 7411 2
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 Digital IC Trainer Kit - 1
5 Patch Cords - As
Required

THEORY:
MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and direct sit to a single output line. The selection of
a particular input line is controlled by a set of selection lines. Normally there are 2ninput line
and selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information

from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as a demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
Data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
TRUTH TABLE:
Selection Inp
Lines ut Y=OUTPUT
S0 S1 D D D D
0 1 2 3

0 0 1 0 0 0 1 (D0)
0 1 0 1 0 0 1 (D1)
1 0 0 0 1 0 1 (D2)
1 1 0 0 0 1 1 (D3)

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S S INPUT
0 0 X→D0=XS1'S0'
0 1 X→D1=XS1'S0
1 0 X→D2=XS1S0'
1 1 X→D3=XS1S0
Y=XS1'S0'+XS1'S0+XS1S0'+XS1S0LOGIC

DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INP OUTP
UT UT
S S I/ D0 D D D
1 0 P 1 2 3

0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer using logic gates was designed and
implemented.
LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:
INP OUTPUT
UT
Y1 Y Y Y4 Y Y Y7 A B C
2 3 5 6

1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
Expt. No.: DESIGN AND IMPLEMENTATION OFENCODER AND DECODER
Date:

AIM:
To design and implement encoders and decoders using logic gates.
APPARATUS REQUIRED:
Sl.N Name of the Apparatus Specificati Quantity
o. on
1 3I/P NAND Gate IC 7410 2
2 OR Gate IC 7432 3
3 NOT Gate IC 7404 1
4 Digital IC Trainer Kit - 1
5 Patch Cords - As
Required

THEORY:
ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generate the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three outputs that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguity that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different.The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e. there is one to one mapping that can be expressed in the truth table. In the block diagram of
the decoder circuit the encoded information is present as an input producing 2n possible outputs.
2n output values are from 0 through out 2n– 1.
LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INP OUTP
UT UT
E A B D0 D D D
1 2 3

1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

RESULT:
Thus the coders are designed and truth tables are verified.
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CL Q Q Q Q
K D C B A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0
9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1
14 1 1 1 0

15 1 1 1 1
AIM:
To design and verify 4 bit ripple counter mod10/mod 12 ripple counter.

APPARATUS REQUIRED:
Sl.N Name of the Specificati Quantity
o. Apparatus on
1 JK Flip Flop IC 7476 2
2 NAND Gate IC 7400 1
3 IC Trainer Kit 1
4 Patch Cards As
Required

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
Are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q’ output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time all
flip flops are not activated at same time which results in asynchronous operation.

PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR MOD-10 RIPPLE COUNTER:

TRUTH TABLE:

CL QD Q Q Q
K C B A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0
PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
LOGIC DIAGRAM FOR MOD-12 RIPPLE COUNTER:

TRUTH TABLE:

CL QD Q Q Q
K C B A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 0 0 0 0
RESULT:
Thus the 4 bit ripple counter mod10/mod 12 ripple counters was implemented and the truth
table was verified.
 Characteristics Table: Excitation Table-JK FlipFlop:

Qn Qn+1 J K
Q Qn+ J K
n
1 0 0 0 X
0 0 0 X 0 1 1 X
0 1 1 X 1 0 X 1
1 0 X 1 1 1 X 0
1 1 0

STATEDIAGRAM:

LOGIC DIAGRAM:
Expt. No.: DESIGN AND IMPLEMENTATION OF 3 BIT
Date: SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counters.

APPARATUS REQUIRED:

Sl.No. Name of the Specificati Quantity

Apparatus on
1 JK Flip Flop IC 7476 2
.
2 OR Gate IC 7432 1
.
3 X OR Gate IC 7486 1
.
4 NOT Gate IC 7404 1
.
5 IC Trainer Kit - 1
.
6 Patch Cards - As
. Required

THEORY:

A counter is a register capable of counting the number of clock pulses arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down counter is one
that is capable of progressing in increasing order or decreasing order through a certain
sequence. A counter that advances upward through its sequence (0, 1, 2, 3...0, 1….) is called up
counter. A counter that decrement downward through its sequence (3, 2, 1, 0, 3, 2 …..) is called
down counter. An up/down counter is also called bidirectional counter. Usually the up/down
operation of the counter is controlled by an up/down signal. When this signal is high, the
counter goes through up sequence and when up/down signal is low counter follows reverse
sequence.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
TRUTH TABLE:

Input Present Next State A B C

Up/ StateQA QA+1QB+1QC+1 JA KA JB KB JC KC
Down QB
QC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
RESULT:

Thus the 3 bit synchronous up/down counter was designed and implemented.