Electrostatic Discharge (ESD)

Introduction
• There is a growing interest in the effects of ESD on the performance of semiconductor
integrated circuits (ICs) because of the impact ESD has on production yields and
product quality.
• ESD problems are increasing in the electronics industry because of the trends toward
higher speed and smaller device sizes.

What is ESD?
• Static charge is an unbalanced electrical charge at rest. Typically, it is created
by insulator surfaces rubbing together or pulling apart. One surface gains
electrons, while the other surface loses electrons. This results in an
unbalanced electrical condition known as static charge.
• When a static charge moves from one surface to another, it becomes ESD.
ESD is a miniature lightning bolt of charge that moves between two surfaces
that have different potentials. It can occur only when the voltage differential
between the two surfaces is sufficiently high to break down the dielectric
strength of the medium separating the two surfaces.
• When a static charge moves, it becomes a current that damages or destroys
gate oxide, metallization, and junctions. ESD can occur in any one of four
different ways: a charged body can touch an IC, a charged IC can touch a
grounded surface, a charged machine can touch an IC, or an electrostatic field
can induce a voltage across a dielectric sufficient to break it down.
 ESD Protection
• Electrostatic discharge is one of the most prevalent causes for chip failures in both
chip manufacturing and field operation.
• ESD can have serious detrimental effects on all semiconductor ICs and the system
that contains them. Standards are developed to enhance the quality and reliability of
ICs by ensuring all devices employed have undergone proper ESD design and
testing, thereby, minimizing the detrimental effects of ESD.
• We have different models for ESD testing, namely
1.The human body model (HBM). 2.The machine model (MM).
3.The charged device model (CDM).
The human body model (HBM):
• A human walking across synthetic carpet in 80% relative humidity can potentially
induce 1.5 kV of static voltage stress.
• In the HBM (.MIL-STD-883C, Method 3015,1988) a touch of a charged person's
finger is simulated by discharging a 100-pF capacitor through a 1.5-kΩ resistor.
• It is important that some protection network be designed into the I/O circuits of the
chip so that the ESD effect can be filtered out before its propagation to the internal
logic circuit. Effective protection networks can withstand as high as 8-kV HBM
ESD stress.
 ESD Protection
2.The machine model (MM):
• In addition to human handling, contact with other machines can also cause
ESD stress. Since body resistance is absent, the stress can be more severe with
higher current levels.
3.The charged device model (CDM):
• It is intended to model the
discharge of the packaged
integrated circuits. (a) Human body model (b) Machine model
• The charge can be accumulated either during the chip assembly process or in
the shipping tubes. The CDM ESD testers electrically charge the device under
test (DUT) and then discharge it to ground, thus probing the high short-duration
current pulse to DUT.

(c) charged device model for ESD

Simplified lumped-element model of HBM-ESD
and MM-ESD testers
 The protection network
• The protection network (PN) usually consists of a diffused resistor-diode
structure. The input resistance is normally between 1 and 3 kΩ. This resistance
in conjunction with the capacitances in diffusion, diodes, and gate capacitance
in input transistors integrates and clamps the voltage to a safe level.
• In essence, the diodes clamp the signal level within a certain voltage range, in
order to minimize the impact of ESD. -0.7 V<VA <VDD+.7 V.

ESD protection network example.

 The protection network
• In order not to permanently, damage the diode structure, the current through the
diode should be limited to less than several tens of milliamperes. Past attempts
to use polysilicon series resistors failed due to dielectric breakdown under high
electric fields.
• The use of additional thick-oxide nMOS transistors as shown in Fig.b has
proven to be very effective and yielded protection in excess of 3 kV in the
HBM-ESD test.
• In this circuit, MI is a thick-oxide punch-through device, M2 is a thick-oxide
nMOS transistor, and M3 is a thin-oxide nMOS transistor operating in saturation
mode. For positive input transients, Ml and M2 have threshold values of 20 to
30 V.

Protection network with thick-oxide transistor.

 Input Circuits
• A simple input circuit consisting of a transmission gate activated by an enable
(E) signal and its complement.
• The incoming signal A is fed into the transmission gate through the protection
network (PN) from the bonding pad of the chip. The enable signal is generated
on-chip and controls the gating of the input signal as X=A, when E=0 and
X = high-impedance state, otherwise

Input series transmission gate circuit symbolic representation

 Input Circuits

Inverting input circuit with (a) protection network, and (b) symbolic view.

(a) Non-inverting TTL level-shifting circuit and (b) its symbolic view.

(a) Input pad circuit with Schmitt trigger and (b) its symbolic view.
 Output Circuits and L(dI/dt) Noise
• The output circuits of VLSI chips are designed to be tristableThe circuit
implementation fig(b) requires more transistors (12 transistors) than the circui t
implementation fig(c), in which only four transistors are required if polarity is
ignored.
 Output Circuits and L(dI/dt) Noise
• In terms of silicon area, the implementation in fig(b) may require less than the
circuit in fig(c) since the last-stage transistors have to be sized large to provide
sufficient current sinking and sourcing capability and also to reduce delay times.
Unfortunately, such a requirement demands a high rate of change in the current di/dt
and can cause significant on-chip noise problems due to the L(di/dt) drop across the
bonding wire connecting the output pad to the package.
An interesting circuit technique for reducing di/dt is shown in Fig.This circuit requires
an additional strobe signal and hence, complicates the timing design, but reduces the
magnitude of di/dt significantly.
• The role of two nMOS transistors controlled by the strobe signal (ST) is to
precharge the gate potentials of the last-stage driver transistors at an approximate
midpoint between the initial and final potentials of the load capacitor.

Circuit structure for

reducing (di/dt) noise.
 On-Chip Clock Generation and Distribution
• Clock signals are the heartbeats of digital systems. Hence, the stability of clock
signals is highly important. Ideally, clock signals should have minimum rise and
fall times, specified duty cycles, and zero skew. In reality, clock signals have
nonzero skews and noticeable rise and fall times; duty cycles can also vary. In
fact, as much as 10% of a machine cycle time is expended to allow realistic
clock skews in large computer systems. The problem is no less serious in VLSI
chip design.
• A simple technique for on-chip generation of a primary clock signal would be to
use a ring oscillator Such a clock circuit has been used in low-end
microprocessor chips
• The generated clock signal can be quite process-dependent and unstable. ,
separate clock chips which use crystal oscillators have been used for high
performance VLSI chip families.
 • The circuit schematic of a Pierce crystal oscillator with good frequency
stability. This circuit is a near series-resonant circuit in which the crystal sees a
low load impedance across its terminals. Series resonance exists in the crystal
but its internal series resistance largely the determines the oscillation frequency.
In its equivalent circuit model, the crystal can be represented as a series RLC
circuit; thus, the higher the series resistance, the lower the oscillation
frequency.
• The external load at the terminals of the crystal also has a considerable effect
on the frequency and the frequency stability. The inverter across the crystal
provides the necessary voltage differential, and the external inverter provides
the amplification to drive clock loads..

A simple circuit that generates a Circuit diagram of a Pierce

pair of non-overlapping clock symbolic representation crystal oscillator circuit.
signals from CK.
 On-Chip Clock Generation and Distribution
• General layout of an H-tree clock distribution
network.

Three-level buffered clock

distribution network.
Genaral structure of the clock distribution network used in DEC
Alpha microprocessor
chips.
 Fault Types and Models
Examples of physical defects include:
• Defects in silicon substrate
• Photolithographic defects
• Mask contamination and scratches
• Process variations and abnormalities
• Oxide defects
The physical defects can cause electrical faults and logical faults. The electrical faults
include:
• Shorts (bridging faults)
• Opens
• Transistor stuck-on, stuck-open
• Resistive shorts and opens
• Excessive change in threshold voltage
• Excessive steady-state currents
The electrical faults in turn can be translated into logical faults. The logicalfaults
include:
• Logical stuck-at-0 or stuck-at-I
• Slower transition (delay fault)
• AND-bridging, OR-bridging
 Design For Testability
Controllability and Observability:
• The controllability: The controllability of a circuit is a measure of the ease (or
difficulty) with which the controller (test engineer) can establish a specific
signal value at each node by setting values at the circuit input terminals.
• The observability :The observability is a measure of the ease (or difficulty)
with which one can determine the signal value at any logic node in the circuit
by controlling its primary input and observing the primary output. Here the
term primary refers to the I/O boundary of the circuit under test.
• The degree of controllability and observability and, thus, the degree of
testability of a circuit, can be measured with respect to whether test vectors are
generated deterministically or randomly.
• There are deterministic procedures for test generation for combinational
circuits, such as the D-algorithm which uses a recursive search procedure
advancing one gate at a time and backtracking, if necessary, until all the faults
are detected. The D-algorithm. requires a large amount of computer time.
• To overcome such shortcomings, many improved algorithms such as
Path-Oriented DEcision Making (PODEM) and FAN-out-oriented test
generation (FAN) have been introduced, Sequential circuit test generation is
several orders of magnitude more difficult than these algorithms.
 Ad Hoc Testable Design Techniques
• One way to increase the testability is to make nodes more accessible at some
cost by physically inserting more access circuits to the original design. We have
different types of techniques
Partition-and-Mux Technique:
• Since the sequence of many serial gates, functional blocks, or large circuits are
difficult to test, such circuits can be partitioned and multiplexors (muxes) can be
inserted such that some of the primary inputs can be fed to partitioned parts
through multiplexers with accessible control signals. With this design technique,
the number of accessible nodes can be increased and the number of test patterns
can be reduced.
Initialize Sequential Circuit:
• When the sequential circuit is powered up, its initial state can be a random,
unknown state. In this case, it is not possible to start the test sequence correctly.
The state of a sequential circuit can be brought to a known state through
initialization.
• In many designs, the initialization can be easily done by connecting
asynchronous preset or clear-input signals from primary or controllable inputs to
flip-flops or latches.
Disable Internal Oscillators and Clocks:
• To avoid synchronization problems during testing, internal oscillators and
clocks should be disabled.
 Ad Hoc Testable Design Techniques
Avoid Asynchronous Logic and Redundant Logic:
• The speed of an asynchronous logic circuit can be faster than that of the
synchronous logic circuit counterpart. However, the design and test of an
asynchronous logic circuit are more difficult than for a synchronous logic
circuit, and its state transition times are difficult to predict. Also, the operation
of an asynchronous logic circuit is sensitive to input test patterns, often causing
race problems and hazards of having momentary signal values opposite to the
expected values.
• Sometimes, designed-in logic redundancy is used to mask a static hazard
condition for reliability. However, the redundant node cannot be observed since
the primary output value cannot be made dependent on the value of the
redundant node.
• Although it is unessential to test redundant nodes when they are designed in as
backup parts, either to enhance the circuit reliability or to increase the
fabrication yield, the use. of redundant circuits can make test generation much
more complex and difficult.
Avoid Delay-Dependent Logic:
• Most automatic test pattern generation (ATPG) programs do not include logic
delays to minimize the complexity of the program. As a result, such
delay-dependent logic is viewed as redundant combinational logic,
 Scan-Based Techniques
• The controllability and observability can be enhanced by providing more
accessible logic nodes with use of additional primary input lines and
multiplexors. However, the use of additional I/O pins can be costly not only for
chip fabrication but also for packaging.
• A popular alternative is to use scan registers with both shift and parallel load
capabilities. The scan design technique is a structured approach to design
sequential circuits for testability. The storage cells in registers are used as
observation points,control points, or both. By using the scan design techniques,
the testing of a sequential circuit is reduced to the problem of testing a
combinational circuit.
• In general, a sequential circuit consists of a combinational circuit and some
storage elements. In the scan-based design, the storage elements are connected
to form a long serial shift register, the so-called scan path, by using
multiplexors and a mode (test/normal) control signal,
• In the test mode, the scan-in signal is clocked into the scan path, and the output
of the last stage latch is scanned out. In the normal mode, the scan-in path is
disabled and the circuit functions as a sequential circuit.
 Scan-Based Techniques
The testing sequence is as follows:
• Step 1: Set the mode to test and, let latches accept data from scan-in input,
• Step 2: Verify the scan path by shifting in and out the test data.
• Step 3: Scan in (shift in) the desired state vector into the shift register.
• Step 4: Apply the test pattern to the primary input pins. I : ;
• Step 5: Set the mode to normal and observe the primary outputs of the circuit
after sufficient time for propagation.,
• Step 6: Assert the circuit clock, for one machine cycle to capture the outputs of
the combinational logic into the registers.
• Step 7: Return to test mode; scan out the contents of the registers, and at the
same time scan in the next pattern.
• Step 8: Repeat steps 3-7 until all test patterns are applied.
The storage cells in scan design can be implemented using edge-triggered D
flipflops,master-slave flip-flops, or level-sensitive latches controlled by
complementary clock signals to ensure race-free operation.
An important approach among scan-based designs is the level sensitive scan
design (LSSD), which incorporates both the level sensitivity and the scan path
approach using shift registers.
 Scan-Based Techniques
The level sensitivity is to ensure that the sequential circuit response Is independent of the
transient characteristics of the circuit, such as the component and wire delays. Thus, LSSD
removes hazards and races.
The boundary scan test method is also used for testing printed circuit boards (PCBs)and multichip
modules (MCMs) carrying multiple chips
On the negative side, scan design uses more complex latches, flip-flops, I/O pins, and
interconnect wires and, thus, requires more chip area. The testing time per test pattern is
also increased due to shift time in long registers.
 Built-In Self Test (BIST) Techniques
• In built-in self test (BIST) design, parts of the circuit are used to test the circuit
itself. Online BIST is used to perform the test under normal operation, where
as off-line BIST is used to perform the test off-line. The essential circuit
modules required for BIST include:
1. Pseudo random pattern generator (PRPG)
2.Output response analyzer (ORA)
The implementation of both PRPG and ORA can be done with Linear
Feedback Shift Registers (LFSRs).
Pseudo Random Pattern Generator:
To test the circuit, test patterns first have to be generated either by using a
pseudo random pattern generator, a weighted test generator, an adaptive test
generator, or other means. A pseudo random test generator circuit can use an
LFSR
Built-In Self Test (BIST) Techniques
 Built-In Self Test (BIST) Techniques
Linear Feedback Shift Register as an ORA:
• To reduce the chip area penalty, data compression schemes are used to compare
the compacted test responses instead of the entire raw test data. One of the
popular data compression schemes is the signature analysis, which is based on
the concept of cyclic redundancy checking.
• It uses polynomial division, which divides the polynomial representation of the
test output data by a characteristic polynomial and then finds the remainder as
the signature. The signature is then compared with the expected signature to
determine whether the device under test is faulty.
• It is possible that the output of a faulty circuit can match the output of the
fault-free circuit; thus, the fault can go undetected in the signature analysis.
Such a phenomenon is called aliasing.
 Built-In Self Test (BIST) Techniques
Built-In Logic Block Observer
• The built-in logic block observer (BILBO) register is a form of ORA which
can be used in each cluster of partitioned registers. The BILBO operation
allows monitoring of circuit operation through exclusive-ORing into LFSR at
multiple points, which corresponds to the signature analyzer with multiple
inputs. A basic BILBO circuit is shown in Fig. which allows four different
modes controlled by C0 and C1 signals.