IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

3, MARCH 2008 1059

Cascaded Multilevel Inverter With Regeneration

Capability and Reduced Number of Switches
Pablo Lezana, Member, IEEE, José Rodríguez, Senior Member, IEEE, and Diego A. Oyarzún

Abstract—Multilevel converters are a very interesting alterna-

tive for medium and high power drives. One of the more flexible
topologies of this type is the cascaded multicell converter. This
paper proposes the use of a single-phase reduced cell suitable for
cascaded multilevel converters. This cell uses a reduced single-
phase active rectifier at the input and an H-bridge inverter at
the output side. This topology presents a very good performance,
effectively controlling the waveform of the input current and of
the output voltage and allowing operation in the motoring and re-
generative mode. The results presented in this paper confirm that
this medium voltage inverter effectively eliminates low frequency
input current harmonics at the primary side of the transformer
and operates without problems in regenerative mode.
Index Terms—Multilevel systems, pulsewidth modulated power
converters, regeneration capability.

I. I NTRODUCTION Fig. 1. Control scheme of the proposed cell.

I N THE LAST few years, the necessity of increasing the

power level in industry has sustained the continuous de-
velopment of multilevel converters due to their capability of
number of switches, control issues and their overall perfor-
mance. In Section III a new cell based on a half bridge single-
phase rectifier [10], [11] and a three-level single-phase inverter
handling voltages up to 6.9 kV and power of several megawatts (H-bridge) is presented. The standard control scheme [12], [13]
[1]–[3]. Among different topologies [4], the cascaded multicell is improved to guarantee a very high input power factor at the
[5], [6] inverter has received much attention. primary of the transformer and to prevent voltage imbalance
The original converter proposed in [5] and [6] uses cells with on the capacitors of each cell. A multicell converter using the
diode rectifiers that does not allow a transfer of power from proposed regenerative cell is presented in Section IV and a
the load to the power supply (regeneration). Several loads such special interconnection among the input transformers is used
as laminators and downhill conveyors demand regeneration to ensure the cancellation of low order current harmonics.
capability on the converter. This fact has motivated several Results for a seven-level converter using the proposed cell
researchers to seek alternatives of cascaded topologies with are included in Section V, showing good quality output signals
regeneration capability, which can be done by replacing the while working with a very high input power factor in rectifying
diode bridge with a pulsewidth modulation (PWM) active rec- and regenerative mode.
tifier at the input side [7], obtaining single- and three-phase
regenerative cells [8], [9].
II. C ASCADE M ULTICELL C ONVERTER
The first part of this paper presents a general multicell
converter and a review of different regenerative cells with The cascade multicell converter was introduced in the early
their corresponding advantages and drawbacks, considering the 1990s in [5] and [6]; this topology is based in the series
connection of units known as cells for each output phase, as
shown in Fig. 1.
Manuscript received December 18, 2006; revised November 23, 2007. This
work was supported in part by the Chilean Research Fund (Fondecyt) through Each cell is a structure based on a rectifier fed by an isolated
Grant 1060427, by the postgraduate program given by Fundación Andes under voltage source, a capacitive dc-link and an inverter structure.
Grant C-14055, and by the Universidad Técnica Federico Santa María and The series connection of the inverters of the cells produces a
the Millennium Nucleus on Industrial Electronics and Mechatronics P04048-F
(MIDEPLAN). multilevel voltage (vxN x = a, b, c), which corresponds to the
P. Lezana is with the Departamento de Electricidad, Universidad Técnica addition of the output voltage of each cell
Federico Santa María, 239-0123 Valparaíso, Chile (e-mail: pablo.lezana@
usm.cl).

n
J. Rodríguez is with the Departamento de Electrónica, Universidad Técnica vxN = vxy , x = a, b, c. (1)
Federico Santa María, 239-0123 Valparaíso, Chile (e-mail: jose.rodriguez@
y=1
usm.cl).
D. A. Oyarzún is with the Hamilton Institute, National University of Ireland,
Maynooth, Ireland (e-mail: [email protected]). The cell structure proposed in [6] is based on a three-
Digital Object Identifier 10.1109/TIE.2008.917095 phase diode bridge, one dc-link capacitor and a single-phase

0278-0046/$25.00 © 2008 IEEE

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1060 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008

Fig. 2. Cell topologies: (a) Non-Regenerative; Regenerative with: (b) Single-phase PWM Rectifier; (c) three-phase PWM Rectifier.

Fig. 3. Power circuit of the proposed cell. Fig. 4. Rectifier behavior when: (a) T1 = 1; (b) T2 = 1.

three-level inverter (or H-bridge) as shown in Fig. 2(a). This

topology needs a complex input transformer to reduce low order Because the input rectifier topology naturally doubles the
harmonics and, due to the diode bridge, cannot reverse the dc-link output voltage for a dc-link voltage of vdc , the input
power flux from the load to the supply. voltage source value must be lower than vdc /2 for a proper
In [8] the authors propose the use of PWM rectifiers as the operation of the rectifier. If the proposed cell is compared with
front-end of the cells for applications that require regeneration an H-H cell [8] with the same total dc-link voltage, the input
capability, and a single-phase PWM-rectifier similar to that current is must be doubled to maintain the same cell power
shown in Fig. 2(b) is used. This cell, known as an H-H cell, rating. For this reason the insulated gate bipolar transistors
requires a simpler transformer than the one shown in Fig. 2(a) (IGBTs) on the rectifier side must be rated at the same voltage
and can reach a very high power factor at the input with a (vdc ), but at double the current that the IGBTs require for an
proper input transformer connection. The main drawback of H-bridge rectifier, while the IGBTs of the H-bridge inverter in
this cell is that the dc-link presents ripple at double the input both cells are exactly the same.
voltage frequency (2fs ). Since rotating coordinates also cannot The dc-link has been separated in two dc-link capacitors,
be directly applied to control the input current [14], [15], it must each working at Vdc /2. However, as the capacitors are con-
be controlled in the stationary frame, where the reference for nected in series, their capacitance must be doubled if they are
the control loop is in essence sinusoidal. Under this condition compared with the capacitance of a traditional H-H cell [8] to
proportional–integrative (PI) controllers are not recommended maintain the capacitance seen by the output H-bridge.
since they do not have zero-steady state error [16], [17]. 1) Rectifier Operation: From Fig. 3 it is easy to see that
The cell presented in [9] uses a three-phase PWM rectifier as T1 and T2 must work in complementary mode, otherwise the
shown in Fig. 2(c) and requires ten semiconductors, an extra dc-link would be short-circuited or the input inductance L
current sensor and a more complex transformer. However, it would be open-circuited. Thus, only two conduction possibil-
does not present pulsating power at double the input frequency, ities are allowed for the rectifier: T1 = 1, T2 = 0 or T1 = 0,
allowing a reduction in the size of the dc-link capacitor. Another T2 = 1. Both conduction states are shown in Fig. 4(a) and (b),
important advantage is that the currents can be controlled in dq respectively, where the Z impedance represents the effect of the
rotating frame. H-bridge inverter.
Note that for a correct operation it is assumed that the
dc-link voltage on each capacitor is always greater than the in-
III. P ROPOSED C ELL put voltage vs . Under this assumption the following expression
A. Topology Description can be obtained.

The proposed cell, which is shown in Fig. 3, only requires 1) T1 = 1: From Fig. 4(a) it can be seen that
two power semiconductors for the rectification stage and four
for the classic H-bridge. Thus, the complete cell can be imple- dis
vL = L = vs − vdc1 . (2)
mented in a standard six-pack inverter module. dt

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LEZANA et al.: INVERTER WITH REGENERATION CAPABILITY AND REDUCED NUMBER OF SWITCHES 1061

Fig. 5. H-bridge inverter output voltage: (a) vab = vdc ; (b) vab = −vdc ; (c) and (d) vab = 0.

As vdc1 > vs , (2) implies that vL is always negative, so is

decreases its value. Hence, the capacitor currents are

ic1 = is − il (3)
ic2 = − il (4)
 Fig. 6. Control scheme of the proposed cell.
1
vdc1 = ic1 (τ ) dτ (5)
C1

1
vdc2 = ic2 (τ ) dτ (6)
C2

if is > 0, C1 can (depending on the value of il ) be charged

by the mains, otherwise if is < 0, the voltage in C1
will decrease its value. The voltage in C2 will depend
exclusively on the load condition.
2) T1 = 0: As seen in Fig. 4(b), (2) changes to Fig. 7. Average model of the PWM rectifier: (a) Circuit; (b) PWM modulator.

dis
vL = L = vs + vdc2 (7)
dt is used for Cc to provide perfect phase tracking on the current
loop at that frequency [16], [17].
due to vdc2 > vs , vL > 0 so is increases its value. In this way Cv and Cc structures are
Under this condition, (3) and (4) change to
s + αv
Cv = Kv (10)
ic1 = − il (8) s
2
s + αc s + βc
ic2 = − is − il . (9) Cc = Kc (11)
s2 − ωs2
If is > 0 the capacitor C2 will be discharged, otherwise if
is < 0, the voltage in C2 can increase its value. As in the previ- where Kv , αv , Kc , αc , and βc are calculated depending on the
ous section, the voltage in C1 depends on the load condition. desired bandwidth, overshoot and settling time.
The control scheme must adjust the duty cycle to keep the Working with a sinusoidal input current of frequency fs in
voltages vdc1 and vdc2 at their reference values. phase with the input voltage has consequences in the dc-link
2) Inverter Unit: Fig. 5 shows the four conduction states for capacitors voltages. A simple way to understand these effects is
an H-bridge inverter. Note that this topology generates up to to use the average rectifier model proposed in [18] and shown in
three different output voltage levels based on the full dc-link Fig. 7, and assume that the voltages are balanced. The following
voltage vdc = vdc1 + vdc2 , disregarding the rectifier topology. relations then hold, according to Fig. 7(b)

1 v∗
B. Control Scheme + r
α= (12)
2 Vdc
The control scheme for the rectifier side of this semireduced 1 v∗
1−α= − r . (13)
cell is shown in Fig. 6. This scheme uses a voltage controller Cv 2 Vdc
to control the entire dc-link voltage vdc and a current controller
Cc that enables a high input power factor. Typically Cv and If the rectifier is working with unitary power factor, vr∗ must
Cc have been chosen as simple PI controllers. However, in this be a sinusoidal signal of frequency fs , and a magnitude and
case a linear resonant controller at mains frequency ωs = 2πfs phase (v̂r and φ, respectively) depending on the load power

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1062 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008

rating and the input impedance, so the instantaneous power on

each capacitor are

pc1 = − vdc1 (1 − α)is

 
1 v̂r∗ sin(ωs t − φ)  
= − vdc1 − îs sin(ωs t)
2 Vdc
 
v̂r∗ îs îs sin(ωs t)
= vdc1 [cos(φ) − cos(2ωs t − φ)] −
2Vdc 2
(14)
pc2 = vdc2 αis
 
v̂r∗ îs îs sin(ωs t)
= vdc2 [cos(φ) − cos(2ωs t − φ)] + .
2Vdc 2
(15)
Fig. 8. Input current and grid voltage with: (a) P unbalance controller,
(b) notch-PI unbalance controller.
Since the main voltage harmonics are the same compared to
the power harmonics in a capacitor, vc1 and vc2 have the same IV. M ULTICELL C ONVERTER W ITH THE P ROPOSED C ELL
harmonics than pc1 and pc2 , respectively, then the entire dc-link
voltage vdc = vc1 + vc2 presents a ripple component at 2ωs but Fig. 9 shows a seven-level multicell converter using the
not at ωs . Since this ripple is a consequence of working with a proposed cell.
high power factor, it cannot be compensated and must thus be Several input currents on each cell are present due to the
ignored by the voltage controller. For this reason a band-stop H-bridge operation. This phenomenon is similar to the one
filter at 2ωs in the vdc measurement is included. described for an H-H cell in [21]. To obtain a proper cancel-
Some research studies [12], [13], [19], have discussed a lation of these harmonics components on the primary side of
voltage imbalance phenomenon between both capacitors due to the transformer, the interconnection proposed in [21] is used.
offsets on the control signals, initial conditions and asymmetry According to Fig. 9 the following relationships holds for the
between both capacitances (typical tolerance is about 20%). secondary voltages:
These studies are focused on a rectifier side identical to the √  π
one proposed in this paper, but with a rather different inverter vs1 = vs4 = vs7 = k 3v̂p sin 2πfs t − (16)
6
topology. In those works the problem is solved by introducing a  
√ π 2π
dc offset in the current reference for the current loop, which vs2 = vs5 = vs8 = k 3v̂p sin 2πfs t − + (17)
6 3
allows movement of the dc-link neutral point to balance the  
capacitors voltage. As stated on the current literature, a simple √ π 2π
vs3 = vs6 = vs9 = k 3v̂p sin 2πfs t − − (18)
proportional (P ) controller should be enough to compensate 6 3
the imbalance. However, according to (14) and (15), it can be
noticed that strong components at fs (in hertz) are present in and for the primary currents
vdc1 and vdc2 . Moreover, as the feedback control signal used 1
is ∆v = vdc1 − vdc2 , and the components at fs (in hertz) in iu = [(is1 + is4 + is7 ) − (is3 + is6 + is9 )] (19)
k
the capacitors are shifted in 180◦ , an amplified fs (in hertz) 1
component is present on the imbalance control path. iv = [(is2 + is5 + is8 ) − (is1 + is4 + is7 )] (20)
k
This component propagates through the P controller and will
1
add spurious phase and magnitude components to ĩs (t). Thus, iw = [(is3 + is6 + is9 ) − (is2 + is5 + is8 )] (21)
k
the current loop will track i∗s (t) instead of ĩs (t), leading to an
undesirable shifted phase input current that degrades the input where k represents the turns ratio of the input transformer. For
power factor. simplicity in this paper it is assumed that k = 1.
A simple solution to this issue is achieved by introducing On the output side, assuming stationary states, the output
a notch filter on the ∆v measurement. The notch filter should voltages and currents are
provide a considerable attenuation at fs (in hertz) to carry the
input power factor near unity. Another well-known drawback of va (t) = î sin(ωo t), ia (t) = î sin(ωo t − φo ) (22)
◦
P controllers is that they cannot warrant zero steady-state error, vb (t) = î sin (ωo t + 120 ) , ib (t) = î sin (ωo t − φo + 120◦ )
even if the plant includes an integrator [20]; a PI controller
(23)
for Cb is recommended. Note that if a low cutoff frequency PI
◦
controller is used, the notch filter can be omitted. Comparison vc (t) = î sin (ωo t − 120 ) , ic (t) = î sin (ωo t − φo − 120◦ )
results using the traditional P controller method and the new (24)
proposed notch-PI controller are shown in Fig. 8, demonstrating
the effectiveness of the proposed scheme. where î and φo will depend on the output impedance.

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LEZANA et al.: INVERTER WITH REGENERATION CAPABILITY AND REDUCED NUMBER OF SWITCHES 1063

Fig. 9. Seven-level multicell converter with the proposed cell.

Under these conditions the output power of each cell can be TABLE I
NET AND LOAD PARAMETERS
calculated, e.g., for cell Ha1

pa1 (t) = va1 (t)ia (t)

v̂a1 î(t)
= [cos(φo ) − cos(2ωo t − φo )] . (25)
2

As cell Ha1 is connected in series with cells Ha2 and Ha3 ,

the output current of these three cells are exactly the same. If
a phase-shifted PWM modulation is then assumed, the funda-
mental output voltage and hence the instantaneous output power
of these cells are the same.
Following the same procedure, the instantaneous output Note that as stated in [21], this cancellation process is only
power for cells Hb1 , Hb2 , and Hb3 is: possible if the number of cells per phase is a multiple of three.

pbx (t) = vbx (t)ib (t) x = 1, 2, 3

V. R ESULTS
v̂bx î
= [cos(φo ) − cos(2ωo t − φo − 120◦ )] (26) For the experimental results, the cells were built using
2
IPM20CSJ060 six-pack modules and two dc-link capacitors
and for cells Hc1 , Hc2 and Hc3 is of 3 mF. The control scheme was implemented in a digital
platform based on a TMS320C6711 DSP, which resolves the
pcx (t) = vcx (t)ic (t), x = 1, 2, 3 control loops and the phase-locked loop (PLL) used for a cor-
v̂cx î rect synchronization with the net and a XC2S150 FPGA, from
= [cos(φo ) − cos(2ωo t − φo + 120◦ )] . (27) Xilinx, which manages the 29 A/D conversions and modulates
2
the actuations calculated by the DSP. The calculation time for
Then the low frequency voltage ripple in the capacitors of one control loop, including the A/D conversion, filters and
cells Ha1 , Hb1 , and Hc1 , due to the output currents, are phase PLL algorithm, was only 9 µs, so a PWM carrier of 2.9 kHz
shifted in 120◦ . As the voltage controllers will try to keep the was used.
capacitors voltage at Vdc , they will introduce harmonics in the The net and load parameters are detailed in Table I.
input currents. These harmonics on the different cells will be The pulsating power generated by the output H-bridges
phase-shifted in 120◦ as well. The same analysis can be done increases its importance while the output frequency decreases.
for Ha2 − Hb2 − Hc2 and Ha3 − Hb3 − Hc3 , obtaining input This can be seen in the simulated and experimental results of
current harmonics phase-shifted in 120◦ between the cells; Figs. 10 and 11, respectively, where the converter is operated
by using the relationships (19)–(21) they are canceled in the at fo = 5 Hz. The seven-level output voltages can be clearly
input transformer, leading to an almost unitary input power identified, a low frequency distortion can be noted [Figs. 10(a)
factor. Although this harmonic cancellation is effective at any and 11(a)], and high quality output currents are still obtained
frequency, operation at very low frequencies can saturate the [Figs. 10(b) and 11(b)]. The effect of the low output frequency
input transformer, affecting the process. is clear in the dc-link voltages of the cells as seen in Fig. 11(c),

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1064 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008

Fig. 10. Simulation results working with fo = 5 Hz: (a) Output voltages; Fig. 11. Experimental results working with fo = 5 Hz: (a) Output voltages;
(b) output currents; (c) total dc-link voltage vdc and capacitors voltage vdc1 (b) output currents; (c) total dc-link voltage vdc and capacitors voltage vdc1
and vdc2 ; (d) input voltage and current of one cell. and vdc2 ; (d) input voltage and current of one cell.

by the presence of a low frequency (2fo ) high amplitude

harmonic component in the ripple. The input currents of the
cell appear highly modulated due to the dc-link voltage ripple
trying to compensate it, an effect shown in Figs. 10(d) and
11(d) Note however that the current keeps in phase with the
input secondary voltage, even in those moments when the
inverter operates in regenerative mode (i.e., at t = 50 [ms])
leading the dc-link voltage to its reference value. Also, note
the presence of low order harmonics in the input voltage of
the cells, which appear as additional perturbations to the inner
current control loop.
Fig. 12(a)–(c) shows the input currents of cells Ha1 − Hb1 −
Hc1 . It can be seen how the low order harmonics are phase-
shifted in 120◦ , so by using the relationships (19)–(21), these
harmonics can be dramatically reduced or even eliminated, as
shown in Fig. 12(d).
This can be seen in a clearer way in Fig. 13, where the spectra
of the input current at the secondary and primary are shown.
Note that the cancellation is not perfect mainly due to two
factors: tolerance of the capacitors on each cell and saturation
and nonlinearities of the input transformer.
Fig. 14 shows the effect of the imbalance control in the
behavior of the dc-link voltages vdc1 and vdc2 . Note that if
the imbalance control is off, the difference between the voltage Fig. 12. Input currents: (a), (b), and (c) of cells with input voltages in phase;
in both capacitors reaches up to 40 V, which can lead to a (d) at primary side.

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LEZANA et al.: INVERTER WITH REGENERATION CAPABILITY AND REDUCED NUMBER OF SWITCHES 1065

Fig. 13. Input current spectra: (a) At secondary side; (b) at primary side.

Fig. 14. Unbalance control at fo 50 Hz when turned on: (a) Voltages of one
cell; (b) input current of one cell. Fig. 15. Regeneration at fo = 50 Hz: (a) dc-link voltage in one cell;
(b) output current; (c) input current and voltage at secondary side; (d) input
voltage and current at primary side.
loss of control capability of the input current. This imbalance
is quickly corrected when the imbalance controller is turned
on. Note however that the entire dc-link voltage vdc remains An additional advantage is that a standard industrial six-
controlled at any time by the main voltage control loop. semiconductor module, used for any conventional two-level
Fig. 15 presents the transition from motoring to generating inverter, can be used to build the entire cell.
operation. From t = 0 to t = 80 ms the input current is sinu- In addition, the control strategy for the rectifier stage keeps
soidal and in phase with the ac voltage (Fig. 15(c) and (d), the balance in the voltage of the dc-link capacitors without
indicating that power is transferred from the three-phase power phase-shift between the input voltage and the fundamental
supply to the load. Starting at t = 80 [ms], an active load frequency of the input current of each cell. The low frequency
changes the polarity of the output current [Fig. 15(b)] and in- input current harmonics of each cell can be effectively elim-
creases the dc-link voltage of the cell [Fig. 15(a)]. This forces inated at the primary side of the input transformer through a
the input current to change its polarity as well (180◦ out of proper interconnection.
phase with respect to the voltage, indicating a regeneration The authors believe that the proposed cell is a good compro-
operation. mise between cost and performance, allowing operation on any
condition at a high input power factor.

VI. C ONCLUSION R EFERENCES

The cell introduced in this paper has a reduced number of [1] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Gago, D. Gonzalez, and
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1066 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008

with energy storage,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1512– Pablo Lezana (S’06–M’07) was born in Temuco,
1521, Oct. 2006. Chile, in 1977. He received the M.Sc. and Ph.D. de-
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José Rodríguez (M’81–SM’94) received the Engi-
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versidad Técnica Federico Santa María, Valparaíso,
H. Kawamoto, “A study of the high performance single-phase UPS,” in
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vol. 2, pp. 1872–1878.
Erlangen, Germany, in 1985.
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Since 1977, he has been a Professor and President
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with the Universidad Técnica Federico Santa María.
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During his sabbatical leave in 1996, he was respon-
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sible for the mining division of the Siemens Cor-
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experience in the mining industry, especially in the application of large drives
[13] Y. Lo, T. Song, and H. Chiu, “Analysis and elimination of voltage im-
like cycloconverter-fed synchronous motors for semiautogenous grinding mills,
balance between the split capacitors in half-bridge boost rectifiers,” IEEE
high power conveyors, controlled drives for shovels and power quality issues.
Trans. Ind. Electron., vol. 49, no. 5, pp. 1175–1177, Oct. 2002.
His research interests are mainly in the area of power electronics and electrical
[14] J. Salaet, S. Alepuz, A. Gilabert, and J. Bordonau, “Comparison be-
drives. In the last years, his main research interests are in multilevel inverters
tween two methods of DQ transformation for single phase converters
and new converter topologies. He has authored and coauthored more than 130
control. Application to a 3-level boost rectifier,” in Proc. IEEE 35th PESC,
refereed journal and conference papers and contributed to one chapter in the
Jun. 2004, vol. 1, pp. 214–220.
Power Electronics Handbook (Academic Press, 2006).
[15] U. A. Miranda, L. G. B. Rolim, and M. Aredes, “A DQ synchronous
reference frame current control for single-phase converters,” in Proc.
IEEE 36th PESC, 2005, pp. 1377–1381.
[16] D. N. Zmood and D. G. Holmes, “Stationary frame current regulation of
PWM inverters with zero steady-state error,” IEEE Trans. Power Elec-
tron., vol. 18, no. 3, pp. 814–822, May 2003.
[17] P. Lezana, C. Silva, J. Rodríguez, and M. Pérez, “Zero-steady-state-error
input-current controller for regenerative multilevel converters based on
single-phase cells,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 733– Diego A. Oyarzún was born in Valdivia, Chile,
740, Apr. 2007. in 1982. He received the B.Sc. and M.Sc. degrees
[18] R. Tymerski, V. Vorpérian, F. Lee, and W. Baumann, “Nonlinear modeling in electronic engineering from Universidad Técnica
of the PWM switch,” IEEE Trans. Power Electron., vol. 4, no. 2, pp. 225– Federico Santa María (UTFSM), Valparaiso, Chile,
233, Apr. 1989. in 2003 and 2006, respectively. Since 2007, he has
[19] D. Lee and Y. Kim, “Control of single-phase-to-three-phase AC/DC/AC been currently working toward the Ph.D. degree with
PWM converters for induction motor drives,” IEEE Trans. Ind. Electron., the Systems Biology Group at the Hamilton Institute,
vol. 54, no. 2, pp. 797–804, Apr. 2007. National University of Ireland, Maynooth, Ireland.
[20] G. Goodwing, S. Graebe, and M. Salgado, Control System Design. During 2006, he was employed as a Research
Englewood Cliffs, NJ: Prentice-Hall, 2000. Assistant with UTFSM. His main research interests
[21] J. Rodríguez, P. Lezana, J. Espinoza, M. Pérez, and J. Pontt, “Input current include the understanding of biological processes
harmonics in a regenerative multi-cell inverter with single-phase active through dynamical systems and control theoretical analysis, optimal control
rectifiers,” in Proc. Rec. 28th Annu. Conf. IEEE IECON, Sevilla, España, theory, metabolic and signal transduction pathway modeling and multivariate
Nov. 5–8, 2002, pp. 932–937. control theory.

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