124 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO.

2, JUNE 2020

A New CMOS Implementation for Miniaturized

Active RFID Insect Tag and VHF Insect Tracking
Meera Kumari, Student Member, IEEE, and S. M. Rezaul Hasan , Senior Member, IEEE

Abstract—This paper proposes a new circuit design for Very a complete tag weighing 390mg. However, this could not be
High Frequency (VHF) radio telemetry, in order to miniaturize employed to track animals weighing less than 7g. In 2005,
active RFID tags for tracking small insects and bees. It presents the same author and collaborators [3] further miniaturized the
a CMOS insect-tag implementation for generating 150 MHz
burst-mode signaling scheme by employing digital approach tag size to 200mg and employed two discrete BJT devices in
which was not reported before. This design is vastly differ- this active tag design. This lighter tag also reduced the width
ent from many presently available VHF tags which employs (time-window) of the transmitted signal to save power and
analog signal generation and discrete components. The new enabled a breakthrough in tracking large insects like bumble-
telemeter circuit employs a 150MHz voltage-controlled ring bees. However, the challenge still remains in tracking many
oscillator (VCRO) feeding into a cascade of frequency-dividers
whose outputs are combined to generate an extremely low duty- smaller insects such as honey bees, wasps, etc. which are of
cycle (LDC) burst-mode transmission signal to conserve power. immense ecological and economic importance. The current
In addition, it also incorporates digital-code for insect-tag iden- state-of-the-art active tags still prove unsuitable and too heavy
tification, compared to analog methods which employs small a burden for these smaller insects to bear.
frequency shifts from a reference f (∼150MHz) to f+f MHz There have been concerns raised by many authors about
for individual tag identification. In the proposed design the
strength of the modulated carrier signal is employed to track the adverse effects of radio telemetry on the creatures being
the tagged insect location through the triangulation technique. tracked [4]. Also, some researchers claimed that these tags
A design-rule-check (DRC) and pattern-density clean chip-tag changed the behavior of the creature [5] and therefore, the
was designed for an 8-bit identification code at a throughput of data accuracy could not be ascertained. However, further
576b/s, on a 28-nm CMOS process. It occupies an active layout research has determined that the tag deployment did not affect
area of 1600-µm2 and consumes 8.2-µW. The core transmit-
ter employs supply-voltage of 0.6V to conserve power while the the tracking data if the tag weight is 5% or less of the animals’
output drivers uses 1.2V for high transmitted signal strength. weight and 10% or less of the insects’ weight [6]. Hence, the
In addition, the new LDC burst-mode signal generation method tag’s miniaturization is crucial so that it does not affect the
was verified on silicon through measurements on a fabricated insect’s foraging behavior in any way. Conventionally, VHF
test chip using a 130nm CMOS process. This test circuit con- active-tag transmitter designs employ Pierce oscillators, which
sumed a measured average power of only 7.07-µW. This novel
design enables the smallest tag-size (5mm x 5mm x 2.5 mm) and uses a quartz crystal, bipolar transistor and many passive
tag-weight (< 95mg) compared to many recent VHF tags. components. These discrete components and their integration
into printed-circuit-board (PCB) makes the transmitter bulkier.
Index Terms—CMOS circuit design, low duty-cycle, radio
telemetry, VHF RFID, voltage-controlled-ring-oscillator, triangu- There are passive tags [7] available which are small enough
lation method, insect telemetry, frequency shift keying. for the bees to carry, but the tracking range of these pas-
sive tags is hardly 1m which renders them unsuitable for the
insects home-range (∼1km) analysis. Moreover, the present
I. I NTRODUCTION state-of-the-art individual insect-tag identification is based on
ESEARCHERS have been tracking animals and study- the frequency of the signal that it transmits, and this makes the
R ing their movements and behavior remotely by using
VHF radio telemeter circuitry since the 1960s [1]. Since then,
frequency stability of the transmitted signal a prime concern
for the proper operation of the tracking system. Consequently,
there have been many technological developments in the active for detecting a large number of insects, the separation between
radio-tag design depending on the animal size, their behavior, adjacent identification frequencies decreases for any avail-
tag durability etc., but still, the basic design of the tag cir- able VHF identification bandwidth, thus rendering frequency
cuit has not changed much. In 1993, Naef-Daenzer performed stability a more crucial parameter. In addition, these tags expe-
a major task in reducing the telemeter-size [2] by designing rience frequency drift over time as the output voltage of the
tag battery does not stay precisely the same and this could
Manuscript received August 4, 2019; revised December 8, 2019; accepted also interfere in the correct identification of the tagged insect.
January 2, 2020. Date of publication January 9, 2020; date of current version Furthermore, these signals being analog are more sensitive to
May 25, 2020. This work was supported in part by the New Zealand Institute
of Plant & Food Research Ltd., and in part by the Massey Venture Ltd. phase noise and other interferences. All these impediments and
(Corresponding author: S. M. Rezaul Hasan.) drawbacks leads to a need to explore the design of low-power
The authors are with the Center for Research in Analog and VLSI digital CMOS VHF active tags for insect telemetry.
Microsystem Design, Massey University, Auckland 0632, New Zealand
(e-mail: [email protected]). In this paper, a new digital CMOS transmitter circuit
Digital Object Identifier 10.1109/JRFID.2020.2964313 for insect tracking telemeter-tag employing a low duty-cycle
2469-7281 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 125

Fig. 1. An architectural block diagram of the new digital telemeter circuit, consisting of frequency dividers, low duty cycle signal generator, tag code
generator, FSK frequency modulator and output driver. The telemeter is designed for operation at a VHF frequency of 150MHz employing 28nm CMOS
process.

(LDC) burst signal has been proposed. The design has obviated
the need for large passive elements which would otherwise
increase tag area [8]. This tag circuit has been designed to
generate and transmit 8 bit-coded signal bursts after a cer-
tain interval of time. In this methodology, each tag will be
uniquely binary-coded for individual tag identification. These
codes are used by the receiver system to determine the loca-
tion of the particular tagged creature based on the strength
of the modulated carrier wave. The paper also discusses the
VCRO frequency stability and frequency spectrum analysis
of the coded signal. The new digital insect telemeter tag has Fig. 2. The burst signal pulse-interval and the pulse-width for various smallest
commercial active VHF tags and the proposed tag, (a) A2412 (duty-ratio =
been soft-designed on 28nm CMOS to explore the reduction 0.01), (b) the proposed insect-tag (this work), (c) PicoPip, and (d) A2412
in chip-size and power dissipation, and, the digital burst signal (duty-ratio = 0.0037).
generator circuit was verified through experimental fabrication
on 130nm CMOS.
the field and reduces the operational range of the tag [9]. Also,
in [3], it is mentioned that it is difficult to track tags with duty-
II. A RCHITECTURE OF THE N EW D IGITAL I NSECT TAG cycle less than 0.008. However, presently, the lowest duty-ratio
The architectural block diagram of the proposed new digital being used in commercial tag is 0.0037. Hence taking the
insect telemeter design is shown in the Fig. 1. Here, primarily, above into consideration, the duty-ratio of 0.008 was chosen
three functions are being implemented. First, the low duty- which would provide enough operational distance (∼1km) at
cycle (LDC) pulse signal generation, second, the generation low power budget. The duty-ratio, ON-time and the interval
of 8-bit tag identification code and third, the FSK modulation between the burst pulses for the presently available small-
of carrier signal with the 8-bit code for aerial transmission. est active commercial VHF tags and the proposed tag are
The LDC signal controls the synchronized transmission of shown in Fig. 2. There are VHF signals inside each burst
the tag identification code since the codes are generated and square-wave pulse but are not shown in the illustration for
transmitted only when this signal goes high. This is performed simplicity. The Figs. 2(a) and (d) shows the pulse signals
by using it as a shift (strobing) signal in the code generation for the A2412 tag [10] at two different duty-ratios, 0.01 and
circuit. As a result, there is a reduction in the total power 0.0037 respectively; Fig. 2(b) shows the signal of the proposed
dissipation of the telemeter and the battery-life is prolonged. insect-tag, while Fig. 2(c) is the signal of the PicoPip tag [11].
The significance of this LDC signal is further discussed in The figure also shows a comparison of the power being dis-
Section IV. Since for tracking bees, transmitted signal bursts sipated by the tags during the generation of the burst-mode
of around 10ms – 15ms is needed for easy signal detection independent of the duty-ratio. From the comparison table it
by the receivers, and, since the insect/tag location needs to be is evident that the proposed new insect tag design not only
tracked every few seconds, a duty-cycle of around 0.008 is conserves battery-life by employing a very low duty-cycle but
chosen as appropriate for transmission. If the duty-cycle gets in addition consumes 83.7% less power than the next best
too low it creates an issue in the detectability of the signal in A2412 tag during just the burst pulse duration alone.

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126 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO. 2, JUNE 2020

TABLE I
T HE F REQUENCY, T IME -P ERIOD AND P ULSE D URATION OF O UTPUT
S IGNALS F ROM E ACH F REQUENCY D IVIDER (FD) TAPPING P OINT FOR
A 150 MH Z I NPUT T HROUGH A C ASCADE OF 28 F REQUENCY D IVIDERS

Fig. 3. The VCRO in 28nm CMOS for generating the 150MHz reference,
consisting of a voltage-divider bias with connection to control/probe pad and
an inverting-buffer at the output. The resistors employs OP (salicide block)
on p+ poly layers (with sheet resistance of 480 ± 15% /sq.) from the 28nm
analog library.

Another use of this LDC signal is to turn-off the switch-

ing devices when there is no transmission in order to reduce
the average power consumption, and this is performed in the
FSK modulation sub-block. The sub-blocks 1, 2, 3 and 5 in of low duty-cycle signal generation, intermediate signals of
Fig. 1 are employed for the LDC signal generation. various frequencies are created which can be further com-
Sub-block 1: This is a current-starved Voltage Controlled bined to generate other signals in the circuit. One possible
Ring Oscillator (VCRO) which is set to generate the required way to make the design more efficient and cost-effective in
reference VHF frequency say, f0 (150MHz in this case). The terms of power dissipation could be by employing dynamic
output of this oscillator has two purposes. First, to gener- pre-charged latches in the frequency-divider [12, 13] for the
ate the LDC signal and second, to provide the carrier signal first 9 FFs. Through simulation it was verified that after the
for modulation by the identification-code. Fig. 3 shows the 9th FF (f9 = 292kHz), the frequency is not high enough
VCRO circuit in 28nm. Here, 28nm OP-resistor based voltage- for the dynamic latches to hold-on to their states during the
divider provides a bias-voltage which controls the current clock intervals. Hence, static FFs possessing cross-coupled
mirror reflecting the bias current through every inverter in regenerative-feedback needed to be employed for f10 to f28
the ring to set the desired frequency. The voltage division at the lower frequency divided signals to hold the logic states.
node has pad contact for probing/external control option. This In a dynamic sequential circuit the logic state is stored in the
voltage-divider draws an additional current of only 1.6µA output capacitance of the dynamic logic gate which does not
and pumps about 2nA transient current into the gate of the guarantee robust operation at the lower fractional frequencies
control transistors to set the frequency at 150 MHz. The of the VHF input signal. Hence, such a dynamic sequential
use of active CMOS cascodes on a proportional-to-absolute- design aiming further power efficiency will limit the operat-
temperature (PTAT) current for biasing would incur much ing frequency of the tag, and if the VCRO frequency fluctuates
more power dissipation compared to the voltage-divider result- below 150 MHz the tag’s operation could fail. Consequently,
ing in reduced tag/battery life-span. On the other hand, use of robustness being the priority in the proposed insect-tag, all the
the OP-resistors can generate an issue with the process vari- 28 frequency dividers employ static MS-DFFs. Table I shows
ation, as discussed later in the paper, which can however be the signal frequency at each FD tapping point along with its
mitigated by the frequency binning process as employed in time-period and pulse duration. From the table it can be seen
semiconductor manufacturing. that various combinations of tapped intermediate signals could
Sub-block 2: It comprises of 28 “divide-by-2” frequency- be multiplied using AND logic for generating signals of var-
divider (FD) flip-flops (FFs) (a ripple counter). This sub block ious duty-cycles. Here, for the insect telemetry application as
takes the reference VHF signal from the VCRO (in this case discussed, a duty-cycle of around 0.008 is chosen and hence
150 MHz) and successively halves the frequency to eventually signals from f22 to f28 are multiplied to generate the duty cycle
generate a 0.56Hz signal. The counter is implemented using of T22 / 2T28 which is 0.0078 in this case.
falling-edge-triggered master-salve D flip-flops (MS-DFF), Sub-blocks 3, 4 and 5: Sub-block 3 consists of a 6-input
and the (divide-by-2) asynchronous frequency-divider method AND gate, which takes the signals (f23 to f28 ) tapped from
has been employed in order to minimize the total power con- the sub-block 2 and multiplies them to enable two separate
sumption. Use of synchronous frequency divider in this case, down- stream signals. The output is ANDed with f22 (sub-
where the clock frequency is 150 MHz, will have additional block 5) to produce the LDC signal as shown in the Fig. 4.
switching power overhead in toggling the flip-flop states at The LDC signal goes high only when all the signals from f22
every clock cycle. Also, if a regular counter is used to count to f28 are high. It also serves as the SHIFT/LD signal for the
the long duration of signal-“sleep time (Toff )” in creating the code generation circuit (sub-block 6). The sub-block 3 output
low duty-cycle signal it can require additional control logic is separately ANDed with f18 (sub-block 4) to produce a clock
(e.g., reset logic) which will further complicate the design signal (CLK) for the code generation circuit. This choice of
and increase power dissipation. In this divider-chain technique tapped signals results in the duty-cycle of CLK to be double

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 127

Fig. 6. (a) FSK modulation using a 2:1 Mux, where the carrier signals f1
(75MHz) and f0 (150MHz) are multiplied (ANDed) with the LDC signal. For
the code bit “1” f0 is selected while for the code bit “0” f1 is selected. (b) The
0.6V-to-1.2V level-shifter in 28nm CMOS (the first inverter) and final burst-
mode tapered buffer output driver (the last three inverters) with the output
Fig. 4. Generation of the low duty-cycle (LDC) signal using the outputs f22
impedance matched to 50 for the antenna attachment.
to f28 of the clock-divider flip-flops FD 22 to FD 28. The output signal is
high only when all the signals f22 to f28 are high at the same time, otherwise
it is low.
power consumption is reduced by preventing unwanted rapid
switching of the transistors in this block.
Sub-block 8: It consists of the final transmission driver
which is a set of four inverters as shown in the Fig. 6(b).
For power reduction, the telemeter supply-voltage is kept at
0.6V. However, the output driver is designed for 1.2V supply
so that the transmitted signal is sufficiently strong for employ-
ing the triangulation method. Hence, the first inverter in the
driver acts as the level-shifter with wider NMOS compared
Fig. 5. Schematic for the generation of code using PISO shift-register and to the PMOS to translate the voltage from 0.6V to 1.2V. The
a set of 8 wires. Each wire of the 8-bit code is connected to the VDD for
“1” or to the GND for “0”. The flip-flops used in the shift register are the other three inverters constitute a 28nm tapered buffer circuit. In
falling-edge triggered master-slave D-flip-flops. When the SHIFT/LD control order to provide broad-band impedance matching for the pulse
is low the code-bits are loaded, and when it is high the code-bits are shifted transmission we have considered the signal transmission in
for transmission.
driving output “high” and output “low”. The impedance look-
ing towards VDD during pull-up and the impedance looking
that of the LDC signal, so that its pulse arrives beforehand towards the ground during pull down are through PMOS and
and sub-block 6 has enough time to load the hardwired code NMOS switches respectively acting in the triode (resistive)
in the flip-flops before the code shifting occurs. region of operation. Hence, the resistance of the switches in
Sub-block 6: This is the circuit for the generation of the 8- the triode (resistive) region are matched as closely as pos-
bit code for the tag so that 256 unique individual tags could be sible to a 50  characteristic load by adjusting the aspect
assigned. The schematic for this circuit is depicted in Fig. 5. It (width/length) ratio of the transistors. Fig. 6(b) shows the
consists of the parallel-input-serial-output (PISO) shift-register impedance matched last-stage of the output driver along-with
and set of 8 wires from B0 to B7 which are connected to the transistor-sizes. Fig. 7(a) demonstrates FSK modulation
ground for “0” s or to the power supply (VDD) for “1” s to for the code 10001110 and Fig. 7(b) illustrates bursts of the
set the unique (distinct) binary code for each tag. These wires carrier with identification code transmitted between the sleep
are fed to the 2:1 MUX of the PISO shift-register. The CLK intervals.
and SHIFT/LD signals are determined based on the word-
length of the code. Here, for the 8-bit code the LDC signal III. F REQUENCY S TABILITY A NALYSIS
is chosen to be the SHIFT/LD signal, while, the output of the The ring oscillator is one of the simplest and easy to imple-
sub-block 4 is chosen as the CLK. The code is loaded into the ment oscillators. However, in general, the use of free-running
flip-flops when SHIFT/LD is low, and, when SHIFT/LD goes ring oscillator as a clock circuit is restrained due to large
high, at every clock-cycle one bit of the code is transferred to power-supply noise and frequency jitter [15]. Also, due to this
the output. reason a PLL or other control circuitry are implemented along-
Sub-block 7: This block takes the output code from the sub- with the ring-oscillator to stabilize the oscillator frequency.
block 6 and employs it as the base-band signal for carrier This enhancement additionally requires an external reference
modulation, followed by the transmission of the carrier signal. clock which along with the PLL increases the size and the
For this purpose, Frequency-Shift Keying (FSK) modulation power requirement of the composite ring oscillator. In the
technique has been chosen so that the transmitted signal has insect telemeter tag implementation, where power dissipation
maximum power and it could be employed in the triangulation and chip-area are highly constrained, inclusion of PLL (with
technique [14] to find the location of the tag for insect tracking. a few mW of power budget by itself) [16] and other control
This circuit is shown in the Fig. 6(a) where a 2:1 multiplexer circuitry with the ring oscillator is not feasible considering
outputs the carriers f0 and f1 for the transmission of 1s and miniaturization and battery life of the tag. On the other hand,
0s respectively. Before being fed into the MUX, the carriers this insect tag is extremely minute compared to the present-
are first multiplied with the LDC signal so that the modulated day VLSI chips where millions of transistors may be switching
signal is transmitted only when the LDC signal is high, and the simultaneously generating a large Ldi/dt voltage across the

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128 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO. 2, JUNE 2020

Fig. 8. Equivalent lumped element representation of the interconnect path

with the VCRO design which includes parasitic impedances for the pad to
the package pin.

proposed insect transmitter tag, the size of the circuit is many

Fig. 7. (a) FSK modulation for the insect-tag identification code 10001110, orders of magnitude smaller and draws a very small current.
fo (150MHz) and f1 (75MHz) are used for sending 1s and 0s respectively, and, Also, in order to prevent supply noise, separate power sup-
(b) the coded burst-mode signal to be transmitted at the tag antenna with
a Ton of 14ms and Toff of 1.776s. ply is provided for the oscillator circuit which draws only
around 3.6µA dynamic current. At 150 MHz, such minute
current along-with the associated low package parasitic does
power supply rails and hence creating supply noise in the not deteriorate the frequency stability in any significant way.
oscillators. And therefore, as will be seen in the following sub- To analyze the effect of Ldi/dt drop on the oscillator
section, due to the small active-area of the tag and the small frequency, the parasitic impedance of the package components
current drawn by the tag oscillator, the supply noise affecting is modeled and simulated along-with the 5-stage VCRO as
the frequency stability of the ring oscillator will be negligible. shown in the Fig. 8. The package parasitic model is indicated
Moreover, the imbedding of 8-bit code in the transmitted LDC with brown colored lines in the front-end of the oscillator.
signal burst makes the identification process more robust and Here, Ls, Rs, and, Cs1 and Cs2 are the parasitic induc-
slight variation in operating frequency is no longer a major tance, resistance and capacitances of the first and second level
concern. Consequently, at present, the use of the VCRO to interconnections of the package components [18, 19] in the
generate the reference frequency (fo ) is the only viable solution supply-voltage path, with the nominal values of 10 nH, 0.1
for the insect telemeter design. and, 1pF for each capacitance, respectively. The oscillator is
In order to justify the suitability of the ring oscillator as followed by a buffer to drive the rest of the circuit. VDDO is
the reference frequency in the insect telemeter tag design, the the nominal supply-voltage and VDDO1 is the supply-voltage
stability of the ring oscillator is now analyzed with respect which the ring oscillator receives after the interconnect drops.
to the supply noise. Details on the effect of the Process- The buffer inverter has a separate power supply (VDDC ) in iso-
Voltage-Temperature (PVT) variation and its impact on the lation from the VCRO to reduce the switching current drawn
performance of the tag is also provided. from the power supply, VDDO . This distributed power-supply
scheme reduces the Ldi/dt drop effecting the oscillator. Here,
A. Supply Noise the resistive voltage divider (R1, R2) consumes far less power
The running frequency of a ring oscillator is given by. compared to an active (MOS) biasing circuit in generating the
control voltage for the insect-tag oscillator.
1
fos ∼
= (1) Fig. 9 shows the simulated effect of the power-supply noise
2nτ (VDDO1 ) on the oscillator. Here, the topmost signal is the oscillator
Here, n is the odd number of inverter stages, τ is the time output which takes around 12.5 nsec for the oscillation to
delay of individual inverters in the ring oscillator at a given build-up. The second signal from the top shows the di/dt
temperature and supply voltage [17]. VDDO1 is the effective waveform due to the switching of the inverters in the ring
supply voltage seen by the oscillator circuit and τ is a func- oscillator. This has the maximum value of 8k A/sec and cor-
tion of VDDO1 as shown in (1). Hence, ideally, at a particular responds to the maximum Ldi/dt voltage variation of 80µV in
temperature and at a fixed supply-voltage the frequency of the the supply line. The third signal in the figure shows the fluc-
ring oscillator should remain constant. However, due to the tuation in the supply voltage, VDDO1 of the VCRO. Noise is
Ldi/dt reactive-loss [18] in the interconnect path, the effective injected due to the switching of the transistors in the oscilla-
supply-voltage fluctuates and hence changes the time-period, tor circuit. At 600mV of source voltage (VDDO ), the applied
thus, making ring oscillator less reliable as a reference clock. effective supply voltage to the oscillator (VDDO1 ) wiggles
The Ldi/dt drop becomes particularly significant when there around 599.69mV. The bottom most signal in the Fig. 9 illus-
are millions of transistors on a single chip and the transient trates the control voltage of the oscillator which also has
switching current drawn by these devices is quite high and can supply noise superimposed on it.
rise up to 100A [17]. In such a case, the effective supply volt- The effect of the fluctuation in the supply and control volt-
age can vary up to 100mV thus affecting the performance of ages on the frequency jitter of the oscillator is shown in the
the circuit considerably. The supply noise deteriorates even Fig. 10. This is the deviation in the operational frequency
more with increasing operating frequency. However, in the from the average value of the oscillator signal frequency,

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 129

TABLE II
P ERFORMANCE OF THE I NSECT T ELEMETER TAG
AT VARIOUS F REQUENCIES

Fig. 9. Transient waveforms illustrating the build-up of the oscillation and

the effect of supply noise on the supply-line and the control-voltage-line of
the VCRO.

Fig. 10. Frequency jitter of the Ring Oscillator including random noise and
Fig. 11. Normal distribution plot of the oscillator’s frequency with a mean
power supply noise indicating a maximum jitter of around 450kHz.
of 150.8 MHz and a standard deviation of 0.157 MHz.

fa (150.87 MHz in this case). The graph shows that the max-
imum jitter in the VCRO’s frequency, represented as f, is
around 450 kHz. From this frequency jitter, the maximum
period jitter, Tp at 150.87 MHz is determined using (2) below:
1 1
− = Tp (2)
fa fa + f
From the above, the Tp value is found to be around 20 psec for
the time-period of 6.63nsec. Also, the throughput of the code
inside the burst signal is 576b/s which varies around 0.67 %
per MHz change in the oscillator frequency as per the Table II. Fig. 12. Monte Carlo analysis plot showing the effect of mismatch variation
in the resistive voltage divider considering 200 Samples.
At this bit-rate, the 20psec oscillator jitter is extremely low to
influence the performance of the insect-tag.
The effect of this jitter has also been analyzed in terms of the
this graph are 151.12MHz and 0.67MHz respectively. From
normal probability distribution of the oscillator’s frequency.
this plot, it is quite clear that the reference frequency for
From the simulated frequency data, the mean frequency, µ is
99.7% of the tags will be in the range of 149.07MHz to
determined to be 150.8MHz with 0.157MHz standard devi-
153.09MHz. Hence, the voltage-divider resistor-mismatch will
ation (σ ). Fig. 11 shows the normal distribution plot of the
not be a bottle-neck issue in the operation and performance of
oscillator frequency. It can be seen from this plot that due
the insect telemeter. The VCRO control-voltage may also be
to the small 3σ value which is 0.47MHz, 99.7% of the time
adjusted externally (external trimming) using the probe-pad, if
the oscillator’s frequency varies within a very small frequency
at all required.
range of 150.5MHz to 151.2MHz. This confirms that the
power supply noise will not be an issue in this miniaturized
insect-tag design. B. Temperature Variation
Mismatch of the voltage-divider resistors in generating Foraging activity of bees and other insect pollinators nor-
the control-voltage of the VCRO has also been considered. mally occur within an environmental temperature range of
Fig. 12 depicts the Monte Carlo simulation result for 200 sam- 14◦ C to 38◦ C [20, 21]. Hence, to understand the operation of
ples indicating the effect of the resistance mismatch variation the tag in this temperature range, simulations were performed
on the VCRO frequency at the typical-typical (TT) process for temperature variation from 10◦ C to 40◦ C. Fig. 13 shows
corner. The mean frequency and the standard deviation for that in the operational temperature range, the tag’s frequency

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130 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO. 2, JUNE 2020

Fig. 15. Frequency variation for the VCRO (with OP-resistors) at various
process corners, ss (slow-slow), sf (slow-fast), tt (typical-typical), fs (fast-
slow) and ff (fast-fast).
Fig. 13. Simulated frequency drift due to environment temperature varia-
tion. In the operational temperature range, the tag’s frequency varies between
118.43MHz and 185.11MHz.

Fig. 16. Monte Carlo simulation result of sample distribution vs. frequency
for various process corners showing a 55% pass with a mean of 155.09 MHz
for 1000 samples.
Fig. 14. The influence of supply-voltage variation on the oscillator’s
frequency (@ typical-typical process corner and 27◦ C temperature).
during fabrication. This variation has always been a serious
varies between 118.43MHz and 185.11MHz. This is around concern to the designer in the yield of working chips, partic-
2.78MHz change per ◦ C fluctuation in the temperature, and, ularly when the size of the circuit is quite large [22]. To con-
the Table II shows the parameters of the tag in this frequency sider the effect of process variation on the running frequency,
range. From this table, it can be seen that with the change the VCRO in Fig. 3 (with OP-resistors) was simulated at
in environmental temperature, the sleep-time, burst-signal various process corners, Slow-Slow (SS), Slow-Fast (SF),
width and data-rate will vary considerably, but, as long as Typical-Typical (TT), Fast-Slow (FS), and Fast-Fast (FF). The
the frequencies are detectable by the receiver, this will not results are plotted in the Fig. 15. Here, for this oscillator
have any impact on the insect tracking, as the tag identifi- the frequency varies significantly with process variation, but,
cation codes are frequency invariant. This is an additional this variation always has an associated statistical distribu-
benefit of this digitalized telemeter insect-tag over the conven- tion with mean and standard deviation [23]. The TT corner
tional analog-based telemeter where the frequency stability is is essentially the mean of this distribution. Since the size of
stringent and paramount for the correct identification of the the circuit is very small in this insect-tag design, a reason-
individual insects. able yield for this telemeter chip can be delivered [16]. The
yield for this telemeter design is predicted by running the
full Monte-Carlo simulation for 1000 sample points. The tags
C. Voltage Variation
with frequencies in the range 120MHz to 180MHz will be
Fig. 14 depicts the effect of supply-voltage fluctuation on binned for the telemeter application and the rest will be dis-
the oscillator’s frequency at typical-typical process corner and carded. Fig. 16 shows the Monte-Carlo simulation result with
27◦ C ambient temperature. It changes at the rate of 1.3MHz 55% (557/1000) successful yield. The pass range is shown by
per mV change in the supply-voltage. However, as discussed the green shaded region in the figure. The associated mean
in the above Section III-A, due to the skeletal telemeter circuit- frequency and standard deviation are 155MHz and 42MHz
size and isolated power supply-line provided for the oscillator, respectively.
a significant fluctuation in the supply-voltage due to power-
supply noise is not expected. IV. D ESIGN AND S IMULATION R ESULTS
The new insect telemeter circuit was designed and simulated
D. Process Variation in 28-nm Global-Foundries (GF) CMOS process. The chip was
Process variation is the change in the transistor attributes in verified to be DRC and pattern-density clean and cleared man-
terms of width, length, oxide-thickness and threshold-voltage ufacturability checks. The transmitter circuitry occupies only

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 131

Fig. 18. Frequency control-voltage of the VCRO for various process corners.
The tuning range of the oscillator is wide enough to allow appropriate control-
voltage to set the frequency to 150 MHz for each process corner.

Fig. 19. Timing diagram for the PISO shift-register in strobing the insect-tag
identification code 10001110.

Fig. 17. Layout of (a) the transmitter circuit, and, (b) the die with bond pads
including ESD protection cells (available in the 28nm cell library) with each
I/O pad. The zoomed-in view of the fill pattern-density for Rx, poly, n-well The complete transmitter circuit was extensively simulated
and all metal layers is also shown.
using Cadence spectre. Parasitic extracted post-layout simula-
tion was also carried out and performance difference compared
to the pre-layout simulation was found to be insignificant. This
around 1600 µm2 [Fig. 17(a)] while the total chip-size along is because the RC time-constant due to the parasitic capac-
with the bond-pads is 1mm2 [Fig. 17(b)]. A zoomed-in view of itance and the finite (non-negligible) via-resistance is small
the fill pattern-density for Rx, poly, n-well and all metal layers (with the resulting pole at extremely high frequency) com-
is also shown. The I/O pads have electrostatic discharge (ESD) pared to the 150MHz operating frequency of the VCRO in
protection. With such miniaturization, the weight of the silicon this chip. The effect of the parasitics will be more prominent
die will be negligible, and the tag load will be constituted by at much higher radio frequencies. Since the entire circuitry,
the battery, antenna and any packaging. The circuit employs except the output driver, employs 0.6V supply-voltage, the
14 bond-pads as labeled on the die photo. There are 3 power- VCRO is in particular sensitive to process variation [24] which
supply pads, VDDD for the driver circuit, VDDO for the was discussed earlier in Section III-D. To indicate that stable
oscillator and VDDC for the rest of the transmitter circuit. 150MHz oscillation is achievable in all cases, PSS simula-
A DC-DC converter was not implemented at this stage as it tion was further carried out for the VCRO for various process
may require large on-chip inductor as well as extra control corners. Fig. 18 shows the frequency vs. control-voltage plot
circuitry which would increase the chip-size and power dissi- where it can be seen that with process variation the running
pation thus diminishing the tag life-span. An off-chip matched frequency of the oscillator changes considerably. However, the
external wire antenna will be deployed with the fabricated die. tuning range of the oscillator is wide enough to allow the con-
For the chip I/O wire-bond type pads designed on the LB (Last trol voltage to set the frequency to 150MHz in each case. The
metal option) layer in accordance with the 28-nm design-rule control-voltage is set to generate 150MHz for the TT process
are employed. For passivation opening, rectangular shaped box corner (R1 and R2 design point in Fig. 18) but can be varied
were made on the DV level as an overlay over the LB layer. if required through external probe-pad bias.
The bond pads are placed over a metal (M1) ground plane The performance of the circuit is demonstrated for the tag
which is connected to the substrate and the ground pad to code 10001110 in the Fig. 19 showing the timing diagram
prevent any noise from the substrate. for the PISO in strobing the code. Fig. 20 provides all the

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132 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO. 2, JUNE 2020

TABLE III
P OWER B UDGET OF THE T RANSMITTER FOR THE VARIOUS
S UB -B LOCKS IN F IG . 1

to be 4.21742µW. Next, Ps = 0.596 µW is the power con-

sumed by the sub-blocks 6 to 8 during the sleep-state and these
same sub-blocks dissipate comparatively much larger power
of Pt = 434µW during the code generation and transmission
mode. Hence, from (3) the average power consumption, Pavg
for this tag, at 0.0078 duty-ratio (D = 0.0078) can be deter-
mined to be 8.2µW. On the contrary, if the LDC signal was
not used to shut-off these most power consuming sub-blocks
(from 6 to 8), and the consequent code generation and trans-
mission mode is not intermittent (periodic), the total average
Fig. 20. Circuit simulated transient telemeter waveforms for the insect-tag power dissipation (Pavg ) would have been 438µW. There is
identification code 10001110. thus over 50 times reduction in power dissipation due to the
LDC signal, and it enables a 4mAh [25] battery gain 53 times
longer life than a tag design without the LDC signal.
waveform diagrams in the generation of the final burst-mode
low duty-cycle modulated output signal. The circuit simulated
duty cycle comes out to be 0.00785 with the baseband data rate V. E XPERIMENTAL R ESULTS OF L OW-D UTY-C YCLE
of 572.6b/s which is very close to the theoretically desired B URST M ODE I MPLEMENTATION IN 130 NM CMOS
duty-cycle of 0.008. This slight difference in the duty-ratio
In this section, we present the measured verification of
will have marginal effect on the pulse-width and the burst-
the LDC burst-mode signal generation employing the VCRO
interval of the signal and will have no significant impact in
and the FDs. The chip was fabricated using GF 8RFDM
the performance of the tag. Even the difference in the average
130 nm CMOS process technology. Due to limited memory
power dissipation due to this slight variation in the duty-ratio
and simulation duration constrain, the technique to create
will be a meagre 9pW which is quite negligible.
the LDC burst-mode signal was implemented using 13 FDs
The code appears only when the LDC signal is high, that is
and like before 0.0078 duty-ratio was generated by logi-
between the interval T1=1.768s and T2=1.782s as shown in
cally multiplying signals from the last 7 frequency dividers
Fig. 20(a) and in agreement with the PISO strobing waveform
(from f7 to f13 ) as shown in the Fig. 21. Here, the LDC
in Fig. 19. Fig. 20(a) also illustrates the carrier frequency in
signal is directly ANDed with the oscillator signal, f0 to
accordance with the logical values of the baseband signal (tag
obtain the burst signal. This scaled version (using 13 FDs)
identification code). Table III summarizes the average dissipa-
does not include the 8-bit code generation circuit in the sig-
tion by various circuit blocks in the transmitter’s power budget.
nal burst and was implemented to verify the proposed new
The total average power consumed is around 8.2µW at 2pF
methodology to create LDC signal burst. Fig. 22(a) shows
load while only 4.8µW is utilized during sleep mode with the
the chip-photo with 5 bond-pads including the power-supply
rest being attributable to the transmission burst. It is observed
pads, VDD_DRIVER and VDD for the output driver and
that after the 14th FD (flip-flop) the average power of succes-
the rest of the circuitry respectively. The corresponding pads
sive FD remains roughly the same at 16.2nW. This could be
on the chip-photo are also indicated on the block diagram
mainly because at lower frequency static power consumption
of the Fig. 21 using incoming external arrows. The test-
becomes more significant than dynamic power.
setup consisted of TDS2012 Tektronics oscilloscope along
The necessity for the low duty-cycle signal in the proposed
with ESCORT EDM-89S Digital Multimeter. The supply
design could be explained using the following equation,
and control voltages were provided using Regulated Power
Pavg = DPt + (1 − D)Ps + Pc (3) Supply (RPS). The chip (in OCP_QFN_7X7_48A SMT lead-
less package) was mounted in a Yamaichi 0.5mm pitch 48 way
where, D is the duty-ratio, Pavg is the total average power dis- through hole QFN test socket. A PCB was fabricated to mount
sipated by the tag, Pc is the continuous power dissipated by the the test socket and facilitate I/O access for the measure-
sub-blocks 1 to 5 as shown in the Fig. 1, which is measured ments as shown in the Fig. 22(b). The circuit was tested at

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 133

Fig. 21. Scaled version of the LDC burst-mode signaling implemented in

130 nm CMOS process employing 13 FDs, to verify the burst-mode signal
generation technique.

TABLE IV
T HE S IMULATED F REQUENCY, T IME -P ERIOD AND P ULSE D URATION OF
O UTPUT S IGNALS F ROM E ACH F REQUENCY D IVIDER (FD) TAPPING
P OINT FOR A 132MH Z I NPUT (F ROM THE VCRO O UTPUT ) T HROUGH
A C ASCADE OF 13 F REQUENCY D IVIDERS

Fig. 23. (a) Measured 484.5ns wide burst-signal appearing in time-intervals

of 62.3 µs, and, (b) burst-mode waveform at 132 MHz (within the burst signal)
for the fabricated Burst signal generator chip in 130 nm CMOS process.

Fig. 24. (a) Measured probability density distribution function of the

132 MHz burst signal with a standard deviation of 2.8 MHz, (b) noise
superimposed on the measured signal.
Fig. 22. (a) Micrograph of the LDC burst signal generator fabricated in
130nm GF CMOS process, (b) photo of the QFN test socket containing the
packaged chip mounted on PCB.
signal amplitude may be due to the limited bandwidth of the
measuring-probe and the oscilloscope, as well as, the drop
f0 = 132 MHz (in VHF range for the telemeter application) in the interconnect traces. From the experiment, the measured
at 20◦ C ambient temperature. duty-ratio was determined to be 0.0077, which is very close to
This frequency was obtained with VDD and VDD_DRIVER 0.0078, the simulated value. These slight variations in the sig-
set at 600mV and V_CONTROL set at 340mV. Table IV nal burst-width, interval and duty-ratio will not have any effect
shows the signal frequencies tapped from the 13 FDs along in the functional performance of the telemeter. The jitter was
with their time periods and pulse durations. The circuit draws determined from the measured and stored signal (132 MHz)
6.78µA during the sleep-mode and 625µA during the burst data and was calculated to be 212 psec. Fig. 24(a) shows
generation mode with a total of 7.07µW at 0.0078 duty-ratio the probability density distribution function of the measured
(@ VDD = 0.6 V). Fig. 23 shows the measured burst-mode signal frequency data inside the burst-mode with the mean
signal waveform displayed on the digital storage oscilloscope. and standard-deviation of around 132 MHz and 2.8 MHz
In the Fig. 23(a) the measured interval between signal bursts is respectively. Analysis was performed to calculate the noise
62.3µsec with a 484.5nsec burst-width which is very close to superimposed on the measured 132 MHz oscillator signal to
the predicted signal burst interval of 62.1µsec with a 485nsec determine the oscillator’s stability. For this purpose, a 480 mV
burst-width based on the Table IV. Fig. 23(b) shows the (Vp-p) pure 132 MHz sinusoidal signal with 240 mV dc super-
132 MHz signal inside the 484.5 nsec burst with a measured imposed on it (same as the measured burst signal bias) is
signal amplitude of around 480 mV for the 600 mV supply- subtracted from the experimentally obtained 132 MHz sig-
voltage. This difference between the measured and expected nal. The resulting superimposed noise, V, is shown in the

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134 IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION, VOL. 4, NO. 2, JUNE 2020

TABLE V
P ERFORMANCE C OMPARISON OF THE P ROPOSED CMOS VHF I NSECT T ELEMETER TAG W ITH VHF P RIOR -A RTS BASED ON S EVERAL C RITERIA

Fig. 24(b) whose root-mean-square (RMS) value is calculated a much smaller ASIC chip-size compared to the ASIC digital
to be 24 mV. This shows that 99% of the signal power is con- code incorporated in Nano-tag [29] as well as a much smaller
centrated in the 132 MHz fundamental and only 1% power tag weight compared to [3]. For attaching the 10 cm whip-
is distributed among the spurious frequencies. This proves the wire-antenna a bond-wire will be used to first connect from
theoretical prediction in Section III-A, that due to the low the tag-die output-port pad (100µm x 100µm) on the chip
oscillator dynamic current, as well as the low package para- to a metal-pad (with larger spatial dimensions) on the battery
sitics, the supply and the ground noise in the fabricated circuit providing the mechanical support for the chip. The whip wire
is quite negligible and would have no significant effect on antenna will then be attached to this metal-pad resting on the
the oscillator’s stability for this telemeter application. As, dis- battery surface thus completing the connection with the tag-die
cussed earlier this eludes the need of crystal oscillators in transmitter-output.
RFID tag [26]. The verified operation of the LDC burst signal
generation on 130 nm CMOS supports this LDC generation
VII. A NALYSIS OF THE M ODULATED
method on the 28 nm CMOS insect-tag employing 28 FDs.
B URST-M ODE S IGNAL
The frequency spectrum of the transmitted burst is now
VI. P ERFORMANCE C OMPARISON OF THE P ROPOSED VHF analyzed considering here for simplicity a sine-wave approx-
I NSECT T ELEMETER TAG W ITH VHF P RIOR -A RT imation (at the matched external wire antenna output) of the
The complete insect-tag would consist of, a 4 mAH silver- burst-mode modulated carrier signal, f (t) so that,
oxide Sony battery which weighs around 80 mg, a 10 cm long 
V(sin(ω0 t) + 1) for logic 1
thin-wire whip-antenna weighing 3 mg, and the transmitter f (t) = (4)
V(sin(ω1 t) + 1) for logic 0
circuit on 1mm2 silicon-chip weighing under 2mg. Hence, the
total weight of the composite tag consisting of all the com- Here, ω0 and ω1 = ω0 /2 are the two carrier frequencies with V
ponents mounted over the battery along-with glob-top epoxy (half of the peak-to-peak carrier signal) being the amplitude
encapsulation (packaging), is expected to be around 95mg and the DC off-set. The Fourier series analysis of the signal is
or less. This would reduce the VHF tag weight by at least possible because the two carrier signals have common multiple
52% and the volume by 58% of the presently existing small- ω1 and are phase synchronized which allows the signal to
est active 200mg VHF telemeter-tag on PCB [3], and hence, be periodic [27]. The Fourier even-coefficients (an ) and the
achieve the original objective of this work. The comparison odd-coefficients (bn ) of the 8-bit coded signal are derived as
of the new CMOS VHF telemeter in terms of tag weight, follows.
dimensions, average current, frequency, power during signal For each logic “1” at kth
1 bit-position from left to right where
generation and transmission, pulse width, pulse interval, and 0 ≤ k1 < 8:
life span with the previous VHF telemeters is provided in the  
 (K1 +1)T
Table V. The table includes a commercial Nano-tag [28] which 2V 8 2nπ t
an = (sin(ω0 t) + 1) × cos dt (5)
uses a 2.8 mm2 ASIC chip implementing a digital-code for T K1 T T
8
the tag identification and weighs 250mg. This design is 50mg
heavier than the tag in [3] even after some ASIC implementa- When n = 220 , 221 the integral in (5) collapses to,
tion, most likely due the use of discrete oscillator components   nπ   nπ 
8Vω0 T
in addition to the ASIC chip, and hence is not suitable for an = sin × sin (2K 1 + 1) (6)
tracking small insects. The core novelty of this telemeter cir- (Tω0 )2 − (2nπ )2 8 8
cuit lies in the digital low duty-cycle clock generator replacing  (K1 +1)T  
2V 8 2nπ t
the analog signal generator of [3] which enables the ultimate bn = (sin(ω0 t) + 1) × sin dt (7)
T K18 T T
goal of reduced tag weight and size to facilitate tracking of
tiny creatures. In addition, it will transmit digitally coded sig- When n = 220 , 221 the integral in (7) collapses to,
nal allowing a large number of tags to be identified at the
same frequency and will also eliminate the need for a very 4Vω0 T   nπ   nπ 
bn = sin × cos (2K1 + 1) (8)
stable clock for the tag identification. This is achieved with (Tω0 )2 − (2nπ )2 8 8

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KUMARI AND HASAN: NEW CMOS IMPLEMENTATION FOR MINIATURIZED ACTIVE RFID INSECT TAG AND VHF INSECT TRACKING 135

The normalized MATLAB plot of (13) with respect to V

is calculated and shown in Fig. 25 to visualize the relative
strength of an for various frequencies. By looking at the val-
ues of the Fourier coefficients as derived above it can be seen
that maximum power spread is present around the two carrier
frequencies ω0 and ω1 as expected in FSK modulation.

VIII. C ONCLUSION
A digital burst-mode insect radio-telemeter tag employing
a new energy-saving low duty-cycle circuit is presented in this
paper. A DRC and pattern-density clean tag-chip designed in
28nm CMOS also results in reduced size and weight along-
Fig. 25. Plot showing the normalized an (with respect to V) vs. frequency. with better tag identification bandwidth. Detailed PVT analysis
for frequency stability and yield including Monte Carlo anal-
ysis has been carried out. A mathematical analysis of the
For each logic “0” at kth
0 bit-position from left to right where burst-mode signal is also provided. In addition, the proposed
0 ≤ k0 < 8: methodology of LDC burst signal generation has been verified
 (K0 +1)T   by measurements on a fabricated chip in 130 nm CMOS pro-
2V 8 2nπ t
an = (sin(ω1 t) + 1) × cos dt (9) cess. Owing to the small oscillator current, the effect of ground
T K08 T T and supply noise is negligible and does not significantly effect
When n = 220 , 221 the integral in (9) collapses to, the LDC signal stability which makes it quite feasible for the
  nπ   nπ  telemeter application.
4Vω0 T
an =  2 sin × sin (2Ko + 1) (10)
Tω0 8 8 ACKNOWLEDGMENTS
2 − (2nπ )2
 (K0 +1)T   The authors wish to acknowledge MOSIS, USC, for the
2V 8 2nπ t chip fabrication support, and the anonymous reviewers for their
bn = (sin(ω1 t) + 1) × sin dt (11)
T K0 T T comments, which helped improve the quality of the manuscript.
8

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[24] S. Paul et al., “A sub-cm3 energy-harvesting stacked wireless sensor Nanyang Technological University, Singapore, from
node featuring a near-threshold voltage IA-32 microcontroller in 14-nm 1986 to 1988, the Curtin University of Technology,
tri-gate CMOS for always-ON always-sensing applications,” IEEE J. Australia, from 1990 to 1991, and Universiti Sains
Solid-State Circuits, vol. 52, no. 4, pp. 961–971, Apr. 2017. Malaysia, Malaysia, from 1992 to 2000. He held an Associate Professor
[25] Sony SR Micro Battery Available. [Online]. Available: position with University Sains Malaysia, where he was the Coordinator of
https://www.sony.net/Products/MicroBattery/sr/spec.html the Analog and VLSI Research Laboratory. From 2000 to 2004, he was
[26] Y.-H. Kim, Y.-C. Choi, M.-W. Seo, S.-S. Yoo, and H.-J. Yoo, “A CMOS an Associate Professor of microelectronics, integrated circuit design, and
transceiver for a multistandard 13.56-MHz RFID reader SoC,” IEEE VLSI design with the Department of Electrical and Computer Engineering,
Trans. Ind. Electron., vol. 57, no. 5, pp. 1563–1572, May 2010. University of Sharjah, UAE. He currently leads the Analog and VLSI Design
[27] Digital Image Processing—University of Cape Town. [Online]. Research Group, Massey University, New Zealand, where he is serving as
Available: http://www.dip.ee.uct.ac.za/∼nicolls/lectures/eee482f/13_ a Senior Faculty Member in computer engineering. He has authored 78 journal
fsk_2up.pdf and 100 conference papers in the areas of analog, digital, RF, and mixed-signal
[28] Holohil Transmitters. [Online]. Available: https://www.holohil.com/ IC design, MEMS sensors, bioelectronics, and VLSI design. His present areas
transmitters/lb-2x/ of interests include analog integrated circuit and VLSI microsystem design,
[29] Nano Tags. [Online]. Available: http://www.lotek.com/nanotagFW- CMOS MEMS sensors, and biological circuit design. He received the Sharjah
0718.pdf Award for Outstanding Publication in IC Design.

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