Computer Architecture

Single-Cycle Implementation
 Single-Cycle Datapath
PCSrc

0
M
Add U
ALU X
4 Add 1
result
RegWrite Shift
left 2

Instruction [25-21] Read

Read MemWrite
Read register 1
PC data 1
address Instruction [20-16] Read
ALUSrc MemtoReg
register 2 Zero
Instruction 0 Read 0
ALU ALU
[31-0] M Write result Address Read 1
data 2 M
U register data M
Instruction U
Instruction [15-11] X Write U
memory Registers X
1 data X
1 Data
Write 0
memory
RegDst data
16 32
Instruction [15-0] Sign
extend ALU
MemRead
control

Instruction [5-0]
ALUOp

 This datapath supports the following instructions:

 add, sub, and, or, slt, lw, sw, beq
Computer Architecture & Network Lab 2
 Single-Cycle Control

RegDst Select destination register

RegWrite Specify if the destination register is written
ALUSrc Select whether source is register or immediate
ALUOp Specify operation for ALU
MemWrite Specify whether memory is to be written
MemRead Specify whether memory is to be read
MemtoReg Select whether memory or ALU output is used
PCSrc Select whether next PC or computed address is used

Computer Architecture & Network Lab 3

 R-format Instruction Dataflow
 For add, sub, and, or, slt instructions

PCSrc

0
M
Add U
ALU X
4 Add 1
result
RegWrite Shift
left 2

Instruction [25-21] Read

Read MemWrite
Read register 1
PC data 1
address Instruction [20-16] Read
ALUSrc MemtoReg
register 2 Zero
Instruction 0 Read 0
ALU ALU
[31-0] M Write result Address Read 1
data 2 M
U register data M
Instruction U
Instruction [15-11] X Write U
memory Registers X
1 data X
1 Data
Write 0
memory
RegDst data
16 32
Instruction [15-0] Sign
extend ALU
MemRead
control

Instruction [5-0]
ALUOp

Computer Architecture & Network Lab 4

 R-format Instruction Control

 Control signal summary

RegDst 1 to select Rd
RegWrite 1 to enable writing Rd
ALUSrc 0 to select Rt value from register file
ALUOp Dependent on operation (see below)
MemWrite 0 to disable writing memory
MemRead 0 to disable reading memory
MemtoReg 0 to select ALU output to register
PCSrc 0 to select next PC
 ALUOp
add OP (add) and OP (and)
sub OP (sub) or OP (or)
slt OP (slt)

Computer Architecture & Network Lab 5

 I-format Load Instruction Dataflow
 For lw instruction

PCSrc

0
M
Add U
ALU X
4 Add 1
result
RegWrite Shift
left 2

Instruction [25-21] Read

Read MemWrite
Read register 1
PC data 1
address Instruction [20-16] Read
ALUSrc MemtoReg
register 2 Zero
Instruction 0 Read 0
ALU ALU
[31-0] M Write result Address Read 1
data 2 M
U register data M
Instruction U
Instruction [15-11] X Write U
memory Registers X
1 data X
1 Data
Write 0
memory
RegDst data
16 32
Instruction [15-0] Sign
extend ALU
MemRead
control

Instruction [5-0]
ALUOp

Computer Architecture & Network Lab 6

 I-format Load Instruction Control

 Control signal summary

RegDst 0 to select Rt
RegWrite 1 to enable writing Rt
ALUSrc 1 to select immediate field value from instruction
ALUOp add
MemWrite 0 to disable writing memory
MemRead 1 to enable reading memory
MemtoReg 1 to select memory output to register
PCSrc 0 to select next PC

Computer Architecture & Network Lab 7

 I-format Store Instruction Dataflow
 For sw instruction

PCSrc

0
M
Add U
ALU X
4 Add 1
result
RegWrite Shift
left 2

Instruction [25-21] Read

Read MemWrite
Read register 1
PC data 1
address Instruction [20-16] Read
ALUSrc MemtoReg
register 2 Zero
Instruction 0 Read 0
ALU ALU
[31-0] M Write result Address Read 1
data 2 M
U register data M
Instruction U
Instruction [15-11] X Write U
memory Registers X
1 data X
1 Data
Write 0
memory
RegDst data
16 32
Instruction [15-0] Sign
extend ALU
MemRead
control

Instruction [5-0]
ALUOp

Computer Architecture & Network Lab 8

 I-format Store Instruction Control

 Control signal summary

RegDst x (don’t care)
RegWrite 0 to disable writing a register
ALUSrc 1 to select Rt value from register file
ALUOp add
MemWrite 1 to enable writing memory
MemRead 0 to disable reading memory
MemtoReg x (don’t care)
PCSrc 0 to select next PC

Computer Architecture & Network Lab 9

 I-format Branch Instruction Dataflow
 For beq instruction

0
M
Add U
ALU X
4 Add 1
result
RegWrite Shift PCSrc
left 2

Instruction [25-21] Read

Read MemWrite
Read register 1
PC data 1
address Instruction [20-16] Read
ALUSrc MemtoReg
register 2 Zero
Instruction 0 Read 0
ALU ALU
[31-0] M Write result Address Read 1
data 2 M
U register data M
Instruction U
Instruction [15-11] X Write U
memory Registers X
1 data X
1 Data
Write 0
memory
RegDst data
16 32
Instruction [15-0] Sign
extend ALU
MemRead
control

Instruction [5-0]
ALUOp

Computer Architecture & Network Lab 10

 I-format Branch Instruction Control

 Control signal summary

RegDst x (don’t care)
RegWrite 0 to disable writing a register
ALUSrc 0 to select Rt value from register file
ALUOp sub
MemWrite 0 to disable writing memory
MemRead 0 to disable reading memory
MemtoReg x (don’t care)
PCSrc zero

Computer Architecture & Network Lab 11

 Single-Cycle Control Signals Summary

Signal R-fmt I-fmt (lw) I-fmt (sw) I-fmt (beq)

RegDst 1 0 x x
RegWrite 1 1 0 0
ALUSrc 0 1 1 0
ALUOp OP add add sub
MemWrite 0 0 1 0
MemRead 0 1 0 0
MemtoReg 0 1 x x
PCSrc 0 0 0 zero

Computer Architecture & Network Lab 12

More Details on Control Signal Generation

Computer Architecture & Network Lab 13

 Review and Projection

 Single-Cycle implementation is easy

 Control is based solely on the operation (and results!)
− dictates ALU operation
− controls multiplexor selection
− enables/disables storage elements
 Processor signals (control and data) stabilize and then any state
(register and/or memory) change takes place when the clock cycle
ends
 Multi-Cycle implementation explained in the next class
 Instruction processing takes multiple steps, one step per cycle
 Within a given clock cycle, signals stabilize and their local state
change takes place when the clock cycle ends

Computer Architecture & Network Lab 14