Computer Architecture

MIPS Instruction Set Architecture

 Instruction Set Architecture
 An Abstract Data Type
 Objects ≡ Registers & Memory

 Operations ≡ Instructions

 Goal of Instruction Set Architecture Design

 To allow high-performance & low-cost implementations while

satisfying constraints imposed by applications including operating

system and complier

Computer Architecture & Network Lab 2

Instruction Set Architecture as an ADT (Review)
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B

Memory Memory
63 63
··

··
Registers 24 (j 15) Registers 24 (j 15)
(beq r0, r1, 2) (beq r0, r1, 2)
r3 8 23 add r1, r2, r3 r3 8 23
22 (sw r3, 0(r0)) 22 (sw r3, 0(r0))
r2 12 r2 12
21 (lw r2, 1(r0)) 21 (lw r2, 1(r0))
r1 1 r1 20
r0 2 20 (add r1, r2, r3) r0 2 20 (add r1, r2, r3)
··

··
PC 20 PC 21
3 7 3 7
2 2 2 2
1 0 1 0
0 4 0 4

Before Register and Memory After Register and Memory

Computer Architecture & Network Lab 3

Instruction Set Architecture as an ADT (Review)
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B

Memory Memory
63 63
··

··
Registers 24 (j 15) Registers 24 (j 15)
(beq r0, r1, 2) (beq r0, r1, 2)
r3 8 23 lw r2, 1(r0) r3 8 23
22 (sw r3, 0(r0)) 22 (sw r3, 0(r0))
r2 12 r2 7
21 (lw r2, 1(r0)) 21 (lw r2, 1(r0))
r1 20 r1 20
r0 2 20 (add r1, r2, r3) r0 2 20 (add r1, r2, r3)
··

··
PC 21 PC 22
3 7 3 7
2 2 2 2
1 0 1 0
0 4 0 4

Before Register and Memory After Register and Memory

Computer Architecture & Network Lab 4

Instruction Set Architecture as an ADT (Review)
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B

Memory Memory
63 63
··

··
Registers 24 (j 15) Registers 24 (j 15)
(beq r0, r1, 2) (beq r0, r1, 2)
r3 8 23 sw r3, 0(r0) r3 8 23
22 (sw r3, 0(r0)) 22 (sw r3, 0(r0))
r2 7 r2 7
21 (lw r2, 1(r0)) 21 (lw r2, 1(r0))
r1 20 r1 20
r0 2 20 (add r1, r2, r3) r0 2 20 (add r1, r2, r3)
··

··
PC 22 PC 23
3 7 3 7
2 2 2 8
1 0 1 0
0 4 0 4

Before Register and Memory After Register and Memory

Computer Architecture & Network Lab 5

Instruction Set Architecture as an ADT (Review)
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B

Memory Memory
63 63
··

··
Registers 24 (j 15) Registers 24 (j 15)
(beq r0, r1, 2) (beq r0, r1, 2)
r3 8 23 beq r0, r1, 2 r3 8 23
22 (sw r3, 0(r0)) 22 (sw r3, 0(r0))
r2 7 r2 7
21 (lw r2, 1(r0)) 21 (lw r2, 1(r0))
r1 20 r1 20
r0 2 20 (add r1, r2, r3) r0 2 20 (add r1, r2, r3)
··

··
PC 23 PC 24
3 7 3 7
2 8 2 8
1 0 1 0
0 4 0 4

Before Register and Memory After Register and Memory

Computer Architecture & Network Lab 6

Instruction Set Architecture as an ADT (Review)
Assumptions
 8 bit ISA
 # of registers = 4 + PC (Program Counter)
 Memory size = 64B

Memory Memory
63 63
··

··
Registers 24 (j 15) Registers 24 (j 15)
(beq r0, r1, 2) (beq r0, r1, 2)
r3 8 23 j 15 r3 8 23
22 (sw r3, 0(r0)) 22 (sw r3, 0(r0))
r2 7 r2 7
21 (lw r2, 1(r0)) 21 (lw r2, 1(r0))
r1 20 r1 20
r0 0 20 (add r1, r2, r3) r0 0 20 (add r1, r2, r3)
··

··
PC 24 PC 15
3 7 3 7
2 8 2 8
1 0 1 0
0 4 0 4

Before Register and Memory After Register and Memory

Computer Architecture & Network Lab 7

 Examples of ISAs and Implementations
 Instruction Set Architectures
 IBM System/360, IA-32 (x86), IA-64, MIPS, SPARC, Alpha, PA-
RISC, ARM, …
 Implementations
 IA-32 (x86)
− Intel: 8086, 8088, 80186, 80286, 80386, 80486, Pentium, Pentium
Pro, Pentium II, Celeron, Pentium III, Pentium 4, …
− AMD: K5, K6, K6-II, K6-III, Athlon, Duron, …
− Cyrix: 80486, 5x86, 6x86,…
 IA-64: Itanium, Itanium 2, …
 Alpha: 21064, 21164, 21264, 21364, …

Computer Architecture & Network Lab 8

 History

 Hot topics in Computer Architecture

 High-level language computer architectures in the 1970s
 RISC architectures in the early 1980s
 Shared-memory multiprocessors in the late 1980s
 Out-of-order speculative execution processors in the 1990s
 Multi-core architectures in the 2000s

From “Single-Chip Multiprocessors: the Rebirth of Parallel Architecture” by Prof. Guri Sohi

Computer Architecture & Network Lab 9

A Critical point in VLSI Technology

Source: www.icknowledge.com

Computer Architecture & Network Lab 10

 History of RISC Architecture

 Integration of processors on a single chip

 A critical point (“epoch”)

 Argued for different architectures (RISC)

− Small repertoire of instructions in a uniform format
− Pipelined execution
− Cache memory
− Load/store architecture
 More transistors allowed for different optimizations
 Large/multi-level caches

 Co-processors

 Superscalar

 etc

From “Single-Chip Multiprocessors: the Rebirth of Parallel Architecture” by Prof. Guri Sohi

Computer Architecture & Network Lab 11

 MIPS Instruction Set Architecture

 One of the Pioneering RISC Instruction Set Architectures

 Small repertoire of instructions in a uniform format
 Pipelined execution
 Cache memory
 Load/store architecture
 Starts with a 32-bit architecture, later extended to 64-bit
 Even currently used in many embedded applications
 Game consoles – Nintendo 64, PlayStation, PlayStation 2, etc
 Network devices – IP phone, WLAN Access points, etc
 Residential Devices – High Definition TV, Digital Photo Frame,
 etc

Computer Architecture & Network Lab 12

 MIPS ISA State (Register & Memory)

Register Memory

0xffff ffff
$31

$1 30
$0 0 2 words =
32
PC 2 bytes
LO
HI

0x0000 0000

Computer Architecture & Network Lab 13

MIPS Register Usage (Software Convention for Interoperability)

0 $zero constant 0 16 $s0 permanent

(For variables in a high-level
1 $at reserved for assembler ··· language program)

2 $v0 return values 23 $s7

3 $v1 24 $t8 temporary

4 $a0 arguments 25 $t9

5 $a1 26 $k0 OS kernel (reserved)

6 $a2 27 $k1
7 $a3 28 $gp global pointer

8 $t0 temporary 29 $sp stack pointer

··· 30 $fp frame pointer
15 $t7 31 $ra return address

Computer Architecture & Network Lab 14

 MIPS Instructions

 Arithmetic/Logic instructions
 Data Transfer (Load/Store) instructions
 Conditional branch instructions
 Unconditional jump instructions

Computer Architecture & Network Lab 15

 MIPS Instruction Format

Name Fields Comments

Field size 6bits 5bits 5bits 5bits 5bits 6bits All MIPS insturctions 32 bits
R-format op rs rt rd shamt funct Arithmetic instruction format
I-format op rs rt address/immediate Transfer, branch, imm. format
J-format op target address Jump instruction format

Computer Architecture & Network Lab 16

 MIPS Integer Arithmetic Instructions

Category Instruction Example Meaning Comments

Arithmetic add add $ s1, $ s2, $ s3 $ s1 = $ s2 + $ s3 3 operands; exception possible

add immediate addi $ s1, $ s2, 100 $ s1 = $ s2 + 100 + constant; exception possible
add unsigned addu $ s1, $ s2, $ s3 $ s1 = $ s2 + $ s3 3 operands; no exceptions
add immediate unsigned addiu $ s1, $ s2, 100 $ s1 = $ s2 + 100 + constant; no exceptions
subtract sub $ s1, $ s2, $ s3 $ s1 = $ s2 - $ s3 3 operands; exception possible
subtract unsigned subu $ s1, $ s2, $ s3 $ s1 = $ s2 - $ s3 3 operands; no exceptions
set less than slt $ s1, $ s2, $ s3 $ s1 = ($ s2 < $ s3) compare signed <
set less than immediate slti $ s1, $ s2, 100 $ s1 = ($ s2 < 100) compare signed < constant
set less than unsigned sltu $ s1, $ s2, $ s3 $ s1 = ($ s2 < $ s3) compare unsigned <
set less than immediate unsigned sltiu $ s1, $ s2, 100 $ s1 = ($ s2 < 100) compare unsigned < constant

Computer Architecture & Network Lab 17

MIPS Integer Arithmetic Instructions

Category Instruction Example Meaning Comments

Arithmetic multiply mult $ s2, $ s3 HI, LO ← $ s2 x $ s3 64 bit signed product

multiply unsigned multu $ s2, $ s3 HI, LO ← $ s2 x $ s3 64 bit unsigned product
divide div $ s2, $ s3 LO ← $ s2 ÷ $ s3, LO ← quotient
HI ← $ s2 mod $ s3 HI ← remainder
divide unsigned divu $ s2, $ s3 LO ← $ s2 ÷ $ s3, Unsigned quotient
HI ← $ s2 mod $ s3 Unsigned remainder
move from HI mfhi $ s1 $ s1 ← HI Used to get copy of HI
move from LO mflo $ s1 $ s1 ← LO Used to get copy of LO

Computer Architecture & Network Lab 18

 MIPS Logical Instructions

Category Instruction Example Meaning Comments

Logical and and $s1, $s2, $s3 $s1 = $s2 & $s3 Thee reg. operands; bit-by-bit AND
and immediate andi $s1, $s2, 100 $s1 = $s2 & 100 Bit-by-Bit AND reg with constant
or or $s1, $s2, $s3 $s1 = $s2 | $s3 Thee reg. operands; bit-by-bit OR
or immediate ori $s1, $s2, 100 $s1 = $s2 | 100 Bit-by-Bit OR reg with constant
xor xor $s1, $s2, $s3 $s1 = $s2 xor $s3 Logical XOR
xor immediate xori $s1, $s2, 10 $s1 = $s2 xor 10 Logical XOR w/ constant
nor nor $s1, $s2, $s3 $s1 = ┒($s2 ∨ $s3) Logical NOR
shift left logical sll $s1, $s2, 10 $s1 = $s2 ≪ 10 Shift left by constant
shift right logical srl $s1, $s2, 10 $s1 = $s2 ≫ 10 Shift right by constant
shift right arithmetic sra $s1, $s2, 10 $s1 = $s2 ≫ 10 Shift right (sign extended)
shift left logical variable sllv $s1, $s2, $s3 $s1 = $s2 ≪ $s3 Shift left by variable
shift right logical variable srlv $s1, $s2, $s3 $s1 = $s2 ≫ $s3 Shift right by variable
shift right arithmetic variable srav $s1, $s2, $s3 $s1 = $s2 ≫ $s3 Shift right arithmetic by variable
load upper immediate lui $s1, 40 $s1 = 40 ≪ 16 Places immediate into upper 16 bits

Computer Architecture & Network Lab 19

MIPS Data Transfer (Load/Store) Instructions

Category Instruction Example Meaning Comments

Date store word sw $ s1, 100($ s2) Memory[$ s2 + 100] = $ s1 Word from register to memory
transfer store halfword sh $ s1, 100($ s2) Memory[$ s2 + 100] = $ s1 Store only lower 16 bits
store byte sb $ s1, 100($ s2) Memory[$ s2 + 100] = $ s1 Store only lowest byte
store float swc1$ f1,100($ s2) Memory[$ s2 + 100] = $ f1 Store FP word
load word lw $ s1, 100($ s2) $ s1 = Memory[$ s2 + 100] Load word
load halfword lh $ s1, 100($ s2) $ s1 = Memory[$ s2 + 100] Load halfword; sign extended
load half unsigned lhu $ s1, 100($ s2) $ s1 = Memory[$ s2 + 100] Load halfword; zero extended
load byte lb $ s1, 100($ s2) $ s1 = Memory[$ s2 + 100] Load byte; sign extended
load byte unsigned lbu $ s1, 100($ s2) $ s1 = Memory[$ s2 + 100] Load byte; zero extended
load float lwc1 $ f1,100($ s2) $ f1 = Memory[$ s2 + 100] Load FP register
load upper immediate lui $ s1, 100 16 Loads constant in upper 16 bits
$ s1 = 100 * 2

Computer Architecture & Network Lab 20

 More about Loads and Stores

 All memory accesses are exclusively through loads and

stores (load-store architecture)
 Alignment restriction
− Word addresses must be multiples of 4
− Halfword addresses must be multiples of 2
 Partial word (halfword or byte) loads from memory
− Sign-extended for signed operations
− Zero-extended for unsigned operations

Computer Architecture & Network Lab 21

 More about Loads and Stores

 Big Endian vs. Little Endian

a b c d ( at address 20 )
MSB LSB

23 d 23 a
22 c 22 b
21 b 21 c
20 a 20 d

Big Endian Little Endian

(Macintosh, Sun SPARC) (DEC Station 3100, Intel 80x86)

Computer Architecture & Network Lab 22

 MIPS Conditional Branch Instructions

Category Instruction Example Meaning Comments

conditional branch branch on equal beq $ s1, $ s2, L if($ s1==$ s2) go to L Equal test and branch
branch on not equal bne $ s1, $ s2, L if($ s1!=$ s2) go to L Not equal test and branch

Computer Architecture & Network Lab 23

 MIPS Unconditional Jump Instructions

Category Instruction Example Meaning Comments

Unconditional jump jump j 2500 go to 10000 Jump to target address

jump register jr $ ra go to $ ra For switch, procedure return
jump and link jal 2500 $ ra = PC + 4 For procedure call
go to 10000

Computer Architecture & Network Lab 24

 MIPS Addressing Modes

 Operand in instruction itself

 Immediate addressing
op rs rt Immediate

 Operand in register
 Register addressing
op rs rt rd ··· funct Registers
Register
 Operand in Memory
 Base addressing
Memory
op rs rt Address

+ Byte Halfword Word

Register

Computer Architecture & Network Lab 25

 MIPS Addressing Modes

 Instruction in memory
 PC-relative addressing (branch)
op rs rt Address Memory

+ Word
PC

 Pseudo-direct addressing (jump)

op Address Memory

： Word
4bits PC

Computer Architecture & Network Lab 26

 MIPS Addressing Modes

 Instruction in memory
 Register (jump register)

op rs Memory

Register Word

Computer Architecture & Network Lab 27

 Addressing Modes (Many not supported in MIPS)
Addressing mode Example Instruction Meaning When used

Register Add R4, R5, R3 R4 ← R5 + R3 When a value is in a register.

Immediate or literal Add R4, R5, #3 R4 ← R5 + 3 For constants.
Displacement or Add R4, R5, 100(R1) R4 ← R5 + M[100+R1] Accessing local variables.
based
Register deferred or Add R4, R5, (R1) R4 ← R5 + M[R1] Accessing using a pointer or a computed address.
indirect
Indexed Add R3, R5, (R1+R2) R3 ← R5 + M[R1+R2] Sometimes useful in array addressing
R1=base of array, R2=index amount.
Direct or absolute Add R1, R5, (1001) R1 ← R5 + M[1001] Sometimes useful for accessing static data:
address constant may need to be large.
Memory indirect or Add R1, R5, @(R3) R1 ← R5 + M[M[R3]] If R3 is the address of a pointer p, then mode
memory deferred yields *p.
Auto-increment Add R1, R5, (R2)+ R1 ← R5 + M[R2] Useful for stepping through arrays within a loop.
R2 pointers to start of array; each reference
R2 ← R2 + d
increments R2 by size of an element, d.
Auto-decrement Add R1, R5, -(R2) R2 ← R2 - d Same use as autoincrement.
R1 ← R5 + M[R2] Autoincrement/decrement can also be used to
implement a stack as push and pop.
Scaled or index Add R1, R5, 100(R2)[R3] R1 ← R5 + Used to index arrays. May be applied to any base
M[100+R2+R3*d] addressing mode in some machines.

Computer Architecture & Network Lab 28

 C vs. Assembly

C Assembly
f = (g + h) – (i + j);
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
f is mapped to s0
g is mapped to s1
h is mapped to s2
i is mapped to s3
j is mapped to s4

Computer Architecture & Network Lab 29

 C vs. Assembly

C Assembly
g = h + A[i];
add $t1, $s4, $s4
add $t1, $t1, $t1
add $t1, $t1, $s3
g is mapped to s1 lw $t0, 0($t1)
h is mapped to s2 add $s1, $s2, $t0
s3 contains the base
address of array A[].
i is mapped to s4.

Computer Architecture & Network Lab 30

 C vs. Assembly

C Assembly
if (i == j) bne $s3, $s4, Else
f = g + h; add $s0, $s1, $s2
else j Exit
f = g – h; Else: sub $s0, $s1, $s2
Exit:

f is mapped to s0
g is mapped to s1
h is mapped to s2
i is mapped to s3
j is mapped to s4

Computer Architecture & Network Lab 31

 C vs. Assembly

C Assembly
Loop: add $t1, $s3, $s3
while (save[i] == k) add $t1, $t1, $t1
i = i + j; add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
add $s3, $s3, $s4
i is mapped to s3 j Loop
j is mapped to s4 Exit:
k is mapped to s5
s6 contains the base address
of array save[].

Computer Architecture & Network Lab 32

 C vs. Assembly

C Assembly
slt $t3, $s5, $zero
switch (k) {
bne $t3, $zero, Exit
case 0: f = i + j; break; slt $t3, $s5, $t2
case 1: f = g + h; break; beq $t3, $zero, Exit
case 2: f = g - h; break; add $t1, $s5, $s5
case 3: f = i - j; break; add $t1, $t1, $t1
} add $t1, $t1, $t4
lw $t0, 0($t1)
jr $t0
f is mapped to s0 L0: add $s0, $s3, $s4
g is mapped to s1 j Exit
h is mapped to s2 L1: add $s0, $s1, $s2
j Exit
i is mapped to s3
L2: sub $s0, $s1, $s2
j is mapped to s4 j Exit
k is mapped to s5 L3: sub $s0, $s3, $s4
t2 contains 4 Exit

Computer Architecture & Network Lab 33

 Pseudo Instructions

 Pseudo instruction : Instructions that are available in assembly

language but not implemented in hardware
 Pseudo instruction examples
Pseudo instruction Equivalent real instruction sequence
move $s1, $s2 add $s1, $zero, $s2
blt $s1, $s2, label slt $at, $s1, $s2
bne $at, $zero, label
abs $s1, $s2 add $s1, $zero, $s2
slt $at, $s2, $zero
beq $at, $zero, L
sub $s1, $zero, $s1
L:

Computer Architecture & Network Lab 34