11 R15

Code: 15404604

B.Tech Ill Year lI Semester (R15) Regular &Supplementary Examinations May/June 2019
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70

PART A
(Compulsory Question)
*****

Answerthe following: (10 X 02 20 Marks)

(a) What is Moore's law? State various IC technologies on the basis of number of transistors on a chip?
(b) Describe the different operating regions for an MOS transistor.
(c) What is figure of merit of a MOS transistor? Mention the suitable expression for figure of merit.
(d) What are the limitations of scaling?
(e)Explainworking of pass transistor logic.
( What are the different ways to improve clock distribution?
(g) Explain working of magnitude comparator.
(h) What are the advantages and applications of FPGA?
What are the different types of modeling in VHDL?
es Explain controllability and observability.

PART B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT-
2 Explain clearly about n-well CMOS fabrication process with neat diagrams.
OR
Draw the VI characteristics of NMOS transistor. Explain its operation and derive the drain to source
current equation in saturation and resistance region.

UNIT-I1
Explain about various contact cuts that are used for CMOS transistor design and fabrication.
OR
Draw a stick diagram for two input NMOS NAND and NOR gates.

UNIT-I
Write short notes about the following:
(a) Pseudo nMOS logic.
(b) Domino-Logic.
OR
Discuss about power delay estimation.

UNIT-IV
8 Implement the arithmetic and logic unit to perform both arithmetic and logic functions using a full
adder.
OR
9(a) Draw and explain the architecture of a CPLD.
(b) Differentiate between the Full-custom and Semi-custom design
UNIT-V
10 What is meant by simulation? Explain the various VHDL simulations.
OR
11 Explain the gate level and function level of testing.
 Code: 16A04604
SR15
B.Tech llI Year ll Semester
(R15) Regular Examinations May/June 20188
VLSI DESIGN
(Electronics and Communication
Engineering)
Time: 3 hours
Max. Marks: 70
PART A
(Compulsory Question)
Answer the following: (10 X 02 20
Marks)
(a) MOSFETs are said to be more efficient than
BJTs. Justify the answer
Define the tems: (i) Body effect.
(ii) Channel length modulation.
(c) How to evaluate
routing capacitance of MOS device?
What are the importance of CMOS
What is the power
design rules?
delay
List out the steps in
product for the load capacitance C 3.5uF, given the
input voltage Voo =
5 V?
physical design layout.
Mention about various Multiplier
architectures followed for VLSI Design.
Give the difference between
Full-custom and Semi-custom devices.
What are the special features of
design verification tools?
What is Built-in-self-test?

PART B
(Answerall five units, 5 X 10 50 Marks)

2 Explain in detail about the

UNIT-1J
steps involved in CMOS IC fabrication
process with essential diagrams.
OR
3 Draw the las-Vas relationship curve and discuss in detail about its
role in the MOS design
equations.
4 Derive the expression for resistance estimation in VLSI
UNIT-I
circuits.
(6) Write short notes on driving large capacitive loads.
OR
5 (a) Explain the 2um CMOS design rules for contacts and transistors.
(6) Briefly discuss about scaling of MOS circuits and its limitations.

6
UNIT-I
With detailed step by step process, design and
a
draw the AND-OR-INVERT form complex gates in
CMOS logic for the output equation Y
(AB +CD). =

OR
Give a
detailed note on
floor-planning and placement in the physical design flow of a CMOS circuit
design
UNIT-IV
Explain about any one multiplier architecture in VLSI
design. What the
considered for the same?
are
challenging issues to be
OR
9 llustrate with neat architecture
diagram and explain about various functional blocks of Field
Programmable Gate Array (FPGAs).

10 (a) Write a short note on circuit

UNIT-V
synthesis.
(b) Give comparison of design
capture tools and design verification tools.
11
OR
Explain in detail about
design for testability.
*****
 Code: 15A04604 R15
D.Iech l Year ll Semester (R15) Regular & Supplementary Examinations Ocfober/November 2020

VLSI DESIGN
(Electronics and Communication Engineering).
Time: 3 hours Max. Marks: 70

PART AA
(Compulsory Question)
Answer the following: (10 X 02 20 Marks)
(a) LIst outthe different steps involved in the IC fabrication process.
Define the term threshold voltage of MOSFET.
What do you mean by inverter delay?
d) Define fan-in and fan-out.
e) What are the steps to be taken care while doing floor-planning?
Differentiate between chip level design and block level design.
(g) List out the differences between FPGA and CPLD.
(h) What is the purpose of DRC?
What is the difference between simulation and synthesis?
What types of defects are tested in manufacturing testing methods?

PART B
(Answerallfive units, 5 X 10 50 Marks)
UNIT-1
2 (a) With neat sketches, explain BiCMOS fabrication in a p-well.
(6) Clearly explain about channel length modulation of the MOSFET.
OR
3 (a) With neat sketches, explain the transfer characteristics of a CMOS inverter.
Explain the processing steps in fabrication of pMOS technology with neat sketches.
UNIT-I1
4 (a) Discuss the design rules for wires.
(b) What is the difference between 'a' and 8' scaling factors? Give some examples.
OR
Discuss in detail about the nMOS design style.
Express the area capacitance in terms of standard capacitance units.
UNIT-I
6 (a) What are the various aspects to be considered in selecting a particular switching technology?
Explain.
(b) Draw the basic structure of a dynamic CMOS gate and explain the same.
OR
7 (a) Compare Two-phase clockingsystem with single phase clocking system. Explain the operation of
clocked inverter circuit with suitable diagram.
(b) How switch logic can be implemented using Pass Transistors and transmission gates? Explain with
suitable diagrams.
UNIT-IV
Design a parity generator and explain the functioning of it with a transistor schematic and layout.
OR
9 (a) Explain about the principle and operation of FPGAs. What are its applications?
(b) What are the advantages and disadvantages of the reconfiguration?

UNIT-V
10 (a) Define synthesis and explain the logic synthesis concept in VLSI circuits.
(b) What are the categories of design for testability? Explain them briefly
OR
11 (a) What is meant by signature analysis in testing? Explain with an example.
(b) Compare functionally test and manufacturing test
 Code: 15A04604

R15
BTechII Year 11 Semester (R15) Regular Exam1nations
VLSI DESIGN May/June 2018
(Electronics and Commur aton
Time 3 hours ngineering
Max M.stks 70
PART A
(Compuisory Ouestion)
Answer the
followng (10 X 02 20 Marks)
(a) MOSEEIs are said
to be nmore efficient than BJT
Body effect (1) Channel length Justify
(b) Define the tems (0) the answer
(c) How to modulation
evaluate routing capacitance of MOS device?
(d) What are the
mportance of CMOS des1gn
(e) What is the power
delay product for the load
rules
List out the
steps n physical design capacitance C 3 51F. given the nput voitage
(9) Mention about vanous layout VA, 5'?

(h) Give the difference Muitiplier architectures followed for VLSI

between Full-custom Design
and Semi custom
What are the
special features of design verification devIces
What is Built-in-self-test? tools?

PART B
(Answer all five units, 5 X 10
50 Marks)
Explain in detal about the
UNIT-1J
steps involved CMOS IC fabrication
in

OR
process with essential diagrarTs
Draw the las-Va.
relationship Curve and discuss in detal
about its role in the MOS
design equatons
4 (a) Derive the expression for resistance UNIT J
(b) Wrte short notes on
estimation in VLSI circuits
driving large capacitive loads
5 OR
(a) Explain the 2m CMOS design rules for contacts
and trans1stors
(b) Briefiy discuss about scaling of MOS circuits and
its limitations

With a detailed step by step

UNIT-I
CMOS
process, design and draw the
AND-OR-INVERT form complex gates
logic for the output equation Y (AB +CD) in

OR
Give a detailed note
design.
on
floor-planning and placement in the physical design flow of a CMOS circut

8 Explain about any

UNIT-IV
one multiplier architecture in VLSI
considered for the same? design. What are the
challenging issues to be

9 OR
lustrate with neat architecture
diagram and explain about various functional blocks of
Programmable Gate Array (FPGAs). Field

10 (a) Write a short note on circuit

UNIT -V
(b)
synthesis
Give comparison of design capture tools
and design verification tools
11 OR
Explain in detail about design for testability.
*****
Code: 15A04604 R15
B.Tech ll Year Il Semester (R15) Supplementary Examinations December/January 2018/19
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
PART A
(Compulsory Question)
*****

Answer the following: (10 X 02 20 Marks)

(a) Differentiate between PMOS and NMOS transistors.
(6) Write the basic DC equations of a MOS transistor design in cutoff, saturation and linear region.
)Find the sheet resistance of a material;given the resistivity p =21Qm and the thickness is 3m.
(d) Give some limitations of scaling
(e) Define the terms placement of scaling.
(f) Give comparison of clock routing and power routing.
(g What is the use of a comparator? Draw the simple comparator circuit?
(h) Differentiate between standard cells and gate arrays.
() Define the terms synthesis and simulation.
Why do we need "Design for testability" in a VLSI design?

PART-B
(Answer all five units, 5 X 10 50 Marks)
UNIT-1
2 Explain in detail about the steps involved in SOI technology fabrication process with essential
diagrams.
OR
3 Design a CMOS inverter circuit and explain about its various regions of operation in detail with the
necessary diagrams.
UNIT-I1
4 With necessary equations, explain in detail about simple capacitive model and flat band capacitance
model.
OR
5 (a) Discuss about VLSI design flow.
(b) Write short notes on stick diagram and layout diagram.
UNIT-I
With a detailed step by step process, design and drawthe OR-AND-INVERT form complex gates in
CMOS logic for the output expression Y ((A +B).(C+ D)..
OR
List out the types of routing in a CMOS physical design. And give a detailed note on each one of
them.
UNIT-IV
Draw the truth table fora cary look ahead adder. With the help of K-map reduce the equation and
draw the logical circuit diagram for the obtained equation.
OR
Discuss about design approach of Full custom and Sem-custom devices
UNIT -V
10 Write a short note on the following tools:
(a) Design capture tools.
(b) Design verification tools
OR
11 Explain in detail about Fault modeling and simulation with the necessary example circult's
 ESC
Code: 15A04604 R15
onpagY
B.Tech IlI Year lI Semester (R15) Supplementary
VLSI DESIGN
Examinetons April 2021
(Electronics & Communication Engineering)
Time: 3 hours Max Marks 70
PART A
(Compulsory Question)
1 Answer the following: (10 X 02 20 Marks)
=

(a) What are the different VLSI technologies available?

(b) Explain about ion implantation
(c) Why scaling is required?
(d) What are the different types of design rules?
(e) What are inputs and outputs of floor plan stage?
() What is core utilization?
(9) What kinds of programmable logic devices are available today? How are they different from one
another?
(h) Discuss about microcell.
List the categories of testing.
) What is meant by open circuit fault?

PART B
(Answerall five units, 5X 10 50 Marks)
UNIT-1
2 (a) With neat sketches, explain the nMOS fabrication procedure?
(b) Clearly explain body effect ofMOSFET
OR
3 (a) Explain the operation of BiCMOS inverter. Clearly specify its characteristics.
(b) With neat sketches, explain how npn transistors are fabricated in bipolar process.
UNIT-
4 (a) Explain the design flow in manufacturing VLSI chip.
(b) What is a stick diagram? Explain about different symbols used for components in stick diagram
OR
5 (a) Write the scaling factors for different types of device parameters.
(b) What are design rules? Why is metal-metalspacing larger than poly-poly spacing?
UNIT I
6 (a) Explain about NORA CMOSlogic. Draw the NORA structure for EX-OR and EX-NOR gates
(b) Define floor planning. Explain the floor planning methods in VLSI design.
OR
7 (a) Explain about switch logic. What are the various aspects to be considered in selecting a particular
Switching technology?
(b) Describe constructional features and performance characteristics of Pseudo-nMOS Iogic.
UNIT-IV
8 (a) Draw the architecture of Carry Bypass Adder and explain its operation.
(6) Explain how the pass transistors are used to connect wire segments for the purpose of FPGA
programming.
OR
9a)Drawthe Barrel shifter architecture and explain its operation.
() Explain how the l/O pad is programmed in FPGA.
UNIT-V
10 (a) Explain about Simulation process and Synthesis process.
() Explain about testing and fault simulation in VLSI design.
OR
11 (a) Discuss the steps in VHDL design flow.
(b) Write a short note on BIST.
*****
 Code: 15A04604 COL EG R15

B.Tech II Year II Semester (R15) Supplementary Examinations pecember 2019

VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70

PART A
(Compulsory Question)

Answer the following: (10 X 02 20 Marks)

(a) Distinguish between CMOS and BiCMOS.
(b) Define the threshold voltage with suitable equation of a MOS device.
(c) Define sheet resistance of the MOS device.
(d) Design a stick diagram for NMOS inverter.
(e) Write short notes on switch logic.
() Design a two input CMOS NAND gate with neat sketch.
(g) What is parity generator?
(h) Compare CPLD and FPGA.
() Write short notes on design capture tools.
) What is the need for testing?

PART B
(Answerallfive units, 5X 10 50 Marks)
UNIT-1
2 Explain clearly about NMOS fabrication process flow with neat diagrams.
OR
3 (a) Draw the V-I characteristics of MOSFET and prove that les is linear function of Vas.
When the gate to source voltage Vos of a MOSFET with threshold voltage of 400mV, working in
(b) saturation is 900mV, the drain current is observed to be 1mA and assuming that the MOSFET is

operating at saturation. Calculate the drain current for

an applied Vss of 1400mV.
UNIT-1
4 (a) Define fan-in and fan-out. Explain their effects on propagation delay.

(b) What do you mean by inverter delay? Explain.

OR
Design a stick and layout diagram for CM0S inverter and two input NMOS NAND gate.
5
UNIT-I
What are the alternate gate circuits available? Explain them with suitable sketch.
6
OR
Discuss about the floor planning
UNIT-IV
Explain the working principle of 6-transistor static RAM and 1-transistor dynamic RAM with

necessary diagrams.
OR
Explain the design flow of FPGA.

UNIT-V
10 Explain the design capture and design verification tools.
OR
11 What is meant by synthesis? Explain the circuit synthesis design methods.

***