1.

Introduction:-
A phase-locked loop (PLL) is an electronic circuit that consists of a
phase detector, a low-pass filter, and a voltage-controlled oscillator.
Reference signal

Feedback signal

Phase Detector
Output

Loop filter
Output
Common applications of a PLL include:

1. Frequency synthesizers that provide multiples of a reference signal

frequency .

2. FM demodulation networks for FM operation with excellent

linearity between the input signal frequency and the PLL output

voltage.

3. Demodulation of the two data transmission or carrier frequencies in

digital-data transmission used in frequency-shift keying (FSK).

4. a wide variety of areas including modems, telemetry receivers and

transmitters, tone decoders, AM detectors, and tracking filters.

To solve the non linearity issue for the phase difference grater
than 180 we can use Phase Frequency Detector instead of using
XOR
2. Basic PLL Operation
• An input signal, Vi and that from a VCO, Vo are compared by a phase
comparator providing an output voltage, Ve that represents the phase
difference between the two signals.
• This voltage is then fed to a low-pass filter that provides an output
voltage (amplified if necessary) that can be taken as the output voltage
from the PLL and is used internally as the voltage to modulate the
VCO’s frequency.
• The closed-loop operation of the circuit is to maintain the VCO
frequency locked to that of the input signal frequency (are the same).
• First consider the operation of the various circuits in the PLL when
the loop is operating in lock.
• The voltage, Vd, taken as output is the value needed to hold the VCO
in lock with the input signal.
• The VCO then provides output of a fixed-amplitude square-wave
signal at the frequency of the input.
• The amplifier allows the adjustment in dc voltage from that obtained
as output of the filter circuit.
• A fixed phase difference between the two signals to the comparator
results in a fixed dc voltage to the VCO.
• Changes in the input signal frequency then result in change in the dc
voltage to the VCO.
• Within a capture-and-lock frequency range, the dc voltage will drive
the VCO frequency to match that of the input.
• While the loop is trying to achieve lock, the output of the phase
comparator contains frequency components at the sum and difference.
• A low-pass filter passes only the lower frequency, so that the loop can
obtain lock between input and VCO signals.
• Owing to the limited operating range of the VCO and the feedback
connection of the PLL circuit, there are two important frequency bands
specified for a PLL.
• The capture range: is the frequency range centered about the VCO
free-running frequency fo over which the loop can acquire lock with the
input signal.
• Once the PLL has achieved capture, it can maintain lock with the input
signal over a somewhat wider frequency range called the lock range.
3. Frequency Demodulation
If the PLL center frequency is selected or designed at the FM carrier
frequency, the filtered or output voltage is the desired demodulated
voltage, varying in value in proportion to the variation of the signal
frequency.
• The PLL circuit thus operates as a complete intermediate-frequency
(IF) strip, limiter, and demodulator as used in FM receivers.
 • An external resistor and capacitor R1 and C1 , are used to set the
free-running or center frequency of the VCO.
• Another external capacitor, C2 , is used to set the low-pass filter
passband, and the VCO output must be connected back as input to the
phase detector to close the PLL loop.

PLL connected as a frequency demodulator

• The free-running frequency fo :
0.3
fo 
R1C1
0.3
fo  12
 136.36kHz
10  10  220  10
3

• with limitation 2kΩ ≤ R1 ≤ 20kΩ. The lock range is

8f
fL   o
V
8 136.36 103 
  181.8 kHz
6
• The capture range is
1 2 f L
fC  
2 R2C2

1 2 181.8 103 
  156.1 kHz
2 3.6  10  330  10
3 12
• The signal at pin 4 is a 136.36-kHz square wave.
• An input within the lock range of 181.8 kHz will result in the output
at pin 7 varying around its dc voltage level set with input signal at fo .
• The dc voltage at pin 7 is linearly related to the input signal
frequency within the frequency range fL = 181.8 kHz around the center
frequency 136.36 kHz.

• The output voltage is the demodulated

signal that varies with frequency within the operating range specified.
4. Frequency Synthesis
A frequency divider is inserted between the VCO output and the phase
comparator so that the loop signal to the comparator is at frequency fo
and the VCO output is Nfo .
• This output is a multiple of the input frequency as long as the loop
is in lock.
• The input signal can be stabilized at f1 with the resulting VCO output
at N f1 if the loop is set up to lock at the fundamental frequency (when
fo = f1).
• Using a 565 PLL as frequency multiplier and a 7490 as divider.
• The input Vi at frequency f1 is compared to the input ( fo ) at pin 5.
• An output at Nfo (4 fo ) is connected through an inverter circuit to
the input at pin 14 of the 7490, which varies between 0 V and 5V.
• Using the output at pin 9, which is one-fourth that at the input to the
7490, we find that the signal at pin 4 of the PLL is four times the input
frequency as long as the loop remains in lock.
• Since the VCO can vary over only a limited range from its center
frequency, it may be necessary to change the VCO frequency
whenever the divider value is changed.
•As long as the PLL circuit is in lock, the VCO output frequency will
be exactly N times the input frequency.
• It is only necessary to readjust fo to be within the capture-and-lock
range, the closed loop then resulting in the VCO output becoming
exactly Nf1 at lock.
5. FSK Decoders
The decoder receives a signal at one of two distinct carrier frequencies,
1270 Hz or 1070 Hz, representing the RS-232C logic levels or mark
(-5 V) or space (+14 V), respectively.
• As the signal appears at the input, the loop locks to the input
frequency and tracks it between two possible frequencies with a
corresponding dc shift at the output.
• The RC ladder filter is used to remove the sum-frequency component.

• The free-running frequency is adjusted with R1 so that the dc voltage

level at the output (pin 7) is the same as that at pin 6.

• Then an input at frequency 1070 Hz will drive the decoder output

voltage to a more positive voltage level, driving the digital output to the

high level (space, or 14 V).

• An input at 1270 Hz will correspondingly drive the 565 dc output less

positive with the digital output, which then drops to the low level (mark,

or 5 V).