Ni 6221
Ni 6221
Ni 6221
June 2007
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FCC/DOC Warnings
This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions
in this manual and the CE marking Declaration of Conformity*, may cause interference to radio and television reception.
Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department
of Communications (DOC).
Changes or modifications not expressly approved by NI could void the user’s authority to operate the equipment under the
FCC Rules.
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This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC
Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated
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used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this
equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference
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* The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or
installer.
Contents
Chapter 1
Getting Started
Installing NI-DAQmx ....................................................................................................1-1
Installing Other Software...............................................................................................1-1
Installing the Hardware..................................................................................................1-1
Device Pinouts ...............................................................................................................1-1
Device Specifications ....................................................................................................1-2
Device Accessories and Cables .....................................................................................1-2
Applying the Signal Label to USB-622x/625x Screw Terminal Devices......................1-2
USB Cable Strain Relief ................................................................................................1-3
Chapter 2
DAQ System Overview
DAQ Hardware ..............................................................................................................2-1
DAQ-STC2 and DAQ-6202 ............................................................................2-2
Calibration Circuitry........................................................................................2-3
Signal Conditioning .......................................................................................................2-3
Sensors and Transducers .................................................................................2-3
Signal Conditioning Options ...........................................................................2-4
SCXI..................................................................................................2-4
SCC ...................................................................................................2-5
5B Series ...........................................................................................2-5
Cables and Accessories..................................................................................................2-6
Custom Cabling ...............................................................................................2-6
Programming Devices in Software ................................................................................2-7
Chapter 3
Connector and LED Information
I/O Connector Signal Descriptions ................................................................................3-2
M Series and E Series Pinout Comparison ....................................................................3-5
+5 V Power Source ........................................................................................................3-7
USB Chassis Ground .....................................................................................................3-7
Chapter 4
Analog Input
Analog Input Range....................................................................................................... 4-2
Analog Input Lowpass Filter ......................................................................................... 4-4
Analog Input Ground-Reference Settings ..................................................................... 4-5
Configuring AI Ground-Reference Settings in Software................................ 4-7
Multichannel Scanning Considerations......................................................................... 4-7
Use Low Impedance Sources .......................................................................... 4-8
Use Short High-Quality Cabling..................................................................... 4-8
Carefully Choose the Channel Scanning Order .............................................. 4-9
Avoid Switching from a Large to a Small Input Range ................... 4-9
Insert Grounded Channel between Signal Channels ........................ 4-9
Minimize Voltage Step between Adjacent Channels ....................... 4-10
Avoid Scanning Faster Than Necessary ......................................................... 4-10
Example 1 ......................................................................................... 4-10
Example 2 ......................................................................................... 4-10
Analog Input Data Acquisition Methods....................................................................... 4-11
Software-Timed Acquisitions ......................................................................... 4-11
Hardware-Timed Acquisitions ........................................................................ 4-11
Buffered ............................................................................................ 4-11
Non-Buffered.................................................................................... 4-12
Analog Input Triggering................................................................................................ 4-12
Connecting Analog Input Signals.................................................................................. 4-13
Connecting Floating Signal Sources ............................................................................. 4-15
What Are Floating Signal Sources? ................................................................ 4-15
When to Use Differential Connections with Floating Signal Sources............ 4-15
When to Use Non-Referenced Single-Ended (NRSE) Connections
with Floating Signal Sources ....................................................................... 4-15
When to Use Referenced Single-Ended (RSE) Connections
with Floating Signal Sources ....................................................................... 4-16
Using Differential Connections for Floating Signal Sources.......................... 4-16
Using Non-Referenced Single-Ended (NRSE) Connections
for Floating Signal Sources .......................................................................... 4-19
Using Referenced Single-Ended (RSE) Connections for Floating
Signal Sources .............................................................................................. 4-20
Chapter 5
Analog Output
AO Offset and AO Reference Selection........................................................................ 5-2
Minimizing Glitches on the Output Signal.................................................................... 5-4
Analog Output Data Generation Methods..................................................................... 5-4
Software-Timed Generations .......................................................................... 5-4
Hardware-Timed Generations......................................................................... 5-4
Non-Buffered.................................................................................... 5-5
Buffered ............................................................................................ 5-5
Analog Output Triggering ............................................................................................. 5-6
Connecting Analog Output Signals ............................................................................... 5-6
Analog Output Timing Signals...................................................................................... 5-7
AO Start Trigger Signal .................................................................................. 5-7
Using a Digital Source...................................................................... 5-7
Using an Analog Source ................................................................... 5-8
Routing AO Start Trigger Signal to an Output Terminal ................. 5-8
AO Pause Trigger Signal ................................................................................ 5-8
Using a Digital Source...................................................................... 5-9
Using an Analog Source ................................................................... 5-10
Routing AO Pause Trigger Signal to an Output Terminal ............... 5-10
AO Sample Clock Signal ................................................................................ 5-10
Using an Internal Source .................................................................. 5-10
Using an External Source ................................................................. 5-10
Routing AO Sample Clock Signal to an Output Terminal ............... 5-10
Other Timing Requirements ............................................................. 5-11
AO Sample Clock Timebase Signal................................................................ 5-11
Getting Started with AO Applications in Software....................................................... 5-12
Chapter 6
Digital I/O
Static DIO...................................................................................................................... 6-2
Digital Waveform Triggering........................................................................................ 6-3
Digital Waveform Acquisition ...................................................................................... 6-3
DI Sample Clock Signal.................................................................................. 6-4
Using an Internal Source .................................................................. 6-4
Using an External Source ................................................................. 6-4
Routing DI Sample Clock to an Output Terminal ............................ 6-5
Digital Waveform Generation ....................................................................................... 6-5
DO Sample Clock Signal ................................................................................ 6-5
Using an Internal Source .................................................................. 6-6
Using an External Source ................................................................. 6-6
Routing DO Sample Clock to an Output Terminal .......................... 6-6
I/O Protection.................................................................................................................6-7
Programmable Power-Up States ....................................................................................6-7
DI Change Detection .....................................................................................................6-8
Applications.....................................................................................................6-9
Connecting Digital I/O Signals......................................................................................6-9
Getting Started with DIO Applications in Software ......................................................6-10
Chapter 7
Counters
Counter Input Applications............................................................................................7-2
Counting Edges ...............................................................................................7-2
Single Point (On-Demand) Edge Counting ......................................7-2
Buffered (Sample Clock) Edge Counting .........................................7-3
Controlling the Direction of Counting ..............................................7-4
Pulse-Width Measurement ..............................................................................7-4
Single Pulse-Width Measurement.....................................................7-4
Buffered Pulse-Width Measurement.................................................7-5
Period Measurement........................................................................................7-6
Single Period Measurement ..............................................................7-6
Buffered Period Measurement ..........................................................7-7
Semi-Period Measurement ..............................................................................7-8
Single Semi-Period Measurement.....................................................7-8
Buffered Semi-Period Measurement.................................................7-8
Frequency Measurement .................................................................................7-9
Method 1—Measure Low Frequency with One Counter..................7-9
Method 1b—Measure Low Frequency with One Counter
(Averaged)......................................................................................7-10
Method 2—Measure High Frequency with Two Counters...............7-11
Method 3—Measure Large Range of Frequencies
Using Two Counters ......................................................................7-12
Choosing a Method for Measuring Frequency .................................7-13
Position Measurement .....................................................................................7-14
Measurements Using Quadrature Encoders......................................7-14
Measurements Using Two Pulse Encoders .......................................7-17
Two-Signal Edge-Separation Measurement....................................................7-17
Single Two-Signal Edge-Separation Measurement ..........................7-18
Buffered Two-Signal Edge-Separation Measurement ......................7-18
Counter Output Applications .........................................................................................7-19
Simple Pulse Generation .................................................................................7-19
Single Pulse Generation ....................................................................7-19
Single Pulse Generation with Start Trigger ......................................7-20
Retriggerable Single Pulse Generation .............................................7-21
Chapter 8
PFI
Using PFI Terminals as Timing Input Signals...............................................................8-2
Exporting Timing Output Signals Using PFI Terminals ...............................................8-3
Using PFI Terminals as Static Digital I/Os ...................................................................8-3
Connecting PFI Input Signals ........................................................................................8-4
PFI Filters ......................................................................................................................8-4
I/O Protection.................................................................................................................8-6
Programmable Power-Up States ....................................................................................8-6
Chapter 9
Digital Routing and Clock Generation
Clock Routing ................................................................................................................9-1
80 MHz Timebase ...........................................................................................9-2
20 MHz Timebase ...........................................................................................9-2
100 kHz Timebase...........................................................................................9-2
External Reference Clock................................................................................9-2
10 MHz Reference Clock ................................................................................9-3
Synchronizing Multiple Devices ...................................................................................9-3
Real-Time System Integration (RTSI)...........................................................................9-4
RTSI Connector Pinout ...................................................................................9-4
Using RTSI as Outputs....................................................................................9-6
Using RTSI Terminals as Timing Input Signals .............................................9-6
RTSI Filters .....................................................................................................9-7
PXI Clock and Trigger Signals ......................................................................................9-8
PXI_CLK10.....................................................................................................9-8
PXI Triggers ....................................................................................................9-8
PXI_STAR Trigger .........................................................................................9-9
PXI_STAR Filters ...........................................................................................9-9
Chapter 10
Bus Interface
DMA Controllers and USB Signal Stream ....................................................................10-1
PXI Considerations ........................................................................................................10-2
PXI Clock and Trigger Signals........................................................................10-2
PXI and PXI Express.......................................................................................10-2
Using PXI with CompactPCI ..........................................................................10-3
Chapter 11
Triggering
Triggering with a Digital Source................................................................................... 11-1
Triggering with an Analog Source ................................................................................ 11-2
APFI <0..1> Terminals ................................................................................... 11-2
Analog Input Channels.................................................................................... 11-3
Analog Trigger Actions .................................................................... 11-3
Routing Analog Comparison Event to an Output Terminal ........................... 11-3
Analog Trigger Types.................................................................................................... 11-3
Analog Edge Triggering.................................................................................. 11-4
Analog Edge Triggering with Hysteresis........................................................ 11-4
Analog Edge Trigger with Hysteresis (Rising Slope) ...................... 11-5
Analog Edge Trigger with Hysteresis (Falling Slope) ..................... 11-5
Analog Window Triggering ............................................................................ 11-6
Analog Trigger Accuracy .............................................................................................. 11-7
Appendix A
Device-Specific Information
NI 6220.......................................................................................................................... A-2
NI 6221.......................................................................................................................... A-7
NI 6224.......................................................................................................................... A-24
NI 6225.......................................................................................................................... A-30
NI 6229.......................................................................................................................... A-45
NI 6250.......................................................................................................................... A-61
NI 6251.......................................................................................................................... A-66
NI 6254.......................................................................................................................... A-86
NI 6255.......................................................................................................................... A-92
NI 6259.......................................................................................................................... A-107
NI 6280.......................................................................................................................... A-129
NI 6281.......................................................................................................................... A-134
NI 6284.......................................................................................................................... A-139
NI 6289.......................................................................................................................... A-145
Appendix B
Timing Diagrams
Appendix C
Troubleshooting
Appendix D
Upgrading from E Series to M Series
Appendix E
Technical Support and Professional Services
Glossary
Index
Device Pinouts
Figure A-1. PCI/PXI-6220 Pinout ............................................................................A-3
Figure A-2. PCI/PXI-6221 (68-Pin) Pinout ..............................................................A-8
Figure A-3. PCI-6221 (37-Pin) Pinout......................................................................A-12
Figure A-4. USB-6221 Screw Terminal Pinout........................................................A-15
Figure A-5. USB-6221 BNC Top Panel and Pinout .................................................A-18
Figure A-13. PCI/PXI-6224 Pinout ............................................................................A-25
Figure A-14. PCI/PXI-6225 Pinout ............................................................................A-31
Figure A-15. USB-6225 Screw Terminal Pinout........................................................A-37
Figure A-16. USB-6225 Mass Termination Pinout ....................................................A-40
Figure A-17. PCI/PXI-6229 Pinout ............................................................................A-46
Figure A-18. USB-6229 Screw Terminal Pinout........................................................A-52
Figure A-19. USB-6229 BNC Top Panel and Pinout .................................................A-55
Figure A-27. PCI/PXI-6250 Pinout ............................................................................A-62
Figure A-28. NI PCI/PCIe/PXI/PXIe-6251 Pinout.....................................................A-67
Figure A-29. USB-6251 Screw Terminal Pinout........................................................A-71
Figure A-30. USB-6251 BNC Top Panel and Pinout .................................................A-74
Figure A-39. USB-6251 Mass Termination Pinout ....................................................A-82
Figure A-40. PCI/PXI-6254 Pinout ............................................................................A-87
Figure A-41. PCI/PXI-6255 Pinout ............................................................................A-93
Figure A-42. USB-6255 Screw Terminal Pinout........................................................A-99
Figure A-43. USB-6255 Mass Termination Pinout ....................................................A-102
Figure A-44. NI PCI/PCIe/PXI/PXIe-6259 Pinout.....................................................A-108
Figure A-45. USB-6259 Screw Terminal Pinout........................................................A-114
Figure A-46. USB-6259 BNC Top Panel and Pinout .................................................A-117
Figure A-55. USB-6259 Mass Termination Pinout ....................................................A-125
Figure A-56. PCI/PXI-6280 Pinout ............................................................................A-130
Figure A-57. PCI/PXI-6281 Pinout ............................................................................A-135
Figure A-58. PCI/PXI-6284 Pinout ............................................................................A-140
Figure A-59. PCI/PXI-6289 Pinout ............................................................................A-146
The M Series User Manual contains information about using the National
Instruments M Series data acquisition (DAQ) devices with NI-DAQ 8.6 and
later. M Series devices feature up to 80 analog input (AI) channels, and up
to four analog output (AO) channels, up to 48 lines of digital input/output
(DIO), and two counters.
Conventions
The following conventions are used in this manual:
» The » symbol leads you through nested menu items and dialog box options
to a final action. The sequence File»Page Setup»Options directs you to
pull down the File menu, select the Page Setup item, and select Options
from the last dialog box.
bold Bold text denotes items that you must select or click in the software, such
as menu items and dialog box options. Bold text also denotes parameter
names.
monospace Text in this font denotes text or characters that you should enter from the
keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
Platform Text in this font denotes a specific platform and indicates that the text
following it applies only to that platform.
Related Documentation
Each application software package and driver includes information about
writing applications for taking measurements and controlling measurement
devices. The following references to documents assume you have
NI-DAQ 8.6 or later, and where applicable, version 7.0 or later of the
NI application software.
The NI-DAQ Readme lists which devices are supported by this version of
NI-DAQ. Select Start»All Programs»National Instruments»NI-DAQ»
NI-DAQ Readme.
The NI-DAQ Readme for Linux lists supported devices and includes
software installation instructions, frequently asked questions, and known
issues.
Getting Started with NI-DAQmx Base for Linux and Mac Users describes
how to install your NI-DAQmx Base software, your NI-DAQmx
Base-supported DAQ device, and how to confirm that your device is
operating properly on your Mac/Linux machine.
The NI-DAQmx Base Readme lists which devices are supported by this
version of NI-DAQmx Base. In Windows, select Start»All Programs»
National Instruments»NI-DAQmx Base»DAQmx Base Readme.
LabVIEW
If you are a new user, use the Getting Started with LabVIEW manual to
familiarize yourself with the LabVIEW graphical programming
environment and the basic LabVIEW features you use to build data
acquisition and instrument control applications. Open the Getting Started
with LabVIEW manual by selecting Start»All Programs»National
Instruments»LabVIEW»LabVIEW Manuals or by navigating to the
labview\manuals directory and opening LV_Getting_Started.pdf.
LabWindows/CVI
The Data Acquisition book of the LabWindows/CVI Help contains
measurement concepts for NI-DAQmx. This book also contains Taking an
NI-DAQmx Measurement in LabWindows/CVI, which includes
step-by-step instructions about creating a measurement task using the DAQ
Assistant. In LabWindows™/CVI™, select Help»Contents, then select
Using LabWindows/CVI»Data Acquisition.
Measurement Studio
If you program your NI-DAQmx-supported device in Measurement Studio
using Visual C++, Visual C#, or Visual Basic .NET, you can interactively
create channels and tasks by launching the DAQ Assistant from MAX or
from within Visual Studio .NET. You can generate the configuration code
based on your task or channel in Measurement Studio. Refer to the DAQ
Assistant Help for additional information about generating code. You also
can create channels and tasks, and write your own applications in your
ADE using the NI-DAQmx API.
For help with NI-DAQmx methods and properties, refer to the NI-DAQmx
.NET Class Library or the NI-DAQmx Visual C++ Class Library included
in the NI Measurement Studio Help. For general help with programming in
Measurement Studio, refer to the NI Measurement Studio Help, which is
fully integrated with the Microsoft Visual Studio .NET help. To view
this help file in Visual Studio. NET, select Measurement Studio»
NI Measurement Studio Help.
To get to the same help topics from within Visual Studio, go to Help»
Contents. Select Measurement Studio from the Filtered By drop-down
list and follow the previous instructions.
Training Courses
If you need more help getting started developing an application with
NI products, NI offers training courses. To enroll in a course or obtain a
detailed course outline, refer to ni.com/training.
DAQ specifications and some DAQ manuals are available as PDFs. You
must have Adobe Acrobat Reader with Search and Accessibility 5.0.5 or
later installed to view the PDFs. Refer to the Adobe Systems Incorporated
Web site at www.adobe.com to download Acrobat Reader. Refer to the
National Instruments Product Manuals Library at ni.com/manuals for
updated documentation resources.
Before installing your DAQ device, you must install the software you plan
to use with the device.
Installing NI-DAQmx
The DAQ Getting Started Guide, which you can download at
ni.com/manuals, offers NI-DAQmx users step-by-step instructions for
installing software and hardware, configuring channels and tasks, and
getting started developing an application.
Device Pinouts
Refer to Appendix A, Device-Specific Information, for M Series device
pinouts.
Device Specifications
Refer to the specifications for your device, the NI 622x Specifications, the
NI 625x Specifications, or the NI 628x Specifications, available on the
NI-DAQ Device Document Browser or ni.com/manuals, for more
detailed information about M Series devices.
Figure 1-2. USB Cable Strain Relief on USB-622x/625x Screw Terminal and
USB-622x/625x Mass Termination Devices
(USB-622x/625x BNC Devices) Thread a zip tie through two of the strain relief
holes on the end cap to provide strain relief for your USB cable as shown
in Figure 1-3. The strain relief holes can also be used as cable management
for signal wires to/from the screw terminals and BNC connectors.
DAQ Hardware
DAQ hardware digitizes signals, performs D/A conversions to generate
analog output signals, and measures and controls digital I/O signals.
Figure 2-2 features components common to all M Series devices.
Analog Input
Analog Output
I/O Connector
Digital
Routing Bus
Digital I/O and Clock Bus
Interface
Generation
Counters
RTSI
PFI
Calibration Circuitry
The M Series analog inputs and outputs have calibration circuitry to correct
gain and offset errors. You can calibrate the device to minimize AI and AO
errors caused by time and temperature drift at run time. No external
circuitry is necessary; an internal reference ensures high accuracy and
stability over time and temperature changes.
Signal Conditioning
Many sensors and transducers require signal conditioning before a
measurement system can effectively and accurately acquire the signal. The
front-end signal conditioning system can include functions such as signal
amplification, attenuation, filtering, electrical isolation, simultaneous
sampling, and multiplexing. In addition, many transducers require
excitation currents or voltages, bridge completion, linearization, or high
amplification for proper and accurate operation. Therefore, most
computer-based measurement systems include some form of signal
conditioning in addition to plug-in data acquisition DAQ devices.
To measure signals from these various transducers, you must convert them
into a form that a DAQ device can accept. For example, the output voltage
of most thermocouples is very small and susceptible to noise. Therefore,
you may need to amplify or filter the thermocouple output before digitizing
SCC
SCC is a front-end signal conditioning system for M Series plug-in data
acquisition devices. An SCC system consists of a shielded carrier that holds
up to 20 single- or dual-channel SCC modules for conditioning
thermocouples and other transducers. SCC is designed for small
measurement systems where you need only a few channels of each signal
type, or for portable applications. SCC systems also offer the most
comprehensive and flexible signal connectivity options.
Note PCI Express users should consider the power limits on certain SCC modules without
an external power supply. Refer to the specifications for your device, and the Disk Drive
Power Connector section of Chapter 3, Connector and LED Information, for information
about power limits and increasing the current the device can supply on the +5 V terminal.
Note SCC is not supported on the PCI-6221 (37-pin), USB-622x/625x Screw Terminal, or
USB-622x/625x BNC devices.
5B Series
5B is a front-end signal conditioning system for plug-in data acquisition
devices. A 5B system consists of eight or 16 single-channel modules that
plug into a backplane for conditioning thermocouples and other analog
signals. National Instruments offers a complete line of 5B modules,
carriers, backplanes, and accessories.
Note For more information about SCXI, SCC, and 5B Series products, refer to
ni.com/signalconditioning.
Refer to the Custom Cabling section of this chapter, the Field Wiring
Considerations section of Chapter 4, Analog Input, and Appendix A,
Device-Specific Information, for information about how to select
accessories for your M Series device.
Custom Cabling
NI offers cables and accessories for many applications. However, if you
want to develop your own cable, adhere to the following guidelines for best
results:
• For AI signals, use shielded, twisted-pair wires for each AI pair of
differential inputs. Connect the shield for each signal pair to the ground
reference at the source.
• Route the analog lines separately from the digital lines.
• When using a cable shield, use separate shields for the analog and
digital sections of the cable. Failure to do so results in noise coupling
into the analog signals from transient digital signals.
For more information about the connectors used for DAQ devices, refer to
the KnowledgeBase document, Specifications and Manufacturers for
Measurement Studio, Visual Basic, and ANSI C examples are located in the
following directories:
• NI-DAQmx examples for Measurement Studio-supported languages
are in the following directories:
– MeasurementStudio\VCNET\Examples\NIDaq
– MeasurementStudio\DotNET\Examples\NIDaq
• NI-DAQmx examples for ANSI C are in the NI-DAQ\Examples\
DAQmx ANSI C Dev directory
AI SENSE, — Input Analog Input Sense—In NRSE mode, the reference for
AI SENSE 2 each AI <0..15> signal is AI SENSE; the reference for
each AI <16..63> and AI <64..79> signal is
AI SENSE 2. Also refer to the Connecting
Ground-Referenced Signal Sources section of Chapter 4,
Analog Input
APFI <0..1> AO GND/AI GND Input Analog Programmable Function Interface Channels
0 to 1—Each APFI signal can be used as AO external
reference inputs for AO <0..3>, AO external offset input,
or as an analog trigger input. APFI <0..1> are referenced
to AI GND when they are used as analog trigger inputs.
APFI <0..1> are referenced to AO GND when they are
used as AO external offset or reference inputs. These
functions are not available on all devices. Refer to the
specifications for your device.
E Series M Series
Terminal Terminal* Terminal Differences
1 FREQ OUT PFI 14/P2.6 E Series devices drive each of these terminals with one
particular internal timing signal.
2 CTR 0 OUT PFI 12/P2.4
(GPCTR0_OUT) M Series devices can drive each terminal with the same
signal as on E Series devices. On M Series devices, you
40 CTR 1 OUT PFI 13/P2.5 also can route many other internal timing signals to each
(GPCTR1_OUT) terminal.
45 EXT STROBE PFI 10/P2.2 On M Series devices, you also can use these terminals as
additional PFI inputs to drive internal timing signals.
46 AI HOLD COMP PFI 11/P2.3
(SCANCLK) On M Series devices, you also can use these terminals as
digital I/O signals.
3 PFI 9/CTR 0 GATE PFI 9/P2.1 As a PFI input, the functionality of E Series and
(GPCTR0_GATE) M Series devices is similar for these terminals.
5 PFI 6/AO START PFI 6/P1.6 E Series devices can drive each of these terminals with
TRIG (WFTRIG) one particular internal timing signal.
6 PFI 5/AO SAMP CLK PFI 5/P1.5 M Series devices can drive each terminal with the same
(UPDATE) signal as on E Series devices. On M Series devices, you
also can route many other internal timing signals to each
10 PFI 1/AI REF TRIG PFI 1/P1.1 terminal.
(TRIG2)
On M Series devices, you also can use these terminals as
37 PFI 8/CTR 0 SRC PFI 8/P2.0 digital I/O signals.
(GPCTR0_SOURCE)
Also refer to Chapter 8, PFI.
38 PFI 7/AI SAMP CLK PFI 7/P1.7
(STARTSCAN)
E Series M Series
Terminal Terminal* Terminal Differences
11 PFI 0/AI START TRIG PFI 0/P1.0 On E Series devices, as an input, this terminal can either
(TRIG1) be a PFI input or the analog trigger input.
39 D GND PFI 15/P2.7 On E Series devices, this is one of the D GND terminals.
On M Series devices, this is the PFI 15/P2.7 terminal.
* In NI-DAQmx, National Instruments has revised terminal names so they are easier to understand and more consistent
among National Instruments hardware and software products. This column shows the NI-DAQmx terminal names
(Traditional NI-DAQ (Legacy) terminal names are shown in parentheses).
+5 V Power Source
The +5 V terminals on the I/O connector supply +5 V referenced to
D GND. Use these terminals to power external circuitry. A self-resetting
fuse protects the supply from overcurrent conditions. The fuse resets
automatically within a few seconds after the overcurrent condition is
removed.
Caution Never connect the +5 V power terminals to analog or digital ground or to any
other voltage source on the M Series device or any other device. Doing so can damage the
device and the computer. NI is not liable for damage resulting from such a connection.
Refer to the specifications document for your device to obtain the device
power rating.
Note (NI PCIe-625x Devices Only) M Series PCI Express devices supply less than 1 A of
+5 V power unless you use the disk drive power connector.
However, you should install the disk drive power connector in either of the
following situations:
• You need more power than listed in the device specifications
• You are using an SCC accessory without an external power supply,
such as the SC-2345
Refer to the specifications document for your device for more information
about PCI Express power requirements and power limits.
Note The power available on the disk drive power connectors in a computer can vary. For
example, consider using a disk drive power connector that is not in the same power chain
as the hard drive.
2
1
4. Replace the computer cover, and plug in and power on the computer.
5. Self-calibrate the PCI Express DAQ device in MAX by following the
instructions in Calibrating DAQ Devices in the Measurement &
Automation Explorer Help.
Note Connecting or disconnecting the disk drive power connector can affect the analog
performance of your device. To compensate for this, NI recommends that you self-calibrate
after connecting or disconnecting the disk drive power connector.
(USB-62xx Screw Terminal Devices) To remove the fuse from the USB-62xx
Screw Terminal, complete the following steps.
1. Power down and unplug the device.
2. Loosen the four Phillips screws that attach the back lid to the
enclosure, and remove the lid.
3. Replace the fuse while referring to Figure 3-2 for the fuse location.
Fuse
(USB-62xx BNC Devices) To remove the fuse from the USB-62xx BNC,
complete the following steps.
1. Power down and unplug the device.
Fuse
2. Remove both end pieces by unscrewing the four sockethead cap screws
with a 7/64 in. hex wrench.
Note The end pieces are attached using self-threading screws. Repeated screwing and
unscrewing of self-threading screws will produce a compromised connection.
(USB-62xx Mass Termination Devices) To remove the fuse from the USB-62xx
Mass Termination, complete the following steps.
1. Power down and unplug the device.
2. Loosen the four Phillips screws that attach the lid to the enclosure, and
remove the lid.
3. Replace the fuse while referring to Figure 3-4 for the fuse location.
Fuse
LED Patterns
(USB-62xx Devices Only) All variants of M Series USB devices have LEDs
labeled ACTIVE and READY. The ACTIVE LED indicates activity over
the bus. The READY LED indicates whether or not the device is
configured. Table 3-3 shows the behavior of the LEDs.
NoteUSB-62xx BNC devices also have a POWER (+5 V) LED on the top panel. The
POWER (+5 V) LED indicates device power.
AI <0..n>
I/O Connector
Mux
DIFF, RSE, AI Lowpass
NI-PGIA ADC AI FIFO AI Data
or NRSE Filter
AI SENSE
Input Range
AI GND Selection
AI Terminal
Configuration
Selection
The main blocks featured in the M Series analog input circuitry are as
follows:
• I/O Connector—You can connect analog input signals to the M Series
device through the I/O connector. The proper way to connect analog
input signals depends on the analog input ground-reference settings,
described in the Analog Input Ground-Reference Settings section. Also
refer to Appendix A, Device-Specific Information, for device I/O
connector pinouts.
• MUX—Each M Series device has one analog-to-digital converter
(ADC). The multiplexers (MUX) route one AI channel at a time to the
ADC through the NI-PGIA.
• Ground-Reference Settings—The analog input ground-reference
settings circuitry selects between differential, referenced single-ended,
and non-referenced single-ended input modes. Each AI channel can
use a different mode.
• Instrumentation Amplifier (NI-PGIA)—The NI programmable gain
instrumentation amplifier (NI-PGIA) is a measurement and instrument
class amplifier that minimizes settling times for all input ranges. The
The input range affects the resolution of the M Series device for an AI
channel. Resolution refers to the voltage of one ADC code. For example, a
16-bit ADC converts analog inputs into one of 65,536 (= 216) codes—that
is, one of 65,536 possible digital values. These values are spread fairly
evenly across the input range. So, for an input range of –10 V to 10 V, the
voltage of each code of a 16-bit ADC is:
Choose an input range that matches the expected input range of your signal.
A large input range can accommodate a large signal variation, but reduces
the voltage resolution. Choosing a smaller input range improves the voltage
resolution, but may result in the input signal going out of range.
For more information about setting ranges, refer to the NI-DAQmx Help or
the LabVIEW Help in version 8.0 or later.
Tables 4-1, 4-2, and 4-3 show the input ranges and resolutions supported by
each M Series device family.
On some devices, the filter cutoff is fixed. On other devices, this filter is
programmable and can be enabled for a lower frequency. For example, the
NI 628x devices have a programmable filter with a cutoff frequency of
40 kHz that can be enabled. If the programmable filter is not enabled, the
cutoff frequency is fixed at 750 kHz. If the cutoff is programmable, choose
the lower cutoff to reduce measurement noise. However, a filter with a
lower cutoff frequency increases the settling time of your device, as shown
in the specifications, which reduces its maximum conversion rate.
Therefore, you may have to reduce the rate of your AI Convert and AI
Sample Clocks. If that reduced sample rate is too slow for your application,
select the higher cutoff frequency.
AI Ground-Reference
Settings Description
DIFF In differential (DIFF) mode, the M Series device measures the
difference in voltage between two AI signals.
RSE In referenced single-ended (RSE) mode, the M Series device measures
the voltage of an AI signal relative to AI GND.
NRSE In non-referenced single-ended (NRSE) mode, the M Series device
measures the voltage of an AI signal relative to one of the AI SENSE or
AI SENSE 2 inputs.
Instrumentation
Amplifier
Vin+
PGIA +
Vin– Vm Measured
Voltage
–
Notice that some M Series devices do not support the AI <16..79> signals.
Caution The maximum input voltages rating of AI signals with respect to ground (and for
differential signals with respect to each other) are listed in the specifications document for
your device. Exceeding the maximum input voltage of AI signals distorts the measurement
results. Exceeding the maximum input voltage rating also can damage the device and the
computer. NI is not liable for any damage resulting from such signal connections.
To configure the input mode of your voltage measurement using the DAQ
Assistant, use the Terminal Configuration drop-down list. Refer to the
DAQ Assistant Help for more information about the DAQ Assistant.
ADC. The specifications document for your DAQ device lists its settling
time.
M Series devices are designed to have fast settling times. However, several
factors can increase the settling time which decreases the accuracy of your
measurements. To ensure fast settling times, you should do the following
(in order of importance):
• Use Low Impedance Sources
• Use Short High-Quality Cabling
• Carefully Choose the Channel Scanning Order
• Avoid Scanning Faster Than Necessary
If your source impedance is high, you can decrease the scan rate to allow
the NI-PGIA more time to settle. Another option is to use a voltage follower
circuit external to your DAQ device to decrease the impedance seen by the
DAQ device. Refer to the KnowledgeBase document, How Do I Create a
Buffer to Decrease the Source Impedance of My Analog Input Signal?,
by going to ni.com/info and entering the info code rdbbis.
When the multiplexer switches from channel 0 to channel 1, the input to the
NI-PGIA switches from 4 V to 1 mV. The approximately 4 V step from 4 V
to 1 mV is 1,000% of the new full-scale range. For a 16-bit device to settle
within 0.0015% (15 ppm or 1 LSB) of the ±200 mV full-scale range on
channel 1, the input circuitry must settle to within 0.000031% (0.31 ppm or
1/50 LSB) of the ±10 V range. Some devices can take many microseconds
for the circuitry to settle this much.
To avoid this effect, you should arrange your channel scanning order so that
transitions from large to small input ranges are infrequent.
In general, you do not need this extra settling time when the NI-PGIA is
switching from a small input range to a larger input range.
You can connect channel 2 to AI GND (or you can use the internal ground
signal; refer to Internal Channels in the NI-DAQmx Help). Set the input
range of channel 2 to –200 mV to 200 mV to match channel 1. Then scan
channels in the order: 0, 2, 1.
Example 1
Averaging many AI samples can increase the accuracy of the reading by
decreasing noise effects. In general, the more points you average, the more
accurate the final result. However, you may choose to decrease the number
of points you average and slow down the scanning rate.
Example 2
If the time relationship between channels is not critical, you can sample
from the same channel multiple times and scan less frequently. For
example, suppose an application requires averaging 100 points from
channel 0 and averaging 100 points from channel 1. You could alternate
reading between channels—that is, read one point from channel 0, then one
point from channel 1, and so on. You also could read all 100 points from
channel 0 then read 100 points from channel 1. The second method
switches between channels much less often and is affected much less by
settling time.
Software-Timed Acquisitions
With a software-timed acquisition, software controls the rate of the
acquisition. Software sends a separate command to the hardware to initiate
each ADC conversion. In NI-DAQmx, software-timed acquisitions are
referred to as having on-demand timing. Software-timed acquisitions are
also referred to as immediate or static acquisitions and are typically used
for reading a single sample of data.
Hardware-Timed Acquisitions
With hardware-timed acquisitions, a digital hardware signal
(ai/SampleClock) controls the rate of the acquisition. This signal can be
generated internally on your device or provided externally.
Buffered
In a buffered acquisition, data is moved from the DAQ device’s onboard
FIFO memory to a PC buffer using DMA or interrupts before it is
transferred to application memory. Buffered acquisitions typically allow
for much faster transfer rates than non-buffered acquisitions because data
is moved in large blocks, rather than one point at a time.
One property of buffered I/O operations is the sample mode. The sample
mode can be either finite or continuous.
If data cannot be transferred across the bus fast enough, the FIFO becomes
full. New acquisitions will overwrite data in the FIFO before it can be
transferred to host memory. The device generates an error in this case. With
continuous operations, if the user program does not read data out of the PC
buffer fast enough to keep up with the data transfer, the buffer could reach
an overflow condition, causing an error to be generated.
Non-Buffered
In non-buffered acquisitions, data is read directly from the FIFO on the
device. Typically, hardware-timed, non-buffered operations are used to
read single samples with known time increments between them.
An analog or digital trigger can initiate these actions. All M Series devices
support digital triggering, but some do not support analog triggering. To
find your device triggering options, refer to the specifications document for
your device.
AI+ AI+
+ +
+ +
– AI– – AI–
– –
AI GND
AI GND
AI SENSE AI SENSE
AI GND
AI GND
*Refer to the Analog Input Ground-Reference Settings section for descriptions of the RSE, NRSE, and DIFF modes and
software considerations.
† Refer to the Connecting Ground-Referenced Signal Sources section for more information.
DIFF input connections are recommended for greater signal integrity for
any input signal that does not meet the preceding conditions.
With this type of connection, the NI-PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground.
DIFF input connections are recommended for greater signal integrity for
any input signal that does not meet the preceding conditions.
With this type of connection, the NI-PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground.
out of the maximum working voltage range of the NI-PGIA and the DAQ
device returns erroneous data.
AI+
Floating +
Signal Vs
Source –
AI–
Inpedance
<100 Ω AI SENSE
AI GND
Figure 4-4. Differential Connections for Floating Signal Sources without Bias Resistors
However, for larger source impedances, this connection leaves the DIFF
signal path significantly off balance. Noise that couples electrostatically
onto the positive line does not couple onto the negative line because it is
connected to ground. This noise appears as a DIFF-mode signal instead of
a common-mode signal, and thus appears in your data. In this case, instead
of directly connecting the negative line to AI GND, connect the negative
line to AI GND through a resistor that is about 100 times the equivalent
source impedance. The resistor puts the signal path nearly in balance,
so that about the same amount of noise couples onto both connections,
yielding better rejection of electrostatically coupled noise. This
configuration does not load down the source (other than the very high input
impedance of the NI-PGIA).
AI+
Floating +
Signal Vs
Source –
AI–
R is about R AI SENSE
100 times
source AI GND
impedance
of sensor
You can fully balance the signal path by connecting another resistor of
the same value between the positive input and AI GND, as shown in
Figure 4-6. This fully balanced configuration offers slightly better noise
rejection, but has the disadvantage of loading the source down with the
series combination (sum) of the two resistors. If, for example, the source
impedance is 2 kΩ and each of the two resistors is 100 kΩ, the resistors
load down the source with 200 kΩ and produce a –1% gain error.
AI+
Bias
Resistors
(see text)
+
Floating Instrumentation
Signal Vs Amplifier
Source +
–
PGIA
+
AI–
– Measured
Vm
Voltage
–
Bias
Current
Return
Paths
Input Multiplexers
AI SENSE
AI GND
I/O Connector
Both inputs of the NI-PGIA require a DC path to ground in order for the
NI-PGIA to work. If the source is AC coupled (capacitively coupled), the
NI-PGIA needs a resistor between the positive input and AI GND. If the
source has low-impedance, choose a resistor that is large enough not to
significantly load the source but small enough not to produce significant
input offset voltage as a result of input bias current (typically 100 kΩ to
1 MΩ). In this case, connect the negative input directly to AI GND. If the
source has high output impedance, balance the signal path as previously
described using the same value resistor on both the positive and negative
inputs; be aware that there is some gain error from loading down the source,
as shown in Figure 4-7.
AC Coupling
AC Coupled AI+
Floating +
Signal Vs
Source –
AI–
AI SENSE
AI GND
Figure 4-8 shows a floating source connected to the DAQ device in NRSE
mode.
AI
Floating +
Signal Vs
Source –
AI SENSE
R
AI GND
rejection of NRSE mode is better than RSE mode because the AI SENSE
connection is made remotely near the source. However, the noise rejection
of NRSE mode is worse than DIFF mode because the AI SENSE
connection is shared with all channels rather than being cabled in a twisted
pair with the AI+ signal.
Using the DAQ Assistant, you can configure the channels for RSE or NRSE
input modes. Refer to the Configuring AI Ground-Reference Settings in
Software section for more information about the DAQ Assistant.
AI <0..n>
Programmable Gain
Floating + Instrumentation
+
Signal Vs Amplifier
Source – PGIA +
Input Multiplexers
AI SENSE – Vm Measured
Voltage
–
AI GND
I/O Connector
Selected Channel in RSE Configuration
Using the DAQ Assistant, you can configure the channels for RSE or NRSE
input modes. Refer to the Configuring AI Ground-Reference Settings in
Software section for more information about the DAQ Assistant.
DIFF input connections are recommended for greater signal integrity for
any input signal that does not meet the preceding conditions.
With this type of connection, the NI-PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground.
AI+
Ground-
Referenced +
Instrumentation
Signal Vs Amplifier
+
Source –
PGIA +
AI–
– Vm Measured
Voltage
Common- –
+
Mode
Vcm
Noise and
Ground –
Potential
Input Multiplexers
AI SENSE
AI GND
I/O Connector
M Series Device Configured in DIFF Mode
With this type of connection, the NI-PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground, shown as Vcm in the figure.
I/O Connector
AI <0..15>
or AI <16..n>
Ground- Instrumentation
+
Referenced + Amplifier
Vs
Signal
Source –
PGIA +
Input Multiplexers
Common- – Vm Measured
+ AI SENSE Voltage
Mode
Vcm AI GND or AI SENSE 2
Noise –
and Ground –
Potential
Any potential difference between the device ground and the signal ground
appears as a common-mode signal at both the positive and negative inputs
of the NI-PGIA, and this difference is rejected by the amplifier. If the input
circuitry of a device were referenced to ground, as it is in the RSE
ground-reference setting, this difference in ground potentials would appear
as an error in the measured voltage.
Using the DAQ Assistant, you can configure the channels for RSE or NRSE
input modes. Refer to the Configuring AI Ground-Reference Settings in
Software section for more information about the DAQ Assistant.
PFI, RTSI
PXI_STAR
PFI, RTSI Analog Comparison Event
ai/SampleClock
Ctr n Internal Output
PXI_STAR
ai/SampleClock SW Pulse
Analog Comparison Timebase Programmable
Event
Clock
20 MHz Timebase Divider
PXI_CLK10 PXI_STAR
Analog Comparison Event
ai/ConvertClock
Ctr n Internal Output
ai/ConvertClock
Timebase Programmable
Clock
Divider
Channel 0
Channel 1
Convert Period
Sample Period
Typically, this rate is the sampling rate for the task multiplied by the
number of channels in the task.
Note The sampling rate is the fastest you can acquire data on the device and still achieve
accurate results. For example, if an M Series device has a sampling rate of 250 kS/s, this
sampling rate is aggregate—one channel at 250 kS/s or two channels at 125 kS/s per
channel illustrates the relationship.
Posttriggered data acquisition allows you to view only data that is acquired
after a trigger event is received. A typical posttriggered DAQ sequence is
shown in Figure 4-14. The sample counter is loaded with the specified
number of posttrigger samples, in this example, five. The value decrements
with each pulse on ai/SampleClock, until the value reaches zero and all
desired samples have been acquired.
ai/StartTrigger
ai/SampleClock
ai/ConvertClock
Sample Counter 4 3 2 1 0
Pretriggered data acquisition allows you to view data that is acquired before
the trigger of interest, in addition to data acquired after the trigger.
Figure 4-15 shows a typical pretriggered DAQ sequence. ai/StartTrigger
can be either a hardware or software signal. If ai/StartTrigger is set up to be
a software start trigger, an output pulse appears on the ai/StartTrigger line
when the acquisition begins. When the ai/StartTrigger pulse occurs, the
sample counter is loaded with the number of pretriggered samples, in this
example, four. The value decrements with each pulse on ai/SampleClock,
until the value reaches zero. The sample counter is then loaded with the
number of posttriggered samples, in this example, three.
ai/StartTrigger
ai/ReferenceTrigger n/a
ai/SampleClock
ai/ConvertClock
Scan Counter 3 2 1 0 2 2 2 1 0
You can specify an internal or external source for ai/SampleClock. You also
can specify whether the measurement sample begins on the rising edge or
falling edge of ai/SampleClock.
You can specify the output to have one of two behaviors. With the pulse
behavior, your DAQ device briefly pulses the PFI terminal once for every
occurrence of ai/SampleClock.
With level behavior, your DAQ device drives the PFI terminal high during
the entire sample.
ai/SampleClockTimebase
ai/StartTrigger
ai/SampleClock
Delay
From
Start
Trigger
With NI-DAQmx 7.4 and later, the driver chooses the fastest conversion
rate possible based on the speed of the A/D converter and adds 10 µs of
padding between each channel to allow for adequate settling time. This
scheme enables the channels to approximate simultaneous sampling and
still allow for adequate settling time. If the AI Sample Clock rate is too fast
to allow for this 10 µs of padding, NI-DAQmx chooses the conversion rate
so that the AI Convert Clock pulses are evenly spaced throughout the
sample.
Caution Setting the conversion rate higher than the maximum rate specified for your
device will result in errors.
ai/ConvertClockTimebase
ai/SampleClock
ai/ConvertClock
Delay Convert
From Period
Sample
Clock
ai/SampleClock
ai/ConvertClock
Channel Measured 0 1 2 3 0 1 2 3 0 1 2 3
Sample #1 Sample #2 Sample #3
ai/SampleClock
ai/ConvertClock
Channel Measured 0 1 2 3 0 1 2 3 0 1 2 3
Sample #1 Sample #2 Sample #3
ai/SampleClock
ai/ConvertClock
Channel Measured 0 1 2 3 0 1 2 3 0
Sample #1 Sample #2 Sample #3
ai/SampleClock
ai/ConvertClock
Channel Measured 0 1 2 3 0 1 2 3 0 1 2 3
Sample #1 Sample #2 Sample #3
ai/SampleClock
ai/ConvertClock
Channel Measured 0 1 2 3 0 1 2 3 0 1 …
Sample #1 Sample #2 Sample #3
The source also can be one of several other internal signals on your DAQ
device. Refer to Device Routing in MAX in the NI-DAQmx Help or the
LabVIEW Help in version 8.0 or later for more information.
You also can specify whether the measurement acquisition begins on the
rising edge or falling edge of ai/StartTrigger.
Once the acquisition begins, the DAQ device writes samples to the buffer.
After the DAQ device captures the specified number of pretrigger samples,
the DAQ device begins to look for the reference trigger condition. If the
reference trigger condition occurs before the DAQ device captures the
specified number of pretrigger samples, the DAQ device ignores the
condition.
If the buffer becomes full, the DAQ device continuously discards the oldest
samples in the buffer to make space for the next sample. This data can be
accessed (with some limitations) before the DAQ device discards it. Refer
to the KnowledgeBase document, Can a Pretriggered Acquisition be
Continuous?, for more information. To access this KnowledgeBase, go to
ni.com/info and enter the info code rdcanq.
When the reference trigger occurs, the DAQ device continues to write
samples to the buffer until the buffer contains the number of posttrigger
samples desired. Figure 4-23 shows the final buffer.
Reference Trigger
Complete Buffer
The source also can be one of several internal signals on your DAQ device.
Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW
Help in version 8.0 or later for more information.
You also can specify whether the measurement acquisition stops on the
rising edge or falling edge of ai/ReferenceTrigger.
The source also can be one of several other internal signals on your DAQ
device. Refer to Device Routing in MAX in the NI-DAQmx Help or the
LabVIEW Help in version 8.0 or later for more information.
Note Pause triggers are only sensitive to the level of the source, not the edge.
Note For more information about programming analog input applications and triggers in
software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
AO 0 DAC0
AO 1 DAC1
AO FIFO AO Data
AO 2 DAC2
AO 3 DAC3
AO Sample Clock
AO Offset Select
AO Reference Select
The main blocks featured in the M Series analog output circuitry are as
follows:
• DACs—Digital-to-analog converters (DACs) convert digital codes to
analog voltages.
• AO FIFO—The AO FIFO enables analog output waveform
generation. It is a first-in-first-out (FIFO) memory buffer between the
computer and the DACs. It allows you to download the points of a
waveform to your M Series device without host computer interaction.
The possible settings for AO reference depend on the device model. For
models not described below, refer to the specifications for your device.
You can use one of the AO <0..3> signals to be the AO reference for a
different AO signal. However, you must externally connect this channel to
APFI 0 or APFI 1.
(NI 628x Devices) On NI 628x devices, the AO offset of each analog output
can be individually set to one of the following:
• 0 V (AO GND)
• 5V
• APFI <0..1>
• AO <0..3>
You can connect an external signal to APFI <0..1> to provide the AO offset.
You can route the output of one of the AO <0..3> signals to be the AO offset
for a different AO <0..3> signal. For example, AO 0 can be routed to be the
AO offset of AO 1. This route is done on the device; no external
connections are required.
You can route the output of one of the AO <0..3> signals to be the AO
reference for a different AO <0..3> signal. For example, AO 0 can be
routed to be the AO reference of AO 1. This route is done on the device;
no external connections are required.
Software-Timed Generations
With a software-timed generation, software controls the rate at which data
is generated. Software sends a separate command to the hardware to initiate
each DAC conversion. In NI-DAQmx, software-timed generations are
referred to as on-demand timing. Software-timed generations are also
referred to as immediate or static operations. They are typically used for
writing a single value out, such as a constant DC voltage.
Hardware-Timed Generations
With a hardware-timed generation, a digital hardware signal controls the
rate of the generation. This signal can be generated internally on your
device or provided externally.
Non-Buffered
In non-buffered acquisitions, data is written directly to the DACs on the
device. Typically, hardware-timed, non-buffered operations are used to
write single samples with good latency and known time increments
between them.
Buffered
In a buffered acquisition, data is moved from a PC buffer to the DAQ
device’s onboard FIFO using DMA or interrupts for NI
PCI/PCIe/PXI/PXIe devices or USB Signal Streams for USB devices
before it is written to the DACs one sample at a time. Buffered acquisitions
typically allow for much faster transfer rates than non-buffered acquisitions
because data is moved in large blocks, rather than one point at a time.
One property of buffered I/O operations is the sample mode. The sample
mode can be either finite or continuous.
With FIFO regeneration, the entire buffer is downloaded to the FIFO and
regenerated from there. Once the data is downloaded, new data cannot be
written to the FIFO. To use FIFO regeneration, the entire buffer must fit
within the FIFO size. The advantage of using FIFO regeneration is that it
does not require communication with the main host memory once the
operation is started, thereby preventing any problems that may occur due to
excessive bus traffic.
With non-regeneration, old data will not be repeated. New data must be
continually written to the buffer. If the program does not write new data to
the buffer at a fast enough rate to keep up with the generation, the buffer
will underflow and cause an error.
An analog or digital trigger can initiate these actions. All M Series devices
support digital triggering, but some do not support analog triggering. To
find your device’s triggering options, refer to the specifications document
for your device. Refer to the AO Start Trigger Signal and AO Pause Trigger
Signal sections for more information about these triggering actions.
AO 0 AO 2
+ Channel 0 + Channel 2
Load V OUT Load V OUT
– –
AO GND AO GND
– –
Load V OUT Load V OUT
+ AO 1 + AO 3
Channel 1 Channel 3
Connector 0 (AI 0–15) M Series Device Connector 1 (AI 16–31) M Series Device
PFI, RTSI
PXI_STAR
PFI, RTSI Analog Comparison Event
ao/SampleClock
Ctr n Internal Output
PXI_STAR
ao/SampleClock
Analog Comparison
Timebase Programmable
Event
Clock
20 MHz Timebase Divider
PXI_CLK10
• ai/ReferenceTrigger
• ai/StartTrigger
• PXI_STAR
The source also can be one of several internal signals on your DAQ device.
Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW
Help in version 8.0 or later for more information.
You also can specify whether the waveform generation begins on the rising
edge or falling edge of ao/StartTrigger.
ao/PauseTrigger does not stop a sample that is in progress. The pause does
not take effect until the beginning of the next sample.
When you generate analog output signals, the generation pauses as soon as
the pause trigger is asserted. If the source of your sample clock is the
onboard clock, the generation resumes as soon as the pause trigger is
deasserted, as shown in Figure 5-4.
Pause Trigger
Sample Clock
If you are using any signal other than the onboard clock as the source of
your sample clock, the generation resumes as soon as the pause trigger is
deasserted and another edge of the sample clock is received, as shown in
Figure 5-5.
Pause Trigger
Sample Clock
The source also can be one of several other internal signals on your DAQ
device. Refer to Device Routing in MAX in the NI-DAQmx Help or the
LabVIEW Help in version 8.0 or later for more information.
You also can specify whether the samples are paused when ao/PauseTrigger
is at a logic high or low level.
ao/SampleClockTimebase
ao/StartTrigger
ao/SampleClock
Delay
From
Start
Trigger
You can route any of the following signals to be the AO Sample Clock
Timebase (ao/SampleClockTimebase) signal:
• 20 MHz Timebase
• 100 kHz Timebase
• PXI_CLK10
• PFI <0..15>
• RTSI <0..7>
• PXI_STAR
• Analog Comparison Event (an analog trigger)
Note For more information about programming analog output applications and triggers in
software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Figure 6-1 shows the circuitry of one DIO line. Each DIO line is similar.
The following sections provide information about the various parts of the
DIO circuit.
DO Waveform
Generation FIFO
DO Sample Clock
Static DO
Buffer
I/O Protection P0.x
DO.x Direction Control
DI Waveform
Measurement
FIFO
DI Sample Clock
DI Change
Detection
The DIO terminals are named P0.<0..31> on the M Series device I/O
connector.
The voltage input and output levels and the current drive levels of the DIO
lines are listed in the specifications of your device.
Static DIO
Each of the M Series DIO lines can be used as a static DI or DO line. You
can use static DIO lines to monitor or control digital signals. Each DIO can
be individually configured as a digital input (DI) or digital output (DO).
P0.6 and P0.7 on 68-pin M Series devices also can control the up/down
input of general-purpose counters 0 and 1, respectively. However, it is
recommended that you use PFI signals to control the up/down input of the
counters. The up/down control signals, Counter 0 Up_Down and Counter 1
Up_Down, are input-only and do not affect the operation of the DIO lines.
For example, consider the case where you are using AI Sample Clock as the
source of DI Sample Clock. To initiate pulses on AI Sample Clock (and
therefore on DI Sample Clock), you use AI Start Trigger to trigger the start
of an AI operation. The AI Start Trigger causes the M Series device to
begin generating AI Sample clock pulses, which in turn generates DI
Sample clock pulses, as shown in Figure 6-2.
AI Sample Clock
DI Sample Clock
If you are using a Counter output as the source of DI Sample Clock, the
counter’s start trigger, enables the counter which drives DI Sample Clock.
If you are using an external signal (such as PFI x) as the source for DI
Sample Clock or DO Sample Clock, you must trigger that external signal.
You can configure each DIO line to be an output, a static input, or a digital
waveform acquisition input.
• PXI_STAR
• Analog Comparison Event (an analog trigger)
The FIFO supports a retransmit mode. In the retransmit mode, after all the
samples in the FIFO have been clocked out, the FIFO begins outputting all
of the samples again in the same order. For example, if the FIFO contains
five samples, the pattern generated consists of sample #1, #2, #3, #4, #5,
#1, #2, #3, #4, #5, #1, and so on.
You must ensure that the time between two active edges of do/SampleClock
is not too short. If the time is too short, the DO waveform generation FIFO
is not able to read the next sample fast enough. The DAQ device reports an
overrun error to the host software.
I/O Protection
Each DIO and PFI signal is protected against overvoltage, undervoltage,
and overcurrent conditions as well as ESD events. However, you should
avoid these fault conditions by following these guidelines.
• If you configure a PFI or DIO line as an output, do not connect it to any
external signal source, ground signal, or power supply.
• If you configure a PFI or DIO line as an output, understand the current
requirements of the load connected to these signals. Do not exceed the
specified current output limits of the DAQ device. NI has several signal
conditioning solutions for digital applications requiring high current
drive.
• If you configure a PFI or DIO line as an input, do not drive the line with
voltages outside of its normal operating range. The PFI or DIO lines
have a smaller operating range than the AI signals.
• Treat the DAQ device as you would treat any static sensitive device.
Always properly ground yourself and the equipment when handling
the DAQ device or connecting to it.
NI-DAQmx 7.4 and later supports programmable power-up states for PFI
and DIO lines. Software can program any value at power up to the P0, P1,
or P2 lines. The PFI and DIO lines can be set as:
• A high-impedance input with a weak pull-down resistor (default)
• An output driving a 0
• An output driving a 1
Refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later
for more information about setting power-up states in NI-DAQmx or MAX.
Note When using your M Series device to control an SCXI chassis, DIO lines 0, 1, 2, and
4 are used as communication lines and must be left to power-up in the default
high-impedance state to avoid potential damage to these signals.
DI Change Detection
You can configure the DAQ device to detect changes in the DIO signals.
Figure 6-3 shows a block diagram of the DIO change detection circuitry.
Enable
P0.0 Synch
Enable
Change Detection Event
Enable
P0.31 Synch
Enable
You can enable the DIO change detection circuitry to detect rising edges,
falling edges, or either edge individually on each DIO line. The DAQ
devices synchronize each DI signal to 80MHzTimebase, and then sends the
signal to the change detectors. The circuitry ORs the output of all enabled
change detectors from every DI signal. The result of this OR is the Change
Detection Event signal.
The Change Detection Event signal also can be used to detect changes on
digital output events.
Applications
The DIO change detection circuitry can interrupt a user program when one
of several DIO signals changes state.
You also can use the output of the DIO change detection circuitry to trigger
a DI or counter acquisition on the logical OR of several digital signals. To
trigger on a single digital signal, refer to the Triggering with a Digital
Source section of Chapter 11, Triggering. By routing the Change Detection
Event signal to a counter, you also can capture the relative time between
samples.
You also can use the Change Detection Event signal to trigger DO or
counter generations.
+5 V
LED
P1.<4..7>
TTL Signal
P1.<0..3>
+5 V
Switch
D GND
I/O Connector
M Series Device
Caution Exceeding the maximum input voltage ratings, which are listed in the
specifications document for each M Series device, can damage the DAQ device and the
computer. NI is not liable for any damage resulting from such signal connections.
Note For more information about programming digital I/O applications and triggers in
software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Counter 0 Gate
Counter 0 Internal Output
Counter 0 Aux
Counter 0 HW Arm
Counter 0 A
Counter 0 TC
Counter 0 B (Counter 0 Up_Down)
Counter 0 Z
Counter 1 Gate
Counter 0 Internal Output
Counter 1 Aux
Counter 1 HW Arm
Counter 1 A
Counter 0 TC
Counter 1 B (Counter 1 Up_Down)
Counter 1 Z
The counters have seven input signals, although in most applications only
a few inputs are used.
Counter Armed
SOURCE
Counter Value 0 1 2 3 4 5
You also can use a pause trigger to pause (or gate) the counter. When the
pause trigger is active, the counter ignores edges on its Source input. When
the pause trigger is inactive, the counter counts edges normally.
You can route the pause trigger to the Gate input of the counter. You can
configure the counter to pause counting when the pause trigger is high or
when it is low. Figure 7-3 shows an example of on-demand edge counting
with a pause trigger.
Counter Armed
Pause Trigger
(Pause When Low)
SOURCE
Counter Value 0 0 1 2 3 4 5
Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger
The count values returned are the cumulative counts since the counter
armed event. That is, the sample clock does not reset the counter.
You can route the counter sample clock to the Gate input of the counter. You
can configure the counter to sample on the rising or falling edge of the
sample clock.
Counter Armed
Sample Clock
(Sample on Rising Edge)
SOURCE
Counter Value 0 1 2 3 4 5 6 7
3 3
6
Buffer
Pulse-Width Measurement
In pulse-width measurements, the counter measures the width of a pulse on
its Gate input signal. You can configure the counter to measure the width of
high pulses or low pulses on the Gate signal.
You can route an internal or external periodic clock signal (with a known
period) to the Source input of the counter. The counter counts the number
of rising (or falling) edges on the Source signal while the pulse on the Gate
signal is active.
You can calculate the pulse width by multiplying the period of the Source
signal by the number of edges returned by the counter.
GATE
SOURCE
Counter Value 0 1 2
HW Save Register 2
The counter counts the number of edges on the Source input while the Gate
input remains active. On each trailing edge of the Gate signal, the counter
stores the count in a hardware save register. A DMA controller transfers the
stored values to host memory.
GATE
SOURCE
Counter Value 0 1 2 3 1 2
3 3
2
Buffer 3 2
Note that if you are using an external signal as the Source, at least one
Source pulse should occur between each active edge of the Gate signal.
This condition ensures that correct values are returned by the counter. If this
Period Measurement
In period measurements, the counter measures a period on its Gate input
signal after the counter is armed. You can configure the counter to measure
the period between two rising edges or two falling edges of the Gate input
signal.
You can route an internal or external periodic clock signal (with a known
period) to the Source input of the counter. The counter counts the number
of rising (or falling) edges occurring on the Source input between the
two active edges of the Gate signal.
You can calculate the period of the Gate input by multiplying the period of
the Source signal by the number of edges returned by the counter.
GATE
SOURCE
Counter Value 0 1 2 3 4 5
HW Save Register 5
The counter counts the number of rising (or falling) edges on the Source
input between each pair of active edges on the Gate input. At the end of
each period on the Gate signal, the counter stores the count in a hardware
save register. A DMA controller transfers the stored values to host memory.
The counter begins when it is armed. The arm usually occurs in the middle
of a period of the Gate input. So the first value stored in the hardware save
register does not reflect a full period of the Gate input. In most applications,
this first point should be discarded.
Counter Armed
GATE
SOURCE
Counter Value 1 2 1 2 3 1 2 3 1
2 2 (Discard) 3 2 (Discard) 3 2 (Discard)
3 3
Buffer 3
Note that if you are using an external signal as the Source, at least one
Source pulse should occur between each active edge of the Gate signal.
This condition ensures that correct values are returned by the counter. If this
condition is not met, consider using duplicate count prevention, described
in the Duplicate Count Prevention section.
Semi-Period Measurement
In semi-period measurements, the counter measures a semi-period on its
Gate input signal after the counter is armed. A semi-period is the time
between any two consecutive edges on the Gate input.
You can route an internal or external periodic clock signal (with a known
period) to the Source input of the counter. The counter counts the number
of rising (or falling) edges occurring on the Source input between
two edges of the Gate signal.
You can calculate the semi-period of the Gate input by multiplying the
period of the Source signal by the number of edges returned by the counter.
The counter begins counting when it is armed. The arm usually occurs
between edges on the Gate input. So the first value stored in the hardware
save register does not reflect a full semi-period of the Gate input. In most
applications, this first point should be discarded.
Counter Armed
GATE
SOURCE
Counter Value 0 1 2 1 2 3 1 1 2 1
2 2 3 2 12 22
Buffer 3 3 3
1 1
2
Note that if you are using an external signal as the Source, at least one
Source pulse should occur between each active edge of the Gate signal.
This condition ensures that correct values are returned by the counter. If this
condition is not met, consider using duplicate count prevention, described
in the Duplicate Count Prevention section.
Frequency Measurement
You can use the counters to measure frequency in several different ways.
You can choose one of the following methods depending on your
application.
You can route the signal to measure (F1) to the Gate of a counter. You can
route a known timebase (Ft) to the Source of the counter. The known
timebase can be 80MHzTimebase. For signals that might be slower than
0.02 Hz, use a slower known timebase.
You can configure the counter to measure one period of the gate signal. The
frequency of F1 is the inverse of the period. Figure 7-10 illustrates this
method.
Interval Measured
F1
F1 Gate
1 2 3 … … N
Ft Source Ft
Single Period N
Period of F1 =
Measurement Ft
Ft
Frequency of F1 =
N
You can route the signal to measure (F1) to the Gate of a counter. You can
route a known timebase (Ft) to the Source of the counter. The known
timebase can be 80MHzTimebase. For signals that might be slower than
0.02 Hz, use a slower known timebase.
Intervals Measured
T1 T2 … TK
F1 Gate
F1
In this method, you route a pulse of known duration (T) to the Gate of a
counter. You can generate the pulse using a second counter. You also can
generate the pulse externally and connect it to a PFI or RTSI terminal. You
only need to use one counter if you generate the pulse externally.
Route the signal to measure (F1) to the Source of the counter. Configure the
counter for a single pulse-width measurement. Suppose you measure the
width of pulse T to be N periods of F1. Then the frequency of F1 is N/T.
Pulse
Pulse Gate
1 2 … N
F1 Source F1
Pulse-Width Width of T = N
Measurement Pulse F1
N
Frequency of F1 =
T
You can route the signal to measure to the Source input of Counter 0, as
shown in Figure 7-13. Assume this signal to measure has frequency F1.
Configure Counter 0 to generate a single pulse that is the width of N periods
of the source input signal.
GATE
0 1 2 3 … N
CTR_0_SOURCE
(Signal to Measure)
CTR_0_OUT
(CTR_1_GATE) Interval
to Measure
CTR_1_SOURCE
Then route the Counter 0 Internal Output signal to the Gate input of
Counter 1. You can route a signal of known frequency (F2) to the Counter 1
Source input. F2 can be 80MHzTimebase. For signals that might be slower
than 0.02 Hz, use a slower known timebase. Configure Counter 1 to
perform a single pulse-width measurement. Suppose the result is that the
pulse width is J periods of the F2 clock.
From Counter 0, the length of the pulse is N/F1. From Counter 1, the length
of the same pulse is J/F2. Therefore, the frequency of F1 is given by
F1 = F2 * (N/J).
Position Measurement
You can use the counters to perform position measurements with
quadrature encoders or two-pulse encoders. You can measure angular
position with X1, X2, and X4 angular encoders. Linear position can be
measured with two-pulse encoders. You can choose to do either a single
point (on-demand) position measurement or a buffered (sample clock)
position measurement. You must arm a counter to begin position
measurements.
X1 Encoding
When channel A leads channel B in a quadrature cycle, the counter
increments. When channel B leads channel A in a quadrature cycle, the
counter decrements. The amount of increments and decrements per cycle
depends on the type of encoding—X1, X2, or X4.
Figure 7-14 shows a quadrature cycle and the resulting increments and
decrements for X1 encoding. When channel A leads channel B, the
increment occurs on the rising edge of channel A. When channel B leads
channel A, the decrement occurs on the falling edge of channel A.
Ch A
Ch B
Counter Value 5 6 7 7 6 5
X2 Encoding
The same behavior holds for X2 encoding except the counter increments or
decrements on each edge of channel A, depending on which channel leads
the other. Each cycle results in two increments or decrements, as shown in
Figure 7-15.
Ch A
Ch B
Counter Value 5 6 7 8 9 9 8 7 6 5
X4 Encoding
Similarly, the counter increments or decrements on each edge of
channels A and B for X4 encoding. Whether the counter increments or
decrements depends on which channel leads the other. Each cycle results in
four increments or decrements, as shown in Figure 7-16.
Ch A
Ch B
Counter Value 5 6 7 8 9 10 11 12 13 13 12 11 10 9 8 7 6 5
Channel Z Behavior
Some quadrature encoders have a third channel, channel Z, which is also
referred to as the index channel. A high level on channel Z causes the
counter to be reloaded with a specified value in a specified phase of the
quadrature cycle. You can program this reload to occur in any one of the
four phases in a quadrature cycle.
In Figure 7-17, the reload phase is when both channel A and channel B are
low. The reload occurs when this phase is true and channel Z is high.
Incrementing and decrementing takes priority over reloading. Thus, when
the channel B goes low to enter the reload phase, the increment occurs first.
The reload occurs within one maximum timebase period after the reload
phase becomes true. After the reload occurs, the counter continues to count
as before. The figure illustrates channel Z reload with X4 decoding.
Ch A
Ch B
Ch Z
Max Timebase
Counter Value 5 6 7 8 9 0 1 2 3 4
A=0
B=0
Z=1
Ch A
Ch B
Counter Value 2 3 4 5 4 3 4
After the counter has been armed and an active edge occurs on the Aux
input, the counter counts the number of rising (or falling) edges on the
Source. The counter ignores additional edges on the Aux input.
The counter stops counting upon receiving an active edge on the Gate input.
The counter stores the count in a hardware save register.
You can configure the rising or falling edge of the Aux input to be the active
edge. You can configure the rising or falling edge of the Gate input to be
the active edge.
Use this type of measurement to count events or measure the time that
occurs between edges on two signals. This type of measurement is
sometimes referred to as start/stop trigger measurement, second gate
measurement, or A-to-B measurement.
Counter
Armed
Measured Interval
AUX
GATE
SOURCE
Counter Value 0 0 0 0 1 2 3 4 5 6 7 8 8 8
HW Save Register 8
The counter counts the number of rising (or falling) edges on the Source
input occurring between an active edge of the Gate signal and an active
edge of the Aux signal. The counter then stores the count in a hardware save
register. On the next active edge of the Gate signal, the counter begins
another measurement. A DMA controller transfers the stored values to host
memory.
AUX
GATE
SOURCE
Counter Value 1 2 3 1 2 3 1 2 3
3 3 3
3 3
Buffer 3
You can specify a delay from when the counter is armed to the beginning
of the pulse. The delay is measured in terms of a number of active edges of
the Source input.
You can specify a pulse width. The pulse width is also measured in terms
of a number of active edges of the Source input. You also can specify the
active edge of the Source input (rising or falling).
Figure 7-21 shows a generation of a pulse with a pulse delay of four and a
pulse width of three (using the rising edge of Source).
Counter Armed
SOURCE
OUT
You can route the Start Trigger signal to the Gate input of the counter. You
can specify a delay from the Start Trigger to the beginning of the pulse. You
also can specify the pulse width. The delay and pulse width are measured
in terms of a number of active edges of the Source input.
After the Start Trigger signal pulses once, the counter ignores the Gate
input.
Figure 7-22 shows a generation of a pulse with a pulse delay of four and a
pulse width of three (using the rising edge of Source).
GATE
(Start Trigger)
SOURCE
OUT
You can route the Start Trigger signal to the Gate input of the counter. You
can specify a delay from the Start Trigger to the beginning of each pulse.
You also can specify the pulse width. The delay and pulse width are
measured in terms of a number of active edges of the Source input.
The counter ignores the Gate input while a pulse generation is in progress.
After the pulse generation is finished, the counter waits for another Start
Trigger signal to begin another pulse generation.
Figure 7-23 shows a generation of two pulses with a pulse delay of five and
a pulse width of three (using the rising edge of Source).
GATE
(Start Trigger)
SOURCE
OUT
You can specify a delay from when the counter is armed to the beginning
of the pulse train. The delay is measured in terms of a number of active
edges of the Source input.
You specify the high and low pulse widths of the output signal. The pulse
widths are also measured in terms of a number of active edges of the Source
input. You also can specify the active edge of the Source input (rising or
falling).
The counter can begin the pulse train generation as soon as the counter is
armed, or in response to a hardware Start Trigger. You can route the Start
Trigger to the Gate input of the counter.
You also can use the Gate input of the counter as a Pause Trigger (if it is not
used as a Start Trigger). The counter pauses pulse generation when the
Pause Trigger is active.
Figure 7-24 shows a continuous pulse train generation (using the rising
edge of Source).
SOURCE
OUT
Counter Armed
Frequency Generation
You can generate a frequency by using a counter in pulse train generation
mode or by using the frequency generator circuit.
Frequency
Output
20 MHz Timebase ÷2 Timebase
Frequency Generator FREQ OUT
Divisor
(1–16)
Figure 7-26 shows the output waveform of the frequency generator when
the divider is set to 5.
Frequency
Output
Timebase
FREQ OUT
(Divisor = 5)
Frequency Output can be routed out to any PFI <0..15> or RTSI <0..7>
terminal. All PFI terminals are set to high-impedance at startup. The FREQ
OUT signal also can be routed to DO Sample Clock and DI Sample Clock.
Frequency Division
The counters can generate a signal with a frequency that is a fraction of an
input signal. This function is equivalent to continuous pulse train
generation.
The increase in the delay value can be between 0 and 255. For instance, if
you specify the increment to be 10, the delay between the active Gate edge
and the pulse on the output will increase by 10 every time a new pulse is
generated.
Suppose you program your counter to generate pulses with a delay of 100
and pulse width of 200 each time it receives a trigger. Furthermore, suppose
you specify the delay increment to be 10. On the first trigger, your pulse
delay will be 100, on the second it will be 110, on the third it will be 120;
the process will repeat in this manner until the counter is disarmed. The
counter ignores any Gate edge that is received while the pulse triggered by
the previous Gate edge is in progress.
The waveform thus produced at the counter’s output can be used to provide
timing for undersampling applications where a digitizing system can
sample repetitive waveforms that are higher in frequency than the Nyquist
frequency of the system. Figure 7-27 shows an example of pulse generation
for ETS; the delay from the trigger to the pulse increases after each
subsequent Gate active edge.
GATE
OUT
D1 D2 = D1 + ΔD D3 = D1 + 2ΔD
To begin any counter input or output function, you must first enable, or arm,
the counter. In some applications, such as buffered semi-period
measurement, the counter begins counting when it is armed. In other
applications, such as single pulse-width measurement, the counter begins
waiting for the Gate signal when it is armed. Counter output operations can
use the arm signal in addition to a start trigger.
With pulse or pulse train generation tasks, the counter drives the pulse(s) on
the Counter n Internal Output signal. The Counter n Internal Output signal
can be internally routed to be a counter/timer input or an “external” source
for AI, AO, DI, or DO timing signals.
You can use these defaults or select other sources and destinations for the
counter/timer signals in NI-DAQmx. Refer to Connecting Counter Signals
in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for
more information about how to connect your signals for common counter
measurements and generations. M Series default PFI lines for counter
functions are listed in Physical Channels in the NI-DAQmx Help or the
LabVIEW Help in version 8.0 or later.
Counter Triggering
Counters support three different triggering actions—arm start, start, and
pause.
For counter output operations, you can use it in addition to the start and
pause triggers. For counter input operations, you can use the arm start
trigger to have start trigger-like behavior. The arm start trigger can be used
for synchronizing multiple counter input and output tasks.
When using an arm start trigger, the arm start trigger source is routed to the
Counter n HW Arm signal.
Start Trigger
For counter output operations, a start trigger can be configured to begin a
finite or continuous pulse generation. Once a continuous generation has
triggered, the pulses continue to generate until you stop the operation in
software. For finite generations, the specified number of pulses is generated
and the generation stops unless you use the retriggerable attribute. When
you use this attribute, subsequent start triggers cause the generation to
restart.
When using a start trigger, the start trigger source is routed to the Counter
n Gate signal input of the counter.
Counter input operations can use the arm start trigger to have start
trigger-like behavior.
Pause Trigger
You can use pause triggers in edge counting and continuous pulse
generation applications. For edge counting acquisitions, the counter stops
counting edges while the external trigger signal is low and resumes when
the signal goes high or vice versa. For continuous pulse generations, the
counter stops generating pulses while the external trigger signal is low and
resumes when the signal goes high or vice versa.
When using a pause trigger, the pause trigger source is routed to the
Counter n Gate signal input of the counter.
Counter Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or
PXI_STAR signal. When the filters are enabled, your device samples the
input on each rising edge of a filter clock. M Series devices use an onboard
oscillator to generate the filter clock with a 40 MHz frequency.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 7-5.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 7-28 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal Filtered input goes
high when terminal
Filter Clock 1 1 2 3 4 1 2 3 4 5 is sampled high on
(40 MHz) five consecutive filter
clocks.
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting, the
jitter is up to 10.025 µs.
Prescaling
Prescaling allows the counter to count a signal that is faster than the
maximum timebase of the counter. M Series devices offer 8X and 2X
prescaling on each counter (prescaling can be disabled). Each prescaler
consists of a small, simple counter that counts to eight (or two) and rolls
over. This counter can run faster than the larger counters, which simply
count the rollovers of this smaller counter. Thus, the prescaler acts as a
frequency divider on the Source and puts out a frequency that is one-eighth
(or one-half) of what it is accepting.
External Signal
Prescaler Rollover
(Used as Source
by Counter)
Counter Value 0 1
Rising Edge
of Gate
Counter detects rising
edge of Gate on the next
rising edge of Source.
Gate
Source
Counter Value 6 7 1 2 1
Buffer 7 2
7
On the first rising edge of the Gate, the current count of 7 is stored. On the
next rising edge of the Gate, the counter stores a 2 since two Source pulses
occurred after the previous rising edge of Gate.
The counter synchronizes or samples the Gate signal with the Source
signal, so the counter does not detect a rising edge in the Gate until the next
Source pulse. In this example, the counter stores the values in the buffer on
the first rising Source edge after the rising edge of Gate. The details of
when exactly the counter synchronizes the Gate signal vary depending on
the synchronization mode. Synchronization modes are described in the
Synchronization Modes section.
No Source edge, so no
value written to buffer.
Gate
Source
Counter Value 6 7 1
Buffer 7
Counter detects
rising Gate edge. Counter value
increments only
Gate one time for each
Source pulse.
Source
80 MHz Timebase
Counter Value 6 7 0 1
Buffer 7 0
7
Even if the Source pulses are long, the counter increments only once for
each Source pulse.
Normally, the counter value and Counter n Internal Output signals change
synchronously to the Source signal. With duplicate count prevention, the
counter value and Counter n Internal Output signals change synchronously
to the 80 MHz Timebase.
Note that duplicate count prevention should only be used if the frequency
of the Source signal is 20 MHz or less.
In all other cases, you should not use duplicate count prevention.
Synchronization Modes
The 32-bit counter counts up or down synchronously with the Source
signal. The Gate signal and other counter inputs are asynchronous to the
Source signal. So M Series devices synchronize these signals before
presenting them to the internal counter.
In DAQmx, the device uses 80 MHz source mode if you perform the
following:
• Perform a position measurement
• Select duplicate count prevention
Otherwise, the mode depends on the signal that drives Counter n Source.
Table 7-6 describes the conditions for each mode.
Source
Synchronize Count
Source
Synchronize Count
Source
Synchronize
Delayed Source
Count
Each PFI input also has a programmable debouncing filter. Figure 8-1
shows the circuitry of one PFI line. Each PFI line is similar.
Timing Signals
Static DO
Buffer
Static DI
Weak Pull-Down
To Input Timing
Signal Selectors PFI
Filters
The voltage input and output levels and the current drive levels of the PFI
signals are listed in the specifications of your device.
Most functions allow you to configure the polarity of PFI inputs and
whether the input is edge or level sensitive.
Note Signals with a * are inverted before being driven to a terminal; that is, these signals
are active low.
PFI 0
PFI 2
PFI 0 PFI 2
Source Source
D GND
I/O Connector
M Series Device
PFI Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or
PXI_STAR signal. When the filters are enabled, your device samples the
input on each rising edge of a filter clock. M Series devices use an onboard
oscillator to generate the filter clock with a 40 MHz frequency.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 8-1.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 8-3 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal Filtered input goes
high when terminal
Filter Clock 1 1 2 3 4 1 2 3 4 5 is sampled high on
(40 MHz) five consecutive filter
clocks.
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025 µs.
I/O Protection
Each DIO and PFI signal is protected against overvoltage, undervoltage,
and overcurrent conditions as well as ESD events. However, you should
avoid these fault conditions by following these guidelines.
• If you configure a PFI or DIO line as an output, do not connect it to any
external signal source, ground signal, or power supply.
• If you configure a PFI or DIO line as an output, understand the current
requirements of the load connected to these signals. Do not exceed the
specified current output limits of the DAQ device. NI has several signal
conditioning solutions for digital applications requiring high current
drive.
• If you configure a PFI or DIO line as an input, do not drive the line with
voltages outside of its normal operating range. The PFI or DIO lines
have a smaller operating range than the AI signals.
• Treat the DAQ device as you would treat any static sensitive device.
Always properly ground yourself and the equipment when handling the
DAQ device or connecting to it.
NI-DAQmx 7.4 and later supports programmable power-up states for PFI
and DIO lines. Software can program any value at power up to the P0, P1,
or P2 lines. The PFI and DIO lines can be set as:
• A high-impedance input with a weak pull-down resistor (default)
• An output driving a 0
• An output driving a 1
Refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later
for more information about setting power-up states in NI-DAQmx or MAX.
Note When using your M Series device to control an SCXI chassis, DIO lines 0, 1, 2, and
4 are used as communication lines and must be left to power-up in the default
high-impedance state to avoid potential damage to these signals.
Clock Routing
Figure 9-1 shows the clock routing circuitry of an M Series device.
External
80 MHz Timebase
Reference
RTSI <0..7> Clock PLL
PXI_CLK10 ÷4 20 MHz Timebase
PXI_STAR
÷ 200 100 kHz Timebase
80 MHz Timebase
The 80 MHz Timebase can be used as the Source input to the 32-bit
general-purpose counter/timers.
20 MHz Timebase
The 20 MHz Timebase normally generates many of the AI and AO timing
signals. The 20 MHz Timebase also can be used as the Source input to the
32-bit general-purpose counter/timers.
The following signals can be routed to drive the external reference clock.
• RTSI <0..7>
• PXI_CLK10
• PXI_STAR
All devices (including the initiator device) receive the 10 MHz reference
clock from RTSI. This signal becomes the external reference clock. A PLL
on each device generates the internal timebases synchronous to the external
reference clock.
Once all of the devices are using or referencing a common timebase, you
can synchronize operations across them by sending a common start trigger
out across the RTSI bus and setting their sample clock rates to the same
value.
In a PCI system, the RTSI bus consists of the RTSI bus interface and a
ribbon cable. The bus can route timing and trigger signals between several
functions on as many as five DAQ, vision, motion, or CAN devices in the
computer.
In a PXI system, the RTSI bus consists of the RTSI bus interface and the
PXI trigger signals on the PXI backplane. This bus can route timing and
trigger signals between several functions on as many as seven DAQ devices
in the system.
Terminal 34
Terminal 33
Terminal 2
Terminal 1
Note Signals with a * are inverted before being driven on the RTSI terminals.
Most functions allow you to configure the polarity of PFI inputs and
whether the input is edge or level sensitive.
RTSI Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or
PXI_STAR signal. When the filters are enabled, your device samples the
input on each rising edge of a filter clock. M Series devices use an onboard
oscillator to generate the filter clock with a 40 MHz frequency.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 9-2.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 9-3 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal Filtered input goes
high when terminal
Filter Clock 1 1 2 3 4 1 2 3 4 5 is sampled high on
(40 MHz) five consecutive filter
clocks.
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025 µs.
Note PXI clock and trigger signals are only available on PXI/PXI Express devices.
PXI_CLK10
PXI_CLK10 is a common low-skew 10 MHz reference clock for
synchronization of multiple modules in a PXI measurement or control
system. The PXI backplane is responsible for generating PXI_CLK10
independently to each peripheral slot in a PXI chassis.
PXI Triggers
A PXI chassis provides eight bused trigger lines to each module in a
system. Triggers may be passed from one module to another, allowing
precisely timed responses to asynchronous external events that are being
monitored or controlled. Triggers can be used to synchronize the operation
of several different PXI peripheral modules.
On M Series devices, the eight PXI trigger signals are synonymous with
RTSI <0..7>.
Note that in a PXI chassis with more than eight slots, the PXI trigger lines
may be divided into multiple independent buses. Refer to the
documentation for your chassis for details.
PXI_STAR Trigger
In a PXI system, the Star Trigger bus implements a dedicated trigger line
between the first peripheral slot (adjacent to the system slot) and the other
peripheral slots. The Star Trigger can be used to synchronize multiple
devices or to share a common trigger signal among devices.
PXI_STAR Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or
PXI_STAR signal. When the filters are enabled, your device samples the
input on each rising edge of a filter clock. M Series devices use an onboard
oscillator to generate the filter clock with a 40 MHz frequency.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 9-3.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 9-4 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal Filtered input goes
high when terminal
Filter Clock 1 1 2 3 4 1 2 3 4 5 is sampled high on
(40 MHz) five consecutive filter
clocks.
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025 µs.
Each DMA controller supports packing and unpacking of data through the
FIFOs to connect different size devices and optimize PCI bus utilization
and automatically handles unaligned memory buffers.
M Series USB devices have four fully-independent USB Signal Stream for
high-performance transfers of data blocks. These channels are assigned to
the first four measurement/acquisition circuits that request one.
PXI Considerations
Note PXI clock and trigger signals are only available on PXI devices.
3U designates devices that are 100 mm tall (as opposed to the taller
6U modules).
Peripheral devices are installed in peripheral slots and are not system
controllers.
1 For some PXI M Series devices, there are two variants—one that will work in PXI hybrid slots and one that supports local bus
for SCXI control when the device is in the right-most slot. Refer to the device specifications for more information.
Caution Damage can result if these lines are driven by the sub-bus. NI is not liable for any
damage resulting from improper signal connections.
(USB Devices) The two primary ways to transfer data across the USB bus are
USB Signal Stream and programmed I/O:
• USB Signal Stream—USB Signal Stream is a method to transfer data
between the device and computer memory using USB bulk transfers
without intervention of the microcontroller on the NI device. NI uses
USB Signal Stream hardware and software technology to achieve high
throughput rates and increase system utilization in USB devices.
• Programmed I/O—Programmed I/O is a data transfer mechanism
where the user’s program is responsible for transferring data. Each
read or write call in the program initiates the transfer of data.
Programmed I/O is typically used in software-timed (on-demand)
(USB Devices) USB M Series devices have four dedicated USB Signal
Stream channels. These channels are assigned to the first four
measurement/acquisition circuits that request one. If a USB Signal Stream
is not available, you must set the data transfer mechanism to programmed
I/O; otherwise the driver returns an error. To change your data transfer
mechanism between USB Signal Stream and programmed I/O, use the
Data Transfer Mechanism property node function in NI-DAQmx.
Note Not all M Series devices support analog triggering. For more information about
triggering compatibility, refer to the specifications document for your device.
The edge can be either the rising edge or falling edge of the digital signal.
A rising edge is a transition from a low logic level to a high logic level.
A falling edge is a high to low transition.
5V
Digital Trigger
0V
You also can program your DAQ device to perform an action in response to
a trigger from a digital source. The action can affect the following:
• Analog input acquisition
• Analog output generation
• Counter behavior
• Digital waveform acquisition and generation
Analog +
Input PGIA ADC
Channels –
AI Circuitry
Analog Comparison
Analog Event
Mux Trigger AO Circuitry
APFI <0..1> Detection (Analog Trigger
Circuitry Output)
Counter Circuitry
You must specify a source and an analog trigger type. The source can be
either an APFI <0..1> terminal or an analog input channel.
When the DAQ device is waiting for an analog trigger with a AI channel as
the source, the AI muxes should not route different AI channels to the
NI-PGIA. If a different channel is routed to the NI-PGIA, the trigger
condition on the desired channel could be missed. The other channels also
could generate false triggers.
Level
Level
For the trigger to assert, the signal must first be below the low threshold,
then go above the high threshold. The trigger stays asserted until the signal
returns below the low threshold. The output of the trigger detection
circuitry is the internal Analog Comparison Event signal, as shown in
Figure 11-5.
High threshold
(Level)
Hysteresis
Low threshold
First signal must go (Level – Hysteresis)
below low threshold
Analog Comparison Event
Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example
For the trigger to assert, the signal must first be above the high threshold,
then go below the low threshold. The trigger stays asserted until the signal
returns above the high threshold. The output of the trigger detection
circuitry is the internal Analog Comparison Event signal, as shown in
Figure 11-6.
High threshold
(Level + Hysteresis)
Hysteresis
Low threshold
(Level)
Then signal must go below low threshold
before Analog Comparison Event asserts
Analog Comparison Event
Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example
Figure 11-7 demonstrates a trigger that asserts when the signal enters the
window.
Top
Bottom
NI 6220
PCI/PXI-6220 Pinout
Figure A-1 shows the pinout of the PCI/PXI-6220.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 NC
NC 55 21 NC
NC 54 20 NC
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6220 Specifications
Refer to the NI 622x Specifications for more detailed information about the
PCI/PXI-6220 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6221
The following sections contain information about the PCI/PXI-6221
(68-pin), PCI-6221 (37-pin), USB-6221 Screw Terminal, and USB-6221
BNC devices.
PCI/PXI-6221 (68-Pin)
PCI/PXI-6221 (68-Pin) Pinout
Figure A-2 shows the pinout of the PCI/PXI-6221 (68-pin) device.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 AO 0
AO GND 55 21 AO 1
AO GND 54 20 NC
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
PCI-6221 (37-Pin)
PCI-6221 (37-Pin) Pinout
Figure A-3 shows the pinout of the PCI-6221 (37-pin) device.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
AI 0 1
20 AI 8
AI 9 2
21 AI 1
AI GND 3
22 AI 2
AI 10 4
23 AI 11
AI 3 5
24 AI GND
AI 4 6
25 AI 12
AI 13 7
26 AI 5
AI SENSE 8
27 AI 6
AI 14 9
28 AI 7
AI 15 10
29 NC
AO GND 11
30 AO 1
AO 0 12
31 AO GND
PFI 0/P1.0 13
32 PFI 1/P1.1
D GND 14
33 PFI 2/P1.2
PFI 3/P1.3 15
34 PFI 4/P1.4
D GND 16
35 PFI 5/P1.5
PFI 6/P1.6 17
36 PFI 7/P1.7
D GND 18
37 P0.0
P0.1 19
NC = No Connect
CTR 0 A 13 (PFI 0)
CTR 0 Z 32 (PFI 1)
CTR 0 B 33 (PFI 2)
CTR 1 A 15 (PFI 3)
CTR 1 Z 34 (PFI 4)
CTR 1 B 35 (PFI 5)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices.
Cables
In most applications, you can use the following cables:
• SH37F-37M-1—37-pin female-to-male shielded I/O cable, 1 m
• SH37F-37M-2—37-pin female-to-male shielded I/O cable, 2 m
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
17 AI 4 81 PFI 8/P2.0
AI 0 1 P0.0 65
18 AI 12 82 D GND
AI 8 2 P0.1 66
19 AI GND 83 PFI 9/P2.1
AI GND 3 P0.2 67
20 AI 5 84 D GND
AI 1 4 P0.3 68
21 AI 13 85 PFI 10/P2.2
AI 9 5 P0.4 69
22 AI GND 86 D GND
AI GND 6 P0.5 70
23 AI 6 87 PFI 11/P2.3
AI 2 7 P0.6 71
24 AI 14 88 D GND
AI 10 8 P0.7 72
25 AI GND 89 PFI 12/P2.4
AI GND 9 PFI 0/P1.0 73
26 AI 7 90 D GND
AI 3 10 PFI 1/P1.1 74
27 AI 15 91 PFI 13/P2.5
AI 11 11 PFI 2/P1.2 75
28 AI GND 92 D GND
AI GND 12 PFI 3/P1.3 76
29 NC 93 PFI 14/P2.6
AI SENSE 13 PFI 4/P1.4 77
30 AI GND 94 D GND
AI GND 14 PFI 5/P1.5 78
31 AO 1 95 PFI 15/P2.7
AO 0 15 PFI 6/P1.6 79
32 AO GND 96 +5 V
AO GND 16 PFI 7/P1.7 80
NC = No Connect
CTR 0 A 81 (PFI 8)
CTR 0 Z 83 (PFI 9)
CTR 1 A 76 (PFI 3)
CTR 1 Z 77 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
USB-6221 BNC
USB-6221 BNC Pinout
Figure A-5 shows the pinout of the USB-6221 BNC.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
CTR 0 A PFI 8
CTR 0 Z PFI 9
CTR 0 B PFI 10
CTR 1 A PFI 3
CTR 1 Z PFI 4
CTR 1 B PFI 11
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Differential Signals
To connect differential signals, determine the type of signal source you are
using—a floating signal (FS) source or a ground-referenced signal (GS)
source. Refer to the Connecting Analog Input Signals section of Chapter 4,
Analog Input, for more information.
AI 0
FS GS
Figure A-7 shows the analog input circuitry on the USB-6221 BNC. When
the switch is in the FS position, AI x – is grounded through a 0.1 µF
capacitor in parallel with a 5 kΩ resistor.
AI x + AI x +
+ +
– –
AI x – AI x –
GS GS
FS FS
0.1 µF 5 kΩ 0.1 µF 5 kΩ
AI GND AI GND
USB-62xx Device USB-62xx Device
Floating Source Grounded Source
Single-Ended Signals
For each BNC connector that you use for two single-ended channels, set the
source type switch to the GS position. This setting disconnects the built-in
ground reference resistor from the negative terminal of the BNC connector,
allowing the connector to be used as a single-ended channel, as shown in
Figure A-8.
AI x
+
– AI x+8
Ground Ref.
Source (GS)
USB-62xx BNC Device
When you set the source type to the GS position and software-configure the
device for single-ended input, each BNC connector provides access to two
single-ended channels, AI x and AI x+8. For example, the BNC connector
labeled AI 0 provides access to single-ended channels AI 0 and AI 8, the
BNC connector labeled AI 1 provides access to single-ended channels AI 1
and AI 9, and so on. Up to 16 single-ended channels are available in
single-ended measurement modes.
Analog Output
You can access analog output signals on the BNC connectors labeled AO 0
and AO 1. Figure A-9 shows the analog output circuitry on the USB-6221
BNC.
AO x
AO GND
PFI x/P1.x
D GND
D GND D GND
USER 1
USER 2 Internal Connection
D GND
+5 V
D GND
P0.0
P0.1 Screw
P0.2 Terminal
P0.3 Block
D GND
P0.4
P0.5
P0.6
P0.7
D GND
PFI 8/P2.0
Figure A-12 shows an example of how to use the USER 1 and USER 2
BNCs. To access the PFI 8 signal from a BNC, connect USER 1 on the
screw terminal block to PFI 8 with a wire.
USER 1 BNC
USER 1
USER 2
D GND
+5 V
D GND
P0.0
P0.1
P0.2
PFI 8 Wire
P0.3
Signal D GND
P0.4
P0.5
P0.6
P0.7 Screw
D GND Terminal
PFI 8/P2.0 Block
The designated space below each USER <1..2> BNC is for marking or
labeling signal names.
NI 6224
PCI/PXI-6224 Pinout
Figure A-13 shows the pinout of the PCI/PXI-6224. The I/O signals appear
on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 35 D GND 12 46 P0.27
AI GND 56 22 NC D GND 13 47 P0.11
TERMINAL 34 TERMINAL 1
NC 55 21 NC +5 V 14 48 P0.15
NC 54 20 NC D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND NC 20 54 NC
P0.7 48 14 +5 V TERMINAL 1 TERMINAL 34 NC 21 55 NC
P0.3 47 13 D GND NC 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6224 Specifications
Refer to the NI 622x Specifications for more detailed information about the
PCI/PXI-6224 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6225
The following sections contain information about the PCI/PXI-6225,
USB-6225 Screw Terminal, and USB-6225 Mass Termination devices.
PCI/PXI-6225
PCI/PXI-6225 Pinout
Figure A-14 shows the pinout of the PCI/PXI-6225.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 AI 71 1 35 AI 79
AI GND 67 33 AI 1 AI 78 2 36 AI 70
AI 9 66 32 AI GND AI 69 3 37 AI 77
AI 2 65 31 AI 10 AI 68 4 38 AI 76
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 AI 75 5 39 AI 67
(AI 16-79)
(AI 0-15)
AI 11 63 29 AI GND AI 66 6 40 AI 74
AI SENSE 62 28 AI 4 AI 65 7 41 AI 73
AI 12 61 27 AI GND AI 72 8 42 AI 64
AI 5 60 26 AI 13 AI GND 9 43 AI GND
AI GND 59 25 AI 6 AI 55 10 44 AI 63
AI 14 58 24 AI GND AI 54 11 45 AI 62
AI 7 57 23 AI 15 AI 61 12 46 AI 53
TERMINAL 68 TERMINAL 35
AI GND 56 22 AO 0 AI 52 13 47 AI 60
AO GND 55 21 AO 1 TERMINAL 34 TERMINAL 1 AI 51 14 48 AI 59
AO GND 54 20 NC AI 58 15 49 AI 50
D GND 53 19 P0.4 AI 49 16 50 AI 57
P0.0 52 18 D GND AI 48 17 51 AI 56
P0.5 51 17 P0.1 AI 47 18 52 AI 39
D GND 50 16 P0.6 AI 38 19 53 AI 46
P0.2 49 15 D GND AI 37 20 54 AI 45
P0.7 48 14 +5 V AI 44 21 55 AI 36
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND AI GND 22 56 AI SENSE 2
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 35 23 57 AI 43
PFI 10/P2.2 45 11 PFI 0/P1.0 AI 34 24 58 AI 42
D GND 44 10 PFI 1/P1.1 AI 41 25 59 AI 33
PFI 2/P1.2 43 9 D GND AI 32 26 60 AI 40
PFI 3/P1.3 42 8 +5 V AI 23 27 61 AI 31
PFI 4/P1.4 41 7 D GND AI 30 28 62 AI 22
PFI 13/P2.5 40 6 PFI 5/P1.5 AI 21 29 63 AI 29
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 20 30 64 AI 28
PFI 7/P1.7 38 4 D GND AI 27 31 65 AI 19
PFI 8/P2.0 37 3 PFI 9/P2.1 AI 18 32 66 AI 26
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI 25
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6225 Specifications
Refer to the NI 622x Specifications for more detailed information about the
PCI/PXI-6225 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
Using a BNC Accessory with Connector 0
Connector 0 of your device is compatible with several BNC accessories:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one screw terminal accessory with the signals on either
connector of your PCI/PXI-6225 device. You can use two screw terminal
accessories with one M Series device by using both connectors.3
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
1 NI recommends that you use the SHC68-68 cable when the SCB-68 is connected to Connector 1.
2 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
3 The SCC-68 only can be used with Connector 0.
Cables
The PCI/PXI-6225 has two connectors that require different cables.
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note For a ground connection, you can connect the shield of a shielded cable to the
chassis ground lug, depicted in Figure A-15.
17 AI 8 49 AI 27
AI 0 1 AI 19 33
18 AI 9 50 AI 28
AI 1 2 AI 20 34
19 AI 10 51 AI 29
AI 2 3 AI 21 35
20 AI 11 52 AI 30
AI 3 4 AI 22 36
21 AI 12 53 AI GND
AI 4 5 AI GND 37
22 AI GND 54 AI 31
AI GND 6 AI 23 38
23 AI 13 55 AI 40
AI 5 7 AI 32 39
24 AI 14 56 AI 41
AI 6 8 AI 33 40
25 AI 15 57 AI 42
AI 7 9 AI 34 41
26 AI 24 58 AI 43
AI 16 10 AI 35 42
27 AI 25 59 AI 44
AI 17 11 AI 36 43
28 AI 26 60 AI SENSE 2
AI 18 12 AI GND 44
29 AI GND 61 AI 45
AI GND 13 AI 37 45
30 NC 62 AI 46
AI SENSE 14 AI 38 46
31 AO GND 63 AI 47
AO GND 15 AI 39 47
32 AO 1 64 AI 56
AO 0 16 AI 48 48
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 24 34 68 AI 16 AI 8 34 68 AI 0
AI 17 33 67 AI 25 AI 1 33 67 AI GND
AI 18 32 66 AI 26 AI GND 32 66 AI 9
AI 27 31 65 AI 19 AI 10 31 65 AI 2
AI 20 30 64 AI 28 AI 3 30 64 AI GND
AI 21 29 63 AI 29 AI GND 29 63 AI 11
AI 30 28 62 AI 22 AI 4 28 62 AI SENSE
AI 23 27 61 AI 31 AI GND 27 61 AI 12
AI 32 26 60 AI 40 AI 13 26 60 AI 5
AI 41 25 59 AI 33 AI 6 25 59 AI GND
AI 34 24 58 AI 42 AI GND 24 58 AI 14
AI 35 23 57 AI 43 AI 15 23 57 AI 7
AI GND 22 56 AI SENSE 2 AO 0 22 56 AI GND
AI 44 21 55 AI 36 AO 1 21 55 AO GND
AI 37 20 54 AI 45 NC 20 54 AO GND
AI 38 19 53 AI 46 P0.4 19 53 D GND
AI 47 18 52 AI 39 D GND 18 52 P0.0
AI 48 17 51 AI 56 P0.1 17 51 P0.5
AI 49 16 50 AI 57 P0.6 16 50 D GND
AI 58 15 49 AI 50 D GND 15 49 P0.2
AI 51 14 48 AI 59 +5 V 14 48 P0.7
AI 52 13 47 AI 60 D GND 13 47 P0.3
AI 61 12 46 AI 53 D GND 12 46 PFI 11/P2.3
AI 54 11 45 AI 62 PFI 0/P1.0 11 45 PFI 10/P2.2
AI 55 10 44 AI 63 PFI 1/P1.1 10 44 D GND
AI GND 9 43 AI GND D GND 9 43 PFI 2/P1.2
AI 72 8 42 AI 64 +5 V 8 42 PFI 3/P1.3
AI 65 7 41 AI 73 D GND 7 41 PFI 4/P1.4
AI 66 6 40 AI 74 PFI 5/P1.5 6 40 PFI 13/P2.5
AI 75 5 39 AI 67 PFI 6/P1.6 5 39 PFI 15/P2.7
AI 68 4 38 AI 76 D GND 4 38 PFI 7/P1.7
AI 69 3 37 AI 77 PFI 9/P2.1 3 37 PFI 8/P2.0
AI 78 2 36 AI 70 PFI 12/P2.4 2 36 D GND
AI 71 1 35 AI 79 PFI 14/P2.6 1 35 D GND
NC = No Connect
CONNECTOR 1 CONNECTOR 0
(AI 16–79) (AI 0–15)
TERMINAL 68 TERMINAL 35 TERMINAL 68 TERMINAL 35
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SH68-68-EP shielded cable.
BNC Accessories
Using a BNC Accessory with Connector 0
Connector 0 of your device is compatible with several BNC accessories:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one screw terminal accessory with the signals on either
connector of your USB-6225 Mass Termination device. You can use
two screw terminal accessories with one M Series device by using both
connectors.2
Cables
Choosing a Cable for Connector 0
In most applications, you can use the following cables with Connector 0:
• SH68-68-EP—High-performance cable with individual bundles
separating analog and digital signals. Each differential analog input
channel is routed on an individually shielded twisted pair of wires.
Analog outputs are also individually shielded
• R68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SH68-68-S cable when the SCB-68 is connected to Connector 1.
2 The SCC-68 only can be used with Connector 0.
NI 6229
The following sections contain information about the PCI/PXI-6229,
USB-6229 Screw Terminal, and USB-6229 BNC devices.
PCI/PXI-6229
PCI/PXI-6229 Pinout
Figure A-17 shows the pinout of the PCI/PXI-6229. The I/O signals appear
on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 D GND 12 46 P0.27
TERMINAL 68 TERMINAL 35
AI GND 56 22 AO 0 D GND 13 47 P0.11
AO GND 55 21 AO 1 TERMINAL 34 TERMINAL 1 +5 V 14 48 P0.15
AO GND 54 20 NC D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND NC 20 54 AO GND
P0.7 48 14 +5 V AO 3 21 55 AO GND
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND AO 2 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6229 Specifications
Refer to the NI 622x Specifications for more detailed information about the
PCI/PXI-6229 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
17 AI 4 49 AI 20
AI 0 1 AI 16 33
18 AI 12 50 AI 28
AI 8 2 AI 24 34
19 AI GND 51 AI GND
AI GND 3 AI GND 35
20 AI 5 52 AI 21
AI 1 4 AI 17 36
21 AI 13 53 AI 29
AI 9 5 AI 25 37
22 AI GND 54 AI GND
AI GND 6 AI GND 38
23 AI 6 55 AI 22
AI 2 7 AI 18 39
24 AI 14 56 AI 30
AI 10 8 AI 26 40
25 AI GND 57 AI GND
AI GND 9 AI GND 41
26 AI 7 58 AI 23
AI 3 10 AI 19 42
27 AI 15 59 AI 31
AI 11 11 AI 27 43
28 AI GND 60 AI GND
AI GND 12 AI GND 44
29 NC 61 NC
AI SENSE 13 AI SENSE 2 45
30 AI GND 62 AI GND
AI GND 14 AI GND 46
31 AO 1 63 AO 3
AO 0 15 AO 2 47
32 AO GND 64 AO GND
AO GND 16 AO GND 48
NC = No Connect NC = No Connect
CTR 0 A 81 (PFI 8)
CTR 0 Z 83 (PFI 9)
CTR 1 A 76 (PFI 3)
CTR 1 Z 77 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
USB-6229 BNC
USB-6229 BNC Pinout
Figure A-19 shows the pinout of the USB-6229 BNC.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
CTR 0 A PFI 8
CTR 0 Z PFI 9
CTR 0 B PFI 10
CTR 1 A PFI 3
CTR 1 Z PFI 4
CTR 1 B PFI 11
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Differential Signals
To connect differential signals, determine the type of signal source you are
using—a floating signal (FS) source or a ground-referenced signal (GS)
source. Refer to the Connecting Analog Input Signals section of Chapter 4,
Analog Input, for more information.
AI 0
FS GS
Figure A-21 shows the analog input circuitry on the USB-6229 BNC.
When the switch is in the FS position, AI x – is grounded through a 0.1 µF
capacitor in parallel with a 5 kΩ resistor.
AI x + AI x +
+ +
– –
AI x – AI x –
GS GS
FS FS
0.1 µF 5 kΩ 0.1 µF 5 kΩ
AI GND AI GND
USB-62xx Device USB-62xx Device
Floating Source Grounded Source
Single-Ended Signals
For each BNC connector that you use for two single-ended channels, set the
source type switch to the GS position. This setting disconnects the built-in
ground reference resistor from the negative terminal of the BNC connector,
allowing the connector to be used as a single-ended channel, as shown in
Figure A-22.
AI x
+
– AI x+8
Ground Ref.
Source (GS)
USB-62xx BNC Device
When you set the source type to the GS position and software-configure the
device for single-ended input, each BNC connector provides access to
two single-ended channels, AI x and AI x+8. For example, the BNC
connector labeled AI 0 provides access to single-ended channels AI 0 and
AI 8, the BNC connector labeled AI 1 provides access to single-ended
channels AI 1 and AI 9, and so on. Up to 32 single-ended channels are
available in single-ended measurement modes.
Analog Output
You can access analog output signals on the BNC connectors labeled AO 0
and AO 1. Figure A-23 shows the analog output circuitry on the USB-6229
BNC.
AO x
AO GND
PFI x/P1.x
D GND
D GND D GND
USER 1
USER 2 Internal Connection
D GND
+5 V
D GND
P0.0
P0.1 Screw
P0.2 Terminal
P0.3 Block
D GND
P0.4
P0.5
P0.6
P0.7
D GND
PFI 8/P2.0
Figure A-26 shows an example of how to use the USER 1 and USER 2
BNCs. To access the PFI 8 signal from a BNC, connect USER 1 on the
screw terminal block to PFI 8 with a wire.
USER 1 BNC
USER 1
USER 2
D GND
+5 V
D GND
P0.0
P0.1
P0.2
PFI 8 Wire
P0.3
Signal D GND
P0.4
P0.5
P0.6
P0.7 Screw
D GND Terminal
PFI 8/P2.0 Block
The designated space below each USER <1..2> BNC is for marking or
labeling signal names.
NI 6250
PCI/PXI-6250 Pinout
Figure A-27 shows the pinout of the PCI/PXI-6250.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 NC
NC 55 21 NC
NC 54 20 APFI 0
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6250 Specifications
Refer to the NI 625x Specifications for more detailed information about the
PCI/PXI-6250 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6251
The following sections contain information about the
NI PCI/PCIe/PXI/PXIe-6251, USB-6251 Screw Terminal, USB-6251
BNC, and USB-6251 Mass Termination devices.
NI PCI/PCIe/PXI/PXIe-6251
NI PCI/PCIe/PXI/PXIe-6251 Pinout
Figure A-28 shows the pinout of the NI PCI/PCIe/PXI/PXIe-6251.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 AO 0
AO GND 55 21 AO 1
AO GND 54 20 APFI 0
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
NI PCI/PCIe/PXI/PXIe-6251 Specifications
Refer to the NI 625x Specifications for more detailed information about the
NI PCI/PCIe/PXI/PXIe-6251 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
Note PCI Express users should consider the power limits on certain SCC modules without
an external power supply. Refer to the NI 625x Specifications, and the Disk Drive Power
Connector section of Chapter 3, Connector and LED Information, for information about
power limits and increasing the current the device can supply on the +5 V terminal.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI/PCI Express devices, such as M Series, E Series, CAN, and other
measurement, vision, and motion devices. Since PXI devices use PXI
backplane signals for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
17 AI 4 81 PFI 8/P2.0
AI 0 1 P0.0 65
18 AI 12 82 D GND
AI 8 2 P0.1 66
19 AI GND 83 PFI 9/P2.1
AI GND 3 P0.2 67
20 AI 5 84 D GND
AI 1 4 P0.3 68
21 AI 13 85 PFI 10/P2.2
AI 9 5 P0.4 69
22 AI GND 86 D GND
AI GND 6 P0.5 70
23 AI 6 87 PFI 11/P2.3
AI 2 7 P0.6 71
24 AI 14 88 D GND
AI 10 8 P0.7 72
25 AI GND 89 PFI 12/P2.4
AI GND 9 PFI 0/P1.0 73
26 AI 7 90 D GND
AI 3 10 PFI 1/P1.1 74
27 AI 15 91 PFI 13/P2.5
AI 11 11 PFI 2/P1.2 75
28 AI GND 92 D GND
AI GND 12 PFI 3/P1.3 76
29 APFI 0 93 PFI 14/P2.6
AI SENSE 13 PFI 4/P1.4 77
30 AI GND 94 D GND
AI GND 14 PFI 5/P1.5 78
31 AO 1 95 PFI 15/P2.7
AO 0 15 PFI 6/P1.6 79
32 AO GND 96 +5 V
AO GND 16 PFI 7/P1.7 80
CTR 0 A 81 (PFI 8)
CTR 0 Z 83 (PFI 9)
CTR 1 A 76 (PFI 3)
CTR 1 Z 77 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
USB-6251 BNC
USB-6251 BNC Pinout
Figure A-30 shows the pinout of the USB-6251 BNC.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
CTR 0 A PFI 8
CTR 0 Z PFI 9
CTR 0 B PFI 10
CTR 1 A PFI 3
CTR 1 Z PFI 4
CTR 1 B PFI 11
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Differential Signals
To connect differential signals, determine the type of signal source you are
using—a floating signal (FS) source or a ground-referenced signal (GS)
source. Refer to the Connecting Analog Input Signals section of Chapter 4,
Analog Input, for more information.
AI 0
FS GS
Figure A-32 shows the analog input circuitry on the USB-6251 BNC.
When the switch is in the FS position, AI x – is grounded through a 0.1 µF
capacitor in parallel with a 5 kΩ resistor.
AI x + AI x +
+ +
– –
AI x – AI x –
GS GS
FS FS
0.1 µF 5 kΩ 0.1 µF 5 kΩ
AI GND AI GND
USB-62xx Device USB-62xx Device
Floating Source Grounded Source
Single-Ended Signals
For each BNC connector that you use for two single-ended channels, set the
source type switch to the GS position. This setting disconnects the built-in
ground reference resistor from the negative terminal of the BNC connector,
allowing the connector to be used as a single-ended channel, as shown in
Figure A-33.
AI x
+
– AI x+8
Ground Ref.
Source (GS)
USB-62xx BNC Device
When you set the source type to the GS position and software-configure the
device for single-ended input, each BNC connector provides access to two
single-ended channels, AI x and AI x+8. For example, the BNC connector
labeled AI 0 provides access to single-ended channels AI 0 and AI 8, the
BNC connector labeled AI 1 provides access to single-ended channels AI 1
and AI 9, and so on. Up to 16 single-ended channels are available in
single-ended measurement modes.
Analog Output
You can access analog output signals on the BNC connectors labeled AO 0
and AO 1. Figure A-34 shows the analog output circuitry on the USB-6251
BNC.
AO x
AO GND
PFI x/P1.x
D GND
APFI
You can access the analog programmable function interface signal on the
BNC connector labeled APFI 0. Figure A-36 shows the APFI circuitry on
the USB-6251 BNC.
APFI x
AI GND
D GND D GND
USER 1
USER 2 Internal Connection
D GND
+5 V
D GND
P0.0
P0.1 Screw
P0.2 Terminal
P0.3 Block
D GND
P0.4
P0.5
P0.6
P0.7
D GND
PFI 8/P2.0
Figure A-38 shows an example of how to use the USER 1 and USER 2
BNCs. To access the PFI 8 signal from a BNC, connect USER 1 on the
screw terminal block to PFI 8 with a wire.
USER 1 BNC
USER 1
USER 2
D GND
+5 V
D GND
P0.0
P0.1
P0.2
PFI 8 Wire
P0.3
Signal D GND
P0.4
P0.5
P0.6
P0.7 Screw
D GND Terminal
PFI 8/P2.0 Block
The designated space below each USER <1..2> BNC is for marking or
labeling signal names.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 8 34 68 AI 0
AI 1 33 67 AI GND
AI GND 32 66 AI 9
AI 10 31 65 AI 2
AI 3 30 64 AI GND
AI GND 29 63 AI 11
AI 4 28 62 AI SENSE
AI GND 27 61 AI 12
AI 13 26 60 AI 5
AI 6 25 59 AI GND
AI GND 24 58 AI 14
AI 15 23 57 AI 7
AO 0 22 56 AI GND
AO 1 21 55 AO GND
APFI 0 20 54 AO GND
P0.4 19 53 D GND
D GND 18 52 P0.0
P0.1 17 51 P0.5
P0.6 16 50 D GND
D GND 15 49 P0.2
+5 V 14 48 P0.7
D GND 13 47 P0.3
D GND 12 46 PFI 11/P2.3
PFI 0/P1.0 11 45 PFI 10/P2.2
PFI 1/P1.1 10 44 D GND
D GND 9 43 PFI 2/P1.2
+5 V 8 42 PFI 3/P1.3
D GND 7 41 PFI 4/P1.4
PFI 5/P1.5 6 40 PFI 13/P2.5
PFI 6/P1.6 5 39 PFI 15/P2.7
D GND 4 38 PFI 7/P1.7
PFI 9/P2.1 3 37 PFI 8/P2.0
PFI 12/P2.4 2 36 D GND
PFI 14/P2.6 1 35 D GND
CONNECTOR 0
(AI 0–15)
TERMINAL 68 TERMINAL 35
TERMINAL 34 TERMINAL 1
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SH68-68-EP shielded cable.
BNC Accessories
You can use the SH68-68-EP shielded cable, to connect your DAQ device
to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
Cables
In most applications, you can use the following cables:
• SH68-68-EP—High-performance cable with individual bundles
separating analog and digital signals. Each differential analog input
channel is routed on an individually shielded twisted pair of wires.
Analog outputs are also individually shielded
• R68-68—Highly-flexible unshielded ribbon cable
NI 6254
PCI/PXI-6254 Pinout
Figure A-40 shows the pinout of the PCI/PXI-6254. The I/O signals appear
on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL35 D GND 12 46 P0.27
AI GND 56 22 NC D GND 13 47 P0.11
NC 55 21 NC TERMINAL 34 TERMINAL 1 +5 V 14 48 P0.15
NC 54 20 APFI 0 D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND APFI 1 20 54 NC
P0.7 48 14 +5 V NC 21 55 NC
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND NC 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6254 Specifications
Refer to the NI 625x Specifications for more detailed information about the
PCI/PXI-6254 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6255
The following sections contain information about the PCI/PXI-6255,
USB-6255 Screw Terminal, and USB-6255 Mass Termination devices.
PCI/PXI-6255
PCI/PXI-6255 Pinout
Figure A-41 shows the pinout of the PCI/PXI-6255.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 AI 71 1 35 AI 79
AI GND 67 33 AI 1 AI 78 2 36 AI 70
AI 9 66 32 AI GND AI 69 3 37 AI 77
AI 2 65 31 AI 10 AI 68 4 38 AI 76
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 AI 75 5 39 AI 67
(AI 16-79)
(AI 0-15)
AI 11 63 29 AI GND AI 66 6 40 AI 74
AI SENSE 62 28 AI 4 AI 65 7 41 AI 73
AI 12 61 27 AI GND AI 72 8 42 AI 64
AI 5 60 26 AI 13 AI GND 9 43 AI GND
AI GND 59 25 AI 6 AI 55 10 44 AI 63
AI 14 58 24 AI GND AI 54 11 45 AI 62
AI 7 57 23 AI 15 AI 61 12 46 AI 53
TERMINAL 68 TERMINAL 35
AI GND 56 22 AO 0 AI 52 13 47 AI 60
AO GND 55 21 AO 1 TERMINAL 34 TERMINAL 1 AI 51 14 48 AI 59
AO GND 54 20 APFI 0 AI 58 15 49 AI 50
D GND 53 19 P0.4 AI 49 16 50 AI 57
P0.0 52 18 D GND AI 48 17 51 AI 56
P0.5 51 17 P0.1 AI 47 18 52 AI 39
D GND 50 16 P0.6 AI 38 19 53 AI 46
P0.2 49 15 D GND AI 37 20 54 AI 45
P0.7 48 14 +5 V AI 44 21 55 AI 36
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND AI GND 22 56 AI SENSE 2
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 35 23 57 AI 43
PFI 10/P2.2 45 11 PFI 0/P1.0 AI 34 24 58 AI 42
D GND 44 10 PFI 1/P1.1 AI 41 25 59 AI 33
PFI 2/P1.2 43 9 D GND AI 32 26 60 AI 40
PFI 3/P1.3 42 8 +5 V AI 23 27 61 AI 31
PFI 4/P1.4 41 7 D GND AI 30 28 62 AI 22
PFI 13/P2.5 40 6 PFI 5/P1.5 AI 21 29 63 AI 29
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 20 30 64 AI 28
PFI 7/P1.7 38 4 D GND AI 27 31 65 AI 19
PFI 8/P2.0 37 3 PFI 9/P2.1 AI 18 32 66 AI 26
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI 25
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6255 Specifications
Refer to the NI 625x Specifications for more detailed information about the
PCI/PXI-6255 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
Using a BNC Accessory with Connector 0
Connector 0 of your device is compatible with several BNC accessories:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.3
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
The PCI/PXI-6255 has two connectors that require different cables.
1 NI recommends that you use the SHC68-68 cable when the SCB-68 is connected to Connector 1.
2 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
3 The SCC-68 only can be used with Connector 0.
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note For a ground connection, you can connect the shield of a shielded cable to the
chassis ground lug, depicted in Figure A-42.
17 AI 8 49 AI 27
AI 0 1 AI 19 33
18 AI 9 50 AI 28
AI 1 2 AI 20 34
19 AI 10 51 AI 29
AI 2 3 AI 21 35
20 AI 11 52 AI 30
AI 3 4 AI 22 36
21 AI 12 53 AI GND
AI 4 5 AI GND 37
22 AI GND 54 AI 31
AI GND 6 AI 23 38
23 AI 13 55 AI 40
AI 5 7 AI 32 39
24 AI 14 56 AI 41
AI 6 8 AI 33 40
25 AI 15 57 AI 42
AI 7 9 AI 34 41
26 AI 24 58 AI 43
AI 16 10 AI 35 42
27 AI 25 59 AI 44
AI 17 11 AI 36 43
28 AI 26 60 AI SENSE 2
AI 18 12 AI GND 44
29 AI GND 61 AI 45
AI GND 13 AI 37 45
30 APFI 0 62 AI 46
AI SENSE 14 AI 38 46
31 AO GND 63 AI 47
AO GND 15 AI 39 47
32 AO 1 64 AI 56
AO 0 16 AI 48 48
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 24 34 68 AI 16 AI 8 34 68 AI 0
AI 17 33 67 AI 25 AI 1 33 67 AI GND
AI 18 32 66 AI 26 AI GND 32 66 AI 9
AI 27 31 65 AI 19 AI 10 31 65 AI 2
AI 20 30 64 AI 28 AI 3 30 64 AI GND
AI 21 29 63 AI 29 AI GND 29 63 AI 11
AI 30 28 62 AI 22 AI 4 28 62 AI SENSE
AI 23 27 61 AI 31 AI GND 27 61 AI 12
AI 32 26 60 AI 40 AI 13 26 60 AI 5
AI 41 25 59 AI 33 AI 6 25 59 AI GND
AI 34 24 58 AI 42 AI GND 24 58 AI 14
AI 35 23 57 AI 43 AI 15 23 57 AI 7
AI GND 22 56 AI SENSE 2 AO 0 22 56 AI GND
AI 44 21 55 AI 36 AO 1 21 55 AO GND
AI 37 20 54 AI 45 APFI 0 20 54 AO GND
AI 38 19 53 AI 46 P0.4 19 53 D GND
AI 47 18 52 AI 39 D GND 18 52 P0.0
AI 48 17 51 AI 56 P0.1 17 51 P0.5
AI 49 16 50 AI 57 P0.6 16 50 D GND
AI 58 15 49 AI 50 D GND 15 49 P0.2
AI 51 14 48 AI 59 +5 V 14 48 P0.7
AI 52 13 47 AI 60 D GND 13 47 P0.3
AI 61 12 46 AI 53 D GND 12 46 PFI 11/P2.3
AI 54 11 45 AI 62 PFI 0/P1.0 11 45 PFI 10/P2.2
AI 55 10 44 AI 63 PFI 1/P1.1 10 44 D GND
AI GND 9 43 AI GND D GND 9 43 PFI 2/P1.2
AI 72 8 42 AI 64 +5 V 8 42 PFI 3/P1.3
AI 65 7 41 AI 73 D GND 7 41 PFI 4/P1.4
AI 66 6 40 AI 74 PFI 5/P1.5 6 40 PFI 13/P2.5
AI 75 5 39 AI 67 PFI 6/P1.6 5 39 PFI 15/P2.7
AI 68 4 38 AI 76 D GND 4 38 PFI 7/P1.7
AI 69 3 37 AI 77 PFI 9/P2.1 3 37 PFI 8/P2.0
AI 78 2 36 AI 70 PFI 12/P2.4 2 36 D GND
AI 71 1 35 AI 79 PFI 14/P2.6 1 35 D GND
CONNECTOR 1 CONNECTOR 0
(AI 16–79) (AI 0–15)
TERMINAL 68 TERMINAL 35 TERMINAL 68 TERMINAL 35
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SH68-68-EP shielded cable.
BNC Accessories
Using a BNC Accessory with Connector 0
Connector 0 of your device is compatible with several BNC accessories:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one screw terminal accessory with the signals on either
connector of your USB-6255 Mass Termination device. You can use two
screw terminal accessories with one M Series device by using both
connectors.2
Cables
Choosing a Cable for Connector 0
In most applications, you can use the following cables with Connector 0:
• SH68-68-EP—High-performance cable with individual bundles
separating analog and digital signals. Each differential analog input
channel is routed on an individually shielded twisted pair of wires.
Analog outputs are also individually shielded
• R68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SH68-68-S cable when the SCB-68 is connected to Connector 1.
2 The SCC-68 only can be used with Connector 0.
NI 6259
The following sections contain information about the
NI PCI/PCIe/PXI/PXIe-6259, USB-6259 Screw Terminal, USB-6259
BNC, and USB-6259 Mass Termination devices.
NI PCI/PCIe/PXI/PXIe-6259
NI PCI/PCIe/PXI/PXIe-6259 Pinout
Figure A-44 shows the pinout of the NI PCI/PCIe/PXI/PXIe-6259. The I/O
signals appear on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 35 D GND 12 46 P0.27
AI GND 56 22 AO 0 D GND 13 47 P0.11
AO GND 55 21 AO 1 TERMINAL 34 TERMINAL 1 +5 V 14 48 P0.15
AO GND 54 20 APFI 0 D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND APFI 1 20 54 AO GND
P0.7 48 14 +5 V AO 3 21 55 AO GND
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND AO 2 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
NI PCI/PCIe/PXI/PXIe-6259 Specifications
Refer to the NI 625x Specifications for more detailed information about the
NI PCI/PCIe/PXI/PXIe-6259 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
Note PCI Express users should consider the power limits on certain SCC modules without
an external power supply. Refer to the NI 625x Specifications, and the Disk Drive Power
Connector section of Chapter 3, Connector and LED Information, for information about
power limits and increasing the current the device can supply on the +5 V terminal.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI/PCI Express devices, such as M Series, E Series, CAN, and other
measurement, vision, and motion devices. Since PXI devices use PXI
backplane signals for timing and synchronization, no cables are required.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
17 AI 4 49 AI 20
AI 0 1 AI 16 33
18 AI 12 50 AI 28
AI 8 2 AI 24 34
19 AI GND 51 AI GND
AI GND 3 AI GND 35
20 AI 5 52 AI 21
AI 1 4 AI 17 36
21 AI 13 53 AI 29
AI 9 5 AI 25 37
22 AI GND 54 AI GND
AI GND 6 AI GND 38
23 AI 6 55 AI 22
AI 2 7 AI 18 39
24 AI 14 56 AI 30
AI 10 8 AI 26 40
25 AI GND 57 AI GND
AI GND 9 AI GND 41
26 AI 7 58 AI 23
AI 3 10 AI 19 42
27 AI 15 59 AI 31
AI 11 11 AI 27 43
28 AI GND 60 AI GND
AI GND 12 AI GND 44
29 APFI 0 61 APFI 1
AI SENSE 13 AI SENSE 2 45
30 AI GND 62 AI GND
AI GND 14 AI GND 46
31 AO 1 63 AO 3
AO 0 15 AO 2 47
32 AO GND 64 AO GND
AO GND 16 AO GND 48
CTR 0 A 81 (PFI 8)
CTR 0 Z 83 (PFI 9)
CTR 1 A 76 (PFI 3)
CTR 1 Z 77 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
USB-6259 BNC
USB-6259 BNC Pinout
Figure A-46 shows the pinout of the USB-6259 BNC.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
CTR 0 A PFI 8
CTR 0 Z PFI 9
CTR 0 B PFI 10
CTR 1 A PFI 3
CTR 1 Z PFI 4
CTR 1 B PFI 11
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
Differential Signals
To connect differential signals, determine the type of signal source you are
using—a floating signal (FS) source or a ground-referenced signal (GS)
source. Refer to the Connecting Analog Input Signals section of Chapter 4,
Analog Input, for more information.
AI 0
FS GS
Figure A-48 shows the analog input circuitry on the USB-6259 BNC.
When the switch is in the FS position, AI x – is grounded through a 0.1 µF
capacitor in parallel with a 5 kΩ resistor.
AI x + AI x +
+ +
– –
AI x – AI x –
GS GS
FS FS
0.1 µF 5 kΩ 0.1 µF 5 kΩ
AI GND AI GND
USB-62xx Device USB-62xx Device
Floating Source Grounded Source
Single-Ended Signals
For each BNC connector that you use for two single-ended channels, set the
source type switch to the GS position. This setting disconnects the built-in
ground reference resistor from the negative terminal of the BNC connector,
allowing the connector to be used as a single-ended channel, as shown in
Figure A-49.
AI x
+
– AI x+8
Ground Ref.
Source (GS)
USB-62xx BNC Device
When you set the source type to the GS position and software-configure the
device for single-ended input, each BNC connector provides access to two
single-ended channels, AI x and AI x+8. For example, the BNC connector
labeled AI 0 provides access to single-ended channels AI 0 and AI 8, the
BNC connector labeled AI 1 provides access to single-ended channels AI 1
and AI 9, and so on. Up to 32 single-ended channels are available in
single-ended measurement modes.
Analog Output
You can access analog output signals on the BNC connectors labeled AO 0
and AO 1. Figure A-50 shows the analog output circuitry on the USB-6259
BNC.
AO x
AO GND
PFI x/P1.x
D GND
APFI
You can access the analog programmable function interface signals on the
BNC connectors labeled APFI <0..1>. Figure A-52 shows the APFI
circuitry on the USB-6259 BNC.
APFI x
AI GND
D GND D GND
USER 1
USER 2 Internal Connection
D GND
+5 V
D GND
P0.0
P0.1 Screw
P0.2 Terminal
P0.3 Block
D GND
P0.4
P0.5
P0.6
P0.7
D GND
PFI 8/P2.0
Figure A-54 shows an example of how to use the USER 1 and USER 2
BNCs. To access the PFI 8 signal from a BNC, connect USER 1 on the
screw terminal block to PFI 8 with a wire.
USER 1 BNC
USER 1
USER 2
D GND
+5 V
D GND
P0.0
P0.1
P0.2
PFI 8 Wire
P0.3
Signal D GND
P0.4
P0.5
P0.6
P0.7 Screw
D GND Terminal
PFI 8/P2.0 Block
The designated space below each USER <1..2> BNC is for marking or
labeling signal names.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 8 34 68 AI 0 AI 24 34 68 AI 16
AI 1 33 67 AI GND AI 17 33 67 AI GND
AI GND 32 66 AI 9 AI GND 32 66 AI 25
AI 10 31 65 AI 2 AI 26 31 65 AI 18
AI 3 30 64 AI GND AI 19 30 64 AI GND
AI GND 29 63 AI 11 AI GND 29 63 AI 27
AI 4 28 62 AI SENSE AI 20 28 62 AI SENSE 2
AI GND 27 61 AI 12 AI GND 27 61 AI 28
AI 13 26 60 AI 5 AI 29 26 60 AI 21
AI 6 25 59 AI GND AI 22 25 59 AI GND
AI GND 24 58 AI 14 AI GND 24 58 AI 30
AI 15 23 57 AI 7 AI 31 23 57 AI 23
AO 0 22 56 AI GND AO 2 22 56 AI GND
AO 1 21 55 AO GND AO 3 21 55 AO GND
APFI 0 20 54 AO GND APFI 1 20 54 AO GND
P0.4 19 53 D GND P0.12 19 53 D GND
D GND 18 52 P0.0 D GND 18 52 P0.8
P0.1 17 51 P0.5 P0.9 17 51 P0.13
P0.6 16 50 D GND P0.14 16 50 D GND
D GND 15 49 P0.2 D GND 15 49 P0.10
+5 V 14 48 P0.7 +5 V 14 48 P0.15
D GND 13 47 P0.3 D GND 13 47 P0.11
D GND 12 46 PFI 11/P2.3 D GND 12 46 P0.27
PFI 0/P1.0 11 45 PFI 10/P2.2 P0.16 11 45 P0.26
PFI 1/P1.1 10 44 D GND P0.17 10 44 D GND
D GND 9 43 PFI 2/P1.2 D GND 9 43 P0.18
+5 V 8 42 PFI 3/P1.3 +5 V 8 42 P0.19
D GND 7 41 PFI 4/P1.4 D GND 7 41 P0.20
PFI 5/P1.5 6 40 PFI 13/P2.5 P0.21 6 40 P0.29
PFI 6/P1.6 5 39 PFI 15/P2.7 P0.22 5 39 P0.31
D GND 4 38 PFI 7/P1.7 D GND 4 38 P0.23
PFI 9/P2.1 3 37 PFI 8/P2.0 P0.25 3 37 P0.24
PFI 12/P2.4 2 36 D GND P0.28 2 36 D GND
PFI 14/P2.6 1 35 D GND P0.30 1 35 D GND
CONNECTOR 0 CONNECTOR 1
(AI 0–15) (AI 16–31)
TERMINAL 68 TERMINAL 35 TERMINAL 68 TERMINAL 35
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SH68-68-EP shielded cable.
BNC Accessories
You can use the SH68-68-EP shielded cable, to connect your DAQ device
to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
Cables
In most applications, you can use the following cables:
• SH68-68-EP—High-performance cable with individual bundles
separating analog and digital signals. Each differential analog input
channel is routed on an individually shielded twisted pair of wires.
Analog outputs are also individually shielded
• R68-68—Highly-flexible unshielded ribbon cable
NI 6280
PCI/PXI-6280 Pinout
Figure A-56 shows the pinout of the PCI/PXI-6280.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 NC
NC 55 21 NC
NC 54 20 APFI 0
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6280 Specifications
Refer to the NI 628x Specifications for more detailed information about the
PCI/PXI-6280 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6281
PCI/PXI-6281 Pinout
Figure A-57 shows the pinout of the PCI/PXI-6281.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8
AI GND 67 33 AI 1
AI 9 66 32 AI GND
AI 2 65 31 AI 10
CONNECTOR 0
AI GND 64 30 AI 3
(AI 0-15)
AI 11 63 29 AI GND
AI SENSE 62 28 AI 4
AI 12 61 27 AI GND
AI 5 60 26 AI 13
AI GND 59 25 AI 6
AI 14 58 24 AI GND
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 34
AI GND 56 22 AO 0
AO GND 55 21 AO 1
AO GND 54 20 APFI 0
D GND 53 19 P0.4
P0.0 52 18 D GND
P0.5 51 17 P0.1
D GND 50 16 P0.6
P0.2 49 15 D GND
P0.7 48 14 +5 V
P0.3 47 13 D GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 1
PFI 10/P2.2 45 11 PFI 0/P1.0
D GND 44 10 PFI 1/P1.1
PFI 2/P1.2 43 9 D GND
PFI 3/P1.3 42 8 +5 V
PFI 4/P1.4 41 7 D GND
PFI 13/P2.5 40 6 PFI 5/P1.5
PFI 15/P2.7 39 5 PFI 6/P1.6
PFI 7/P1.7 38 4 D GND
PFI 8/P2.0 37 3 PFI 9/P2.1
D GND 36 2 PFI 12/P2.4
D GND 35 1 PFI 14/P2.6
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6281 Specifications
Refer to the NI 628x Specifications for more detailed information about the
PCI/PXI-6281 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
• BNC-2120—Similar to the BNC-2110, and also has a built-in function
generator, quadrature encoder, temperature reference, and
thermocouple connector
• BNC-2090A—Desktop/rack-mountable device with 22 BNCs for
connecting analog, digital, and timing signals
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6284
PCI/PXI-6284 Pinout
Figure A-58 shows the pinout of the PCI/PXI-6284. The I/O signals appear
on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL35 D GND 12 46 P0.27
AI GND 56 22 NC D GND 13 47 P0.11
NC 55 21 NC TERMINAL 34 TERMINAL 1 +5 V 14 48 P0.15
NC 54 20 APFI 0 D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND APFI 1 20 54 NC
P0.7 48 14 +5 V NC 21 55 NC
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND NC 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
NC = No Connect NC = No Connect
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6284 Specifications
Refer to the NI 628x Specifications for more detailed information about the
PCI/PXI-6284 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
NI 6289
PCI/PXI-6289 Pinout
Figure A-59 shows the pinout of the PCI/PXI-6289. The I/O signals appear
on two 68-pin connectors.
For a detailed description of each signal, refer to the I/O Connector Signal
Descriptions section of Chapter 3, Connector and LED Information.
Note M Series devices may be used with most E Series accessories. However, some
E Series accessories use different terminal names. Refer to the M Series and E Series
Pinout Comparison section of Chapter 3, Connector and LED Information, for more
information.
AI 0 68 34 AI 8 P0.30 1 35 D GND
AI GND 67 33 AI 1 P0.28 2 36 D GND
AI 9 66 32 AI GND P0.25 3 37 P0.24
AI 2 65 31 AI 10 D GND 4 38 P0.23
CONNECTOR 0
CONNECTOR 1
AI GND 64 30 AI 3 P0.22 5 39 P0.31
(AI 16-31)
(AI 0-15)
AI 11 63 29 AI GND P0.21 6 40 P0.29
AI SENSE 62 28 AI 4 D GND 7 41 P0.20
AI 12 61 27 AI GND +5 V 8 42 P0.19
AI 5 60 26 AI 13 D GND 9 43 P0.18
AI GND 59 25 AI 6 P0.17 10 44 D GND
AI 14 58 24 AI GND P0.16 11 45 P0.26
AI 7 57 23 AI 15 TERMINAL 68 TERMINAL 35 D GND 12 46 P0.27
AI GND 56 22 AO 0 D GND 13 47 P0.11
AO GND 55 21 AO 1 TERMINAL 34 TERMINAL 1 +5 V 14 48 P0.15
AO GND 54 20 APFI 0 D GND 15 49 P0.10
D GND 53 19 P0.4 P0.14 16 50 D GND
P0.0 52 18 D GND P0.9 17 51 P0.13
P0.5 51 17 P0.1 D GND 18 52 P0.8
D GND 50 16 P0.6 P0.12 19 53 D GND
P0.2 49 15 D GND APFI 1 20 54 AO GND
P0.7 48 14 +5 V AO 3 21 55 AO GND
TERMINAL 1 TERMINAL 34
P0.3 47 13 D GND AO 2 22 56 AI GND
PFI 11/P2.3 46 12 D GND TERMINAL 35 TERMINAL 68 AI 31 23 57 AI 23
PFI 10/P2.2 45 11 PFI 0/P1.0 AI GND 24 58 AI 30
D GND 44 10 PFI 1/P1.1 AI 22 25 59 AI GND
PFI 2/P1.2 43 9 D GND AI 29 26 60 AI 21
PFI 3/P1.3 42 8 +5 V AI GND 27 61 AI 28
PFI 4/P1.4 41 7 D GND AI 20 28 62 AI SENSE 2
PFI 13/P2.5 40 6 PFI 5/P1.5 AI GND 29 63 AI 27
PFI 15/P2.7 39 5 PFI 6/P1.6 AI 19 30 64 AI GND
PFI 7/P1.7 38 4 D GND AI 26 31 65 AI 18
PFI 8/P2.0 37 3 PFI 9/P2.1 AI GND 32 66 AI 25
D GND 36 2 PFI 12/P2.4 AI 17 33 67 AI GND
D GND 35 1 PFI 14/P2.6 AI 24 34 68 AI 16
CTR 0 A 37 (PFI 8)
CTR 0 Z 3 (PFI 9)
CTR 1 A 42 (PFI 3)
CTR 1 Z 41 (PFI 4)
Note For more information about default NI-DAQmx counter inputs, refer to Connecting
Counter Signals in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.
PCI/PXI-6289 Specifications
Refer to the NI 628x Specifications for more detailed information about the
PCI/PXI-6289 device.
SCXI Accessories
SCXI is a programmable signal conditioning system designed for
measurement and automation applications. To connect your M Series
device to an SCXI chassis, use the SCXI-1349 adapter and an
SHC68-68-EPM cable.
Note When using Connector 1 in parallel mode with SCXI modules that support track and
hold, you must programmatically disable track and hold.
You also can use an M Series device to control the SCXI section of a
PXI/SCXI combination chassis, such as the PXI-1010 or PXI-1011. The
M Series device in the rightmost PXI slot controls the SCXI devices.
No cables or adapters are necessary.
SCC Accessories
SCC provides portable, modular signal conditioning to your DAQ system.
To connect your M Series device to an SCC module carrier, such as the
SC-2345, SC-2350, or SCC-68, use an SHC68-68-EPM shielded cable.
BNC Accessories
You can use the SHC68-68-EPM shielded cable, to connect your DAQ
device to BNC accessories, such as the following:
• BNC-2110—Provides BNC connectivity to all analog signals, some
digital signals, and spring terminals for other digital signals
• BNC-2111—Provides BNC connectivity to 16 single-ended analog
input signals, two analog output signals, five DIO/PFI signals, and the
external reference voltage for analog output
You can use one BNC accessory with the signals on either connector of
your M Series device. You can use two BNC accessories with one M Series
device by using both connectors.
You can use one screw terminal accessory with the signals on either
connector of your M Series device. You can use two screw terminal
accessories with one M Series device by using both connectors.
RTSI Cables
Use RTSI bus cables to connect timing and synchronization signals among
PCI devices, such as M Series, E Series, CAN, and other measurement,
vision, and motion devices. Since PXI devices use PXI backplane signals
for timing and synchronization, no cables are required.
1 TB-2706 uses Connector 0 of your PXI device. After a TB-2706 is installed, Connector 1 cannot be used.
Cables
In most applications, you can use the following cables:
• SHC68-68-EPM1—High-performance cable designed specifically for
M Series devices. It has individual bundles separating analog and
digital signals. Each differential analog input channel is routed on an
individually shielded twisted pair of wires. Analog outputs are also
individually shielded
• SHC68-68—Lower-cost shielded cable with 34 twisted pairs of wire
• RC68-68—Highly-flexible unshielded ribbon cable
1 NI recommends that you use the SHC68-68-EPM cable; however, an SHC68-68-EP cable will work with M Series devices.
_i POUT
Selected Reference Trigger Reference Trigger
Terminal Terminal
_i POUT
Start
Terminal Terminal
Selected Start
POUT
RTSI
The following signals are used in Figure B-1 and in the following sections:
• Terminal—Refers to any device terminal, such as PFI or RTSI. These
terminals are used as inputs and as outputs for signals.
• _i—Refers to any internal signal available to the analog input timing
engine for use. In the case of signals coming from an external terminal,
this would be the signal after is been through the first input buffer.
_i also can refer to other internal signals such as internal timebases or
signals coming from other blocks.
• POUT—Refers to any output signal right before is driven to an output
terminal.
• Convert Clock Timebase and Sync Convert Clock
Timebase—Convert Clock Timebase is the source signal used to
generate the signal that will actually cause the ADC to do a conversion
(p_AI_Convert). This signal can be an internal or external timebase
Input Timing
Input timing refers to the delays involved in importing external signals to
be used as triggers or clocks in the AI timing engine. Figures B-2 and B-3
and Table B-1 describe the insertion delays for external signals.
_i
Start
Terminal Terminal
Selected Start
RTSI
_i
Selected Pause Trigger
Terminal
Figure B-2. Input Timing and the Analog Input Timing Engine
Terminal
t1
t1
_i
given condition (maximum or minimum timing). This difference can be useful when two external signals will be used
together and the relative timing between the signals is important.
Internal Timing
AI Timing Clocks
The analog input timing engine has two levels of timing that control an AI
acquisition. The first level is the convert level. This is the timing that
controls when the analog to digital conversions take place. The SC, DIV,
and SI2 counters run on this timing level. The signal that clocks this timing
level is called Convert Clock Timebase. This signal can come from an
internal source (for example, an internal timebase) or an external signal.
It can be divided down using the SI2 counter, or it can be used directly
(in external convert mode). In order to synchronize triggers to the Convert
Clock Timebase signal, another related signal is generated called Sync
Convert Clock Timebase. Sync Convert Clock Timebase is generated
differently depending on the mode the AI timing engine is operating on:
• When Convert Clock Timebase is a signal that will be divided down
using the SI2 counter (either internal or external), it is considered to be
a free-running clock. In this case, the Sync Convert Clock Timebase is
the inverted version of the Convert Clock Timebase signal. The idea is
to use the falling edge of the original signal to synchronize external
signals before the rising edge of the Convert Clock Timebase occurs
(after polarity selection). This case is the one described in this section.
• When Convert Clock Timebase is not going to be divided by the
SI2 counter (in the case of an external convert signal), this signal is
assumed to be not free-running and highly irregular. In this case, Sync
Convert Clock Timebase is selected to be the actual external signal,
and Convert Clock Timebase is a delayed version of the external
signal. This delay is long enough so that external signals can be
synchronized with Sync Convert Clock Timebase and used by Convert
Clock Timebase. For timing diagrams and parameters for this case,
refer to the Convert Clock section.
The second level of timing is the sample level. Basically, converts are
grouped in sets called samples, and the timing of the samples can be
independent from the timing of the converts. The M Series device can use
a timebase to generate the sample timing. This timebase is called Sample
Clock Timebase. This signal can be internal (for example, an internal
timebase) or external. Either way, the signal gets divided in the SI counter
and used to generate Sample Clock signals (which in turn, signal the start
of a sample). In order to synchronize external triggers to the Sample Clock
Timebase, another related signal is created, Sync Sample Clock Timebase.
This is always the inverted signal selected to be Sample Clock Timebase,
while the Sample Clock Timebase signal is a copy without inversion of the
signal. The idea is that for each significant edge of the Sample Clock
Timebase, there is a significant edge of the Sync Sample Clock Timebase
signal that occurs before Sample Clock Timebase and that can be used to
synchronize the input triggers.
The source for Convert Clock Timebase and Sample Clock Timebase is the
internal signal bus, _i. The timing of this signal is described in relation to
this common point. The Convert Clock Timebase and Sample Clock
Timebase can be asynchronous from each other.
Start
Terminal Terminal
Selected Start
RTSI
Pause Trigger
Terminal
Figure B-4. AI Timing Clocks and the Analog Input Timing Engine
t2 t2 t3
_i
t4
Sample
Clock Timebase
t5
Sync Sample
Clock Timebase
t6
Convert
Clock Timebase
t7
Sync Convert
Clock Timebase
Convert Clock
Convert Clock is the signal that determines when an analog to digital
conversion is started. The signal going to the ADC is called p_AI_Convert.
Convert Clock also can be routed to several external I/O terminals for
external use. Convert Clock is always generated from the Convert Clock
Timebase signal, either directly or indirectly (by dividing it down using the
SI2 counter). If the SI2 counter is used, it is assumed that a reliable
free-running clock is being used. Refer to the AI Timing Clocks section for
the timing relationship between Convert Clock Timebase and Sync Convert
Clock Timebase. If the SI2 counter is not being used (external convert
case), the Convert Clock Timebase is assumed to be not free-running and
the relationship between the Convert Clock Timebase and the Sync Convert
Clock Timebase is an asynchronous delay.
Whether the SI2 counter is used or not, the timing parameters in the
generation of Convert Clock are the same starting at the Convert Clock
Timebase signal.
Start
Terminal Terminal
Selected Start
RTSI
Selected Pause Trigger
Terminal
Figure B-6. Convert Clock and the Analog Input Timing Engine
t8
_i
t9
Convert Clock Timebase
t10
p_AI_Convert
t11
POUT
_i
p_AI_Convert
t12
Figure B-8. Convert Clock and Any Internal Signal Timing Diagram
Start
Start is the signal that starts an AI acquisition. This signal can come from
an external source (through an external terminal) or from an internal
source. One possible internal source is a software-generated pulse. A
multiplexer selects from all the possible sources (all of them at _i level) and
outputs a signal called Selected Start. Selected Start then gets sent to the
two timing levels in the AI section (the Convert Clock Timebase and the
Sample Clock Timebase timing level) for synchronization to each clock.
Once the Convert Clock Timebase timing domain has received a valid Start,
the AI timing engine is ready to start generating converts, as soon as it
receives a Sample Clock (beginning of a sample). Once the Sample Clock
Timebase domain has received a valid Start, the AI timing engine is ready
to start generating Sample Clocks.
RTSI
Selected Pause Trigger
Terminal
Figure B-9. Convert Clock Timebase Timing and the Analog Input Timing Engine
_i
t13
Selected Start
t15
t14
Sync Convert Clock Timebase
t16
Start
t17
POUT
_i
Start
Terminal Terminal
Selected Start
RTSI
Figure B-11. Sample Clock Timebase Timing and the Analog Input Timing Engine
_i
t18
Selected Start
t20
t19
Sync Sample Clock Timebase
t21
SI Start
Reference Trigger
Use the Reference Trigger to stop the acquisition. It is normally used in
pretrigger acquisitions; it is necessary to acquire data before and after the
trigger. The Reference Trigger signals the time when the AI timing engine
starts counting the number of posttrigger conversions to take before
stopping. The Reference Trigger can come from external or internal
sources and its source is selected with a multiplexer. Its output is called the
Selected Reference Trigger.
Start
Terminal Terminal
Selected Start
RTSI
Selected Pause Trigger
Terminal
Figure B-13. Reference Trigger and the Analog Input Timing Engine
_i
t22
Selected Reference Trigger
t24
t23
Sync Convert Clock Timebase
t25
Reference Trigger
t26 t26
POUT
Sample Clock
Sample Clock signals the start of a sample (which, in turn, is a set of
converts). Sample Clock is generated from external or internal sources. The
main internal source is the terminal count (TC) of the SI counter that runs
on the Sample Clock Timebase signal. All the sources for Sample Clock are
at the _i level and are selected using a multiplexer. The output of this
multiplexer is called Selected Sample Clock.
Start
Terminal Terminal
Selected Start
RTSI
Selected Pause Trigger
Terminal
Figure B-15. Sample Clock and the Analog Input Timing Engine
_i
t27
Selected Sample Clock
t28 t29
Sample Clock
t31
POUT
The AI timing engine also can export a signal related to the Sample Clock
called AI_Sample_In_Progress. This signal asserts with the Sample Clock
and stays asserted until after the last convert of the sample. It is useful for
external simultaneous sample and hold signal conditioning.
Sample Clock
Convert Clock
POUT
t32 t33
Pause Trigger
The Pause Trigger signal can be used to pause the acquisition any time the
signal deasserts. It is generated from internal or external sources. A
multiplexer selects a signal from the _i bus; its output is called Selected
Pause Trigger.
Start
Terminal Terminal
Selected Start
RTSI
Selected Pause Trigger
Terminal
Figure B-18. Pause Trigger and the Analog Input Timing Engine
_i
t34
Selected Pause Trigger
t36
t35 t35
Output Timing
Output timing refers to the delays involved in exporting internal signals to
external terminals, so they can be used to trigger or time external devices.
These timing parameters include the selection multiplexer in each terminal
plus the delay of the output driver. Figures B-20 and B-21 and Table B-11
describe output timing.
The delays presented in this section assume a 200 pF load on PFI lines and
a 50 pF load on RTSI lines. Actual delays will vary with the actual load.
POUT
Selected Reference Trigger Reference Trigger
Terminal Terminal
POUT
Start
Terminal Terminal
Selected Start
POUT
RTSI
Figure B-20. Output Timing and the Analog Input Timing Engine
POUT
t39
t40
Terminal
Other
Internal Internal
Sources Sources
Sample
Clock
Timebase AO TIMER Sample Clock
STAR_TRIG,
RTSI, or
PFI Selected
STAR_TRIG_i, START
PFI
RTSI_i, or
PFI_i
START Trigger
Selected Pause
Pause Trigger
RTSI
The following signals are used in Figure B-22 and in the following
sections:
• Sample Clock—This signal multiplied by the digital to analog
conversions. This signal is routed to the DAC, and in every pulse, the
DAC will perform a data conversion. This signal can come directly
from an external signal or can be the result of dividing down the
Sample Clock Timebase using the UI counter.
Input Timing
Input timing refers to the delays of importing signals from the external
terminals so that the analog output timing engine can use them as sources
for different triggers or clocks. Figure B-23 and Table B-12 describe the
insertion delays for external signals.
Terminal
t1
t1
_i
given condition (maximum or minimum timing). This difference can be useful when two external signals will be used
together and the relative timing between the signals is important.
Signal_i
t3
If the Sample Clock is being generated by dividing down the Sample Clock
Timebase, the analog output generation is timed from the output of the
UI counter. The signal Sample Clock Timebase can be an external signal.
When the analog output timing engine operates in this mode, it is assumed
that the source signal for the Sample Clock timebase is a free-running
clock, so the Sync Sample Clock Timebase is the inverted version of
Sample Clock Timebase. Configuring the analog output timing engine for
rising edge operation will cause the external signals to be synchronized on
the falling edge of the Sample Clock Timebase, which corresponds to the
rising edge of Sync Sample Clock Timebase.
Signal_i
t4
Sync Sample Clock Timebase
t5
Sample Clock Timebase
Figure B-25. Sample Clock Timebase and the Sync Sample Clock Timebase
Timing Diagram
Table B-14. Sample Clock Timebase and the Sync Sample Clock Timebase Timing
Start Trigger
As an output, the Start Trigger is routed as an asynchronous pulse. The
actual signal that gets routed is the Selected Start signal, so there is no
synchronous delay involved.
Selected Start
Signal_i Logic D Q To Internal Logic
Signal_i t6
t7
Selected Start t8
t7 Setup 1.5 —
t8 Hold 0 —
Pause Trigger
The analog output Pause Trigger can be used to pause an ongoing
generation. It is received on the rising edge of Sync Sample Clock
Timebase.
Selected Pause
Signal_i Logic D Q To Internal Logic
t9
t9
Signal_i
t10
Sync Sample Clock Timebase
t11 Hold 0 —
• Let DFFSetup and DFFHold be the setup and hold time of the DFF.
• Let ExternalSetup and ExternalHold be the setup and hold time of the
trigger to the clock at the terminals.
Figure B-30 shows the external trigger and external clock and the trigger
delay and clock delay.
DFF
External
TriggerDelay D Q
Trigger
External
ClockDelay
Clock
To satisfy the DFF setup and hold requirement, the following condition
must be true:
DFFSetup and DFFHold are given by Table B-16 for AO Start and Table B-18
for AO Pause triggers.
ClockDelay is the sum of the input timing (shown in Table B-12), and
insertion timing (shown in Table B-13).
TriggerDelay is the sum of the input timing (shown in Table B-12), and
internal timing (shown in Tables B-15 and B-17).
For setup calculations, use the maximum timing parameters. For hold
calculations, use the minimum timing parameters.
For input timing, as shown in Table B-12, two numbers are given for the
maximum delay and two numbers for the minimum delay. In order to
account for the worst case skew between different input terminals, use the
range given in the input delay tables in the Input Timing section in a way
that provides the most conservative results. For setup calculations, use the
bigger number for TriggerDelay and the smaller number ClockDelay. For
hold calculations, use the smaller number for TriggerDelay and the larger
number for ClockDelay.
Output Timing
The analog output timer has three possible trigger outputs—Start Trigger,
Pause Trigger, and Sample Clock. The delays presented in this section
assume a 200 pF load on PFI lines and a 50 pF load on RTSI lines. Actual
delays will vary with the actual load. The two numbers given for each
condition represent the variation from the best case and worst case
terminals.
Start Trigger
As an output, the Start Trigger is routed as an asynchronous pulse. The
actual signal that gets routed is the Selected Start signal, so there is no
synchronous delay involved.
Routing Logic
RTSI, PFI
t12
Selected Start
PFI/RTSI Terminal
Pause Trigger
Pause Trigger is only output asynchronously and only to RTSI. The actual
signal being routed is Selected Pause. The Pause Trigger output timing can
be derived by adding the delay in Table B-20 to the total Selected Pause
delay.
Routing Logic
RTSI
t13
Selected Pause
Sample Clock
The rising edge of the Sample Clock is output synchronous to the Sample
Clock Timebase. It can be calculated by adding the Sample Clock
Timebase insertion to the delay in Table B-21. The exported Sample Clock
signal is active low, each falling edge representing a conversion.
Routing Logic
RTSI, PFI
t14
Sample Clock Timebase
RTSI/PFI Terminal
P0_i
P0
DI Waveform
DI Sample
PFI, RTSI, Acquisition FIFO
Clock
or PXI_STAR PFI_i, RTSI_i,
or PXI_STAR_i
PFI (Output)
Other Internal
Signals
Figure B-38 and Tables B-22 and B-23 describe the digital waveform
acquisition timing delays and requirements. Your inputs must meet the
requirements to ensure proper behavior.
t1
t2 t2
PFI, RTSI,
or PXI_STAR
t3 t3
PFI_i, RTSI_i,
or PXI_STAR_i
t4 t4
DI Sample Clock
t5 t6
P0
t7 t7
P0_i
t8 t9
PFI (Output)
t9 † PFI (output) high PFI (output) low One period of Two periods of
80 MHz Timebase 80 MHz Timebase
* The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a
given condition (maximum or minimum timing). This difference can be useful when two external signals will be used
together and the relative timing between the signals is important.
† When DI Sample Clock is routed to a PFI output pin, the pulse width of the output is independent of the pulse width of the
input. The pulse width is specified in a number of periods of the 80 MHz Timebase
PFI_i, RTSI_i, P0
or PXI_STAR_i DO Waveform
DO Sample
PFI, RTSI, Generation FIFO
Clock
or PXI_STAR
PFI (Output)
Other Internal
Signals
Figure B-40 and Tables B-24 and B-25 describe the digital waveform
generation timing delays and requirements. Your inputs must meet the
requirements to ensure proper behavior.
t10
t11 t11
PFI, RTSI,
or PXI_STAR
t12 t12
PFI_i, RTSI_i,
or PXI_STAR_i
t13 t13
DO Sample Clock
t14
P0
t15 t16
PFI (Output)
t16† PFI (output) high PFI (output) low Two periods of Three periods of
80 MHz Timebase 80 MHz Timebase
* The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a
given condition (maximum or minimum timing). This difference can be useful when two external signals will be used
together and the relative timing between the signals is important.
† When DO Sample Clock is routed to a PFI output pin, the pulse width of the output is independent of the pulse width of
the input. The pulse width is specified in a number of periods of the 80 MHz Timebase.
Input Delays
This section describes some of the timing delays of the counter/timer
circuit. To describe delays of the counter/timer, we model the circuitry as
shown in Figure B-41. In the figure, PFI, RTSI, and PXI_STAR represent
signals at connectors pins of the M Series device. The other named signals
represent internal signals.
PFI, RTSI,
or PXI_STAR
PFI_i, RTSI_i,
or PXI_STAR_i
t1 t1
Selected Source is used to clock the 32-bit counter. Selected Gate drives the
Gate Logic, which generates the Counter Enable signal.
All internal counter timing is referenced to these two signals. Any internal
signal refers to signals with _i from the previous table or signals coming
from another subsystem inside the M Series device. It does not include
internal timebases or the PXI_CLK10.
PFI_i, RTSI_i,
or PXI_STAR_i
Selected_Gate
t2 t2
PFI_i, RTSI_i,
or PXI_STAR_i
Selected_Source
t3 t3
The delays depend on both the synchronization mode and gating mode for
the application.
Selected_Gate
t4 t4
Count_Enable
Synchronization
Time Mode Gating Mode Min (ns) Max (ns)
Other Internal Source Edge 1/2 Source Period – 1 ns 1/2 Source Period + 3 ns
Input Requirements
Refer to the Figure B-41 for the M Series counter/timer circuitry.
t5
t6
Counter n Source
t6
t7
Counter n Gate
t7
Figure B-48 and Table B-32 show the setup and hold requirements at the
PFI pins for the first case (where a PFI pin drives Counter n Source and a
different PFI pin drives Counter n Gate).
PFI (Gate)
t8S t8H
PFI (Source)
Synchronization
Time Description Gating Mode Mode Min (ns) Max (ns)
t8S Setup time from PFI (Gate) Edge External Source 12.3 —
to PFI (Source)
Level External Source 8.3 —
t8H Hold time from PFI (Gate) Edge External Source 0.5 —
to PFI (Source)
Level External Source 2.0 —
Figure B-49 and Table B-33 show the setup and hold requirements of the
internal block of the DAQ-STC2. Use the table to calculate the setup and
hold times for your Source and Gate signals for the general case. In the
general case, you can determine whether the setup and hold requirements
are met by adding up the various delays of the appropriate signals through
the counter/timer circuit.
Count_Enable
t9S t9H
Selected_Source
Figure B-49. DAQ-STC2 Internal Block Setup and Hold Requirements Timing Diagram
Table B-33. DAQ-STC2 Internal Block Setup and Hold Requirements Timing
t9H Hold 0 —
Note This example shows how we determine the setup and hold times for the PFI to PFI
example above (first case) using level gating.
Setup
To calculate the setup time, subtract the Source delay from the Gate delay.
Use maximum delays.
Gate Delay
PFI to PFI_i 22.0 ns
PFI_i to Selected Gate 6.0 ns
Selected Gate to Count Enable (Level) 18.0 ns
Count Enable Setup Time + 1.5 ns
47.5 ns
Source Delay
PFI to PFI_i 18.2 ns
PFI_i to Selected Source + 21.0 ns
39.2 ns
TSetup > 47.5 ns – 39.2 ns = 8.3 ns
Hold
To calculate the hold time, subtract the Gate delay from the Source delay.
Use minimum delays.
Gate Delay
PFI to PFI_i 5.2 ns
PFI_i to Selected Gate 1.0 ns
Selected Gate to Count Enable (Level) 6.0 ns
Count Enable Hold Time + 0.0 ns
12.2 ns
Source Delay
PFI to PFI_i 6.2 ns
PFI_i to Selected Source + 8.0 ns
14.2 ns
THold > 14.2 ns – 12.2 ns = 2.0 ns
Output Delays
Refer to the Figure B-41 for the M Series counter/timer circuitry.
Selected Source
t10
Out_o
t11
PFI, RTSI
(Counter n Internal Out)
t12
PFI, RTSI
(Counter n Source)
Selected Gate
t13
PFI, RTSI
(Counter n Gate)
Gating Modes
Gating mode refers to how the counter/timer uses the Gate input. Some
timing operations depend on the gating mode. Depending on the
application, the counter/timers either level gating mode or edge gating
mode.
In NI-DAQmx, the counter/timers use level gating mode for the following
measurements:
• Edge counting
• Pulse width measurements
• Two-signal edge separation measurements
t14
t15 t15 t20
Counter n A
t16
t17 t17
Counter n B
t19
Counter n Z
t18 t18
t1
80 MHz Timebase
20 MHz Timebase
t2
t3
Figure B-52. Generating Different Clocks from the Onboard 80 MHz Oscillator
Table B-36. Generating Different Clocks from the Onboard 80 MHz Oscillator
Table B-37 shows delays for generating different clocks using an External
Reference Clock and the PLL.
RTSI <0..7>
t5
STAR_TRIG
PXI_CLK10
(Reference Clock)
Table B-37. Generating Different Clocks Using an External Reference Clock and the PLL
Analog Input
I am seeing crosstalk or ghost voltages when sampling multiple
channels. What does this mean?
You may be experiencing a phenomenon called charge injection, which
occurs when you sample a series of high-output impedance sources with a
multiplexer. Multiplexers contain switches, usually made of switched
capacitors. When a channel, for example AI 0, is selected in a multiplexer,
those capacitors accumulate charge. When the next channel, for example
AI 1, is selected, the accumulated current (or charge) leaks backward
through channel 1. If the output impedance of the source connected to AI 1
is high enough, the resulting reading can somewhat affect the voltage in
AI 0. To circumvent this problem, use a voltage follower that has
operational amplifiers (op-amps) with unity gain for each high-impedance
source before connecting to an M Series device. Otherwise, you must
decrease the sample rate for each channel.
How can I use the AI Sample Clock and AI Convert Clock signals on
an M Series device to sample the AI channel(s)?
M Series devices use ai/SampleClock and ai/ConvertClock to perform
interval sampling. As Figure C-1 shows, ai/SampleClock controls the
sample period, which is determined by the following equation:
Channel 0
Channel 1
Convert Period
Sample Period
Analog Output
I am seeing glitches on the output signal. How can I minimize it?
When you use a DAC to generate a waveform, you may observe glitches on
the output signal. These glitches are normal; when a DAC switches from
one voltage to another, it produces glitches due to released charges. The
largest glitches occur when the most significant bit of the DAC code
changes. You can build a lowpass deglitching filter to remove some of these
glitches, depending on the frequency and nature of the output signal. Visit
ni.com/support for more information about minimizing glitches.
Counters
When multiple sample clocks on my buffered counter measurement
occur before consecutive edges on my source, I see weird behavior.
Why?
Duplicate count prevention ensures that the counter returns correct data for
counter measurement in some applications where a slow or non-periodic
external source is used.
If you searched ni.com and could not find the answers you need, contact
your local office or NI corporate headquarters. Phone numbers for our
worldwide offices are listed at the front of this manual. You also can visit
the Worldwide Offices section of ni.com/niglobal to access the branch
office Web sites, which provide up-to-date contact information, support
phone numbers, email addresses, and current events.
Symbols
% Percent.
± Plus or minus.
/ Per.
º Degree.
Ω Ohm.
A
A Amperes—the unit of electric current.
AC Alternating current.
AI 1. Analog input.
2. Analog input channel signal.
analog input signal An input signal that varies smoothly over a continuous range of values,
rather than in discrete steps.
analog output signal An output signal that varies smoothly over a continuous range of values,
rather than in discrete steps.
analog signal A signal representing a variable that can be observed and represented
continuously.
analog trigger A trigger that occurs at a user-selected point on an incoming analog signal.
Triggering can be set to occur at a specific level on either an increasing or
a decreasing signal (positive or negative slope). Analog triggering can be
implemented either in software or in hardware. When implemented in
software (LabVIEW), all data is collected, transferred into system memory,
and analyzed for the trigger condition. When analog triggering is
implemented in hardware, no data is transferred to system memory until the
trigger condition has occurred.
AO Analog output.
B
b Bit—One binary digit, either 0 or 1.
bus, buses The group of electrical conductors that interconnect individual circuitry in
a computer. Typically, a bus is the expansion vehicle to which I/O or other
devices are connected. Examples of PC buses are the PCI, AT(ISA), and
EISA bus.
C
C Celsius.
channel Pin or wire lead to which you apply or from which you read the analog or
digital signal. Analog signals can be single-ended or differential. For digital
signals, you group channels to form ports. Ports usually consist of either
four or eight digital channels.
clock Hardware component that controls timing for reading from or writing to
groups.
common-mode The ability of an electronic system to cancel any electronic noise pick-up
rejection that is common to both the positive and negative polarities of the input leads
to the instrument front end. Common mode rejection is only a relevant
specification for systems having a balanced or differential input.
common-mode signal 1. Any voltage present at the instrumentation amplifier inputs with
respect to amplifier ground.
2. The signal, relative to the instrument chassis or computer’s ground, of
the signals from a differential input. This is often a noise signal, such
as 50 or 60 Hz hum.
D
D GND Digital ground signal.
DAQ device A device that acquires or generates data and can contain multiple channels
and conversion devices. DAQ devices include plug-in devices, PCMCIA
cards, and DAQPad devices, which connect to a computer USB or 1394
(FireWire®) port. SCXI modules are considered DAQ devices.
data acquisition The general concept of acquiring data, as in begin data acquisition or data
acquisition and control. See also DAQ.
data transfer A technique for moving digital data from one system to another.
Options for data transfer are DMA, interrupt, and programmed I/O. For
programmed I/O transfers, the CPU in the PC reads data from the DAQ
device whenever the CPU receives a software signal to acquire a single data
point. Interrupt-based data transfers occur when the DAQ device sends an
interrupt to the CPU, telling the CPU to read the acquired data from the
DAQ device. DMA transfers use a DMA controller, instead of the CPU, to
move acquired data from the device into computer memory. Even though
high-speed data transfers can occur with interrupt and programmed I/O
transfers, they require the use of the CPU to transfer data. DMA transfers
are able to acquire data at high speeds and keep the CPU free for
performing other tasks at the same time.
device An electronic board that performs general analog or digital I/O functions
on one or multiple channels, connected to a PC through a bus or I/O port,
such as PCI, PXI, Ethernet, USB, or serial.
differential input An input circuit that actively responds to the difference between two
terminals, rather than the difference between one terminal and ground.
Often associated with balanced input circuitry, but also may be used with
an unbalanced source.
digital I/O The capability of an instrument to generate and acquire digital signals.
Static digital I/O refers to signals where the values are set and held, or
rarely change. Dynamic digital I/O refers to digital systems where the
signals are continuously changing, often at multi-MHz clock rates.
digital trigger A TTL level signal having two discrete levels—A high and a low level.
DMA controller chip Performs the transfers between memory and I/O devices independently of
the CPU.
driver Software unique to the device or type of device, and includes the set of
commands the device accepts.
E
E Series A standard architecture for instrumentation-class, multichannel data
acquisition devices.
edge detection A technique that locates an edge of an analog signal, such as the edge of a
square wave.
encoder A device that converts linear or rotary displacement into digital or pulse
signals. The most popular type of encoder is the optical encoder, which uses
a rotating disk with alternating opaque areas, a light source, and a
photodetector.
external trigger A voltage pulse from an external source that causes a DAQ operation to
begin.
F
FIFO First-In-First-Out memory buffer—A data buffering technique that
functions like a shift register where the oldest values (first in) come out
first. Many DAQ products and instruments use FIFOs to buffer digital data
from an A/D converter, or to buffer the data before or after bus
transmission.
The first data stored is the first data sent to the acceptor. FIFOs are often
used on DAQ devices to temporarily store incoming or outgoing data until
that data can be retrieved or output. For example, an analog input FIFO
stores the results of A/D conversions until the data can be retrieved into
system memory, a process that requires the servicing of interrupts and often
the programming of the DMA controller. This process can take several
milliseconds in some cases. During this time, data accumulates in the FIFO
for future retrieval. With a larger FIFO, longer latencies can be tolerated. In
the case of analog output, a FIFO permits faster update rates, because the
waveform data can be stored on the FIFO ahead of time. This again reduces
the effect of latencies associated with getting the data from system memory
to the DAQ device.
filter A physical device or digital algorithm that selectively removes noise from
a signal, or emphasizes certain frequency ranges and de-emphasizes others.
Electronic filters include lowpass, band-pass, and highpass types. Digital
filters can operate on numeric data to perform equivalent operations on
digitized analog data or to enhance video images.
filtering A type of signal conditioning that allows you to filter unwanted frequency
components from the signal you are trying to measure.
floating The condition where a common mode voltage exists, or may exist, between
earth ground and the instrument or circuit of interest. Neither the high, nor
the low side of a circuit is at earth potential.
floating signal sources Signal sources with voltage signals that are not connected to an absolute
reference of system ground. Also called non-referenced signal sources.
Some common examples of floating signal sources are batteries,
transformers, and thermocouples.
frequency The number of alternating signals that occur per unit time.
ft Feet.
G
glitch An unwanted signal excursion of short duration that is usually unavoidable.
ground 1. A pin.
2. An electrically neutral wire that has the same potential as the
surrounding earth. Normally, a noncurrent-carrying circuit intended for
safety.
3. A common reference point for an electrical system.
H
hardware The physical components of a computer system, such as the circuit boards,
plug-in devices, chassis, enclosures, peripherals, and cables.
hardware triggering A form of triggering where you set the start time of an acquisition and
gather data at a known position in time relative to a trigger signal.
hysteresis Lag between making a change and the effect of the change.
I
I/O Input/Output—The transfer of data to/from a computer system involving
communications channels, operator interface devices, and/or data
acquisition and control interfaces.
instrument driver A set of high-level software functions that controls a specific GPIB, VXI,
or RS232 programmable instrument or a specific plug-in DAQ device.
Instrument drivers are available in several forms, ranging from a function
callable language to a virtual instrument (VI) in LabVIEW.
instrumentation A circuit whose output voltage with respect to ground is proportional to the
amplifier difference between the voltages at its two inputs. An instrumentation
amplifier normally has high-impedance differential inputs and high
common-mode rejection.
interchannel delay Amount of time that passes between sampling consecutive channels in an
AI scan list. The interchannel delay must be short enough to allow sampling
of all the channels in the channel list, within the sample interval. The
greater the interchannel delay, the more time the PGIA is allowed to settle
before the next channel is sampled. The interchannel delay is regulated by
ai/ConvertClock.
interface Connection between one or more of the following: hardware, software, and
the user. For example, hardware interfaces connect two other pieces of
hardware.
interrupt, interrupt 1. A means for a device to notify another device that an event occurred.
request line
2. A computer signal indicating that the CPU should suspend its current
task to service a designated activity.
K
kHz Kilohertz—A unit of frequency; 1 kHz = 103 = 1,000 Hz.
kS 1,000 samples.
L
LabVIEW A graphical programming language.
lowpass filter A filter that passes signals below a cutoff frequency while blocking signals
above that frequency.
M
m Meter.
mass termination USB or DAQPad devices where all signals flow through 68-pin connectors,
as opposed to screw terminal or BNC variants.
measurement device DAQ devices, such as the M Series multifunction I/O (MIO) devices, SCXI
signal conditioning modules, and switch modules.
module A board assembly and its associated mechanical parts, front panel, optional
shields, and so on. A module contains everything required to occupy one or
more slots in a mainframe. SCXI and PXI devices are modules.
multiplex To assign more than one signal to a channel. See also mux.
N
NI National Instruments.
NI-DAQ The driver software needed to use National Instruments DAQ devices and
SCXI components. Some devices use Traditional NI-DAQ (Legacy); others
use NI-DAQmx.
NI-DAQmx The latest NI-DAQ driver with new VIs, functions, and development tools
for controlling measurement devices. The advantages of NI-DAQmx over
earlier versions of NI-DAQ include the DAQ Assistant for configuring
channels and measurement tasks for your device for use in LabVIEW,
LabWindows/CVI, and Measurement Studio; increased performance such
as faster single-point analog I/O; and a simpler API for creating DAQ
applications using fewer functions and VIs than earlier versions of
NI-DAQ.
non-referenced Signal sources with voltage signals that are not connected to an absolute
signal sources reference or system ground. Also called floating signal sources. Some
common example of non-referenced signal sources are batteries,
transformers, or thermocouples.
O
offset The unwanted DC voltage due to amplifier offset voltages added to a signal.
P
PCI Peripheral Component Interconnect—A high-performance expansion bus
architecture originally developed by Intel to replace ISA and EISA. It offers
a theoretical maximum transfer rate of 132 MB/s.
period The period of a signal, most often measured from one zero crossing to the
next zero crossing of the same slope. The period of a signal is the reciprocal
of its frequency (in Hz). Period is designated by the symbol T.
Plug and Play devices A specification prepared by Microsoft, Intel, and other PC-related
companies that result in PCs with plug-in devices that can be fully
configured in software, without jumpers or switches on the devices.
power source An instrument that provides one or more sources of AC or DC power. Also
known as power supply.
pretriggering The technique used on a DAQ device to keep a continuous buffer filled with
data, so that when the trigger conditions are met, the sample includes the
data leading up to the trigger condition.
pulse A signal whose amplitude deviates from zero for a short period of time.
pulse width The time from the rising to the falling slope of a pulse (at 50% amplitude).
PXI_STAR A special set of trigger lines in the PXI backplane for high-accuracy device
synchronization with minimal latencies on each PXI slot. Only devices in
the PXI Star controller Slot 2 can set signal on this line. For additional
information concerning PXI star signal specifications and capabilities, read
the PXI Specification located at www.pxisa.org/specs.
Q
quadrature encoder An encoding technique for a rotating device where two tracks of
information are placed on the device, with the signals on the tracks offset
by 90° from each other. This makes it possible to detect the direction of the
motion.
R
range The maximum and minimum parameters between which a sensor,
instrument, or device operates with a specified set of characteristics. This
may be a voltage range or a frequency range.
RTSI bus Real-Time System Integration bus—The National Instruments timing bus
that connects DAQ devices directly, by means of connectors on top of the
devices, for precise synchronization of functions.
S
s Seconds.
S Samples.
sample counter The clock that counts the output of the channel clock, in other words, the
number of samples taken. On devices with simultaneous sampling, this
counter counts the output of the scan clock and hence the number of scans.
scan One or more analog or digital input samples. Typically, the number of input
samples in a scan is equal to the number of channels in the input group. For
example, one pulse from the scan clock produces one scan which acquires
one new sample from every analog input channel in the group.
scan interval Controls how often a scan is initialized; is regulated by the AI Sample
Clock signal.
SCC Signal Conditioning Carriers—A compact, modular form factor for signal
conditioning modules.
sensor A device that responds to a physical stimulus (heat, light, sound, pressure,
motion, flow, and so on), and produces a corresponding electrical signal.
Primary characteristics of sensors are sensitivity, frequency range, and
linearity.
signal conditioning 1. Electronic equipment that makes transducer or other signals suitable in
level and range to be transmitted over a distance, or to interface with
voltage input instruments.
2. The manipulation of signals to prepare them for digitizing.
signal source A generic term for any instrument in the family of signal generators.
single trigger mode When the arbitrary waveform generator goes through the staging list only
once.
single-buffered Describes a device that acquires a specified number of samples from one or
more channels and returns the data when the acquisition is complete.
single-ended input A circuit that responds to the voltage on one input terminal and ground.
See also differential input.
single-ended output A circuit whose output signal is present between one output terminal and
ground.
software applications The programs that run on your computer and perform a specific
user-oriented function, such as accounting, program development,
measurement, or data acquisition. In contrast, operating system functions
basically perform the generic “housekeeping” of the machine, which is
independent of any specific application. Operating system functions
include the saving of data (file system), handling of multiple programs at
the same time (multi-tasking), network interconnection, printing, and
keyboard/user interface interaction.
software triggering A method of triggering in which you simulate an analog trigger using
software. Also called conditional retrieval.
source impedance A parameter of signal sources that reflects current-driving ability of voltage
sources (lower is better) and the voltage-driving ability of current sources
(higher is better).
T
task In NI-DAQmx, a collection of one or more channels, timing, and triggering
and other properties that apply to the task itself. Conceptually, a task
represents a measurement or generation you want to perform.
Timebase The reference signals for controlling the basic accuracy of time or
frequency-based measurements. For instruments, timebase refers to the
accuracy of the internal clock.
transducer A device that responds to a physical stimulus (heat, light, sound, pressure,
motion, flow, and so on), and produces a corresponding electrical signal.
See also sensor.
trigger 1. Any event that causes or starts some form of data capture.
2. An external stimulus that initiates one or more instrument functions.
Trigger stimuli include a front panel button, an external input voltage
pulse, or a bus trigger command. The trigger may also be derived from
attributes of the actual signal to be acquired, such as the level and slope
of the signal.
U
USB Universal Serial Bus—A 480 Mbit/s serial bus with up to 12-Mbps
bandwidth for connecting computers to keyboards, printers, and other
peripheral devices. USB 2.0 retains compatibility with the original USB
specification.
V
V Volts.
Vm Measured voltage.
W
waveform 1. The plot of the instantaneous amplitude of a signal as a function of
time.
2. Multiple voltage readings taken at a specific sampling rate.
when to use with ground-referenced disk drive power connector (PCI Express
signal sources, 4-21 devices), 3-8
differential analog input, troubleshooting, C-1 DMA, 10-1
differential connections as a transfer method, 10-4
using with floating signal sources, 4-16 changing data transfer methods, 10-5
using with ground-referenced signal controllers, 10-1
sources, 4-23 DO Sample Clock signal, 6-5
when to use with floating signal do/SampleClock, 6-5
sources, 4-15 documentation
when to use with ground-referenced conventions used in manual, xv
signal sources, 4-21 NI resources, E-1
digital related documentation, xvi
waveform acquisition, 6-3 double-buffered acquisition, 4-12
waveform generation, 6-5 drivers (NI resources), E-1
digital I/O, 6-1 duplicate count prevention, 7-35
block diagram, 6-1 enabling in NI-DAQmx, 7-38
circuitry, 6-1 example, 7-35
connecting signals, 6-9 prevention example, 7-36
DI change detection, 6-8 troubleshooting, C-3
digital waveform generation, 6-5
getting started with applications in
software, 6-10 E
I/O protection, 6-7 E Series
programmable power-up states, 6-7 differences from M Series, D-1
static DIO, 6-2 migrating applications from, D-1
timing diagrams, B-30 pinout comparison versus M Series, 3-5
triggering, 11-1 upgrading from, D-1
waveform acquisition, 6-3 edge counting, 7-2
waveform triggering, 6-3 buffered, 7-3
digital routing, 9-1 on-demand, 7-2
digital signals sample clock, 7-3
Change Detection Event, 6-8 single point, 7-2
connecting, 6-9 edge-separation measurement
DI Sample Clock, 6-4 buffered two-signal, 7-18
DO Sample Clock, 6-5 single two-signal, 7-18
digital source, triggering, 11-1 enabling duplicate count prevention in
digital waveform NI-DAQmx, 7-38
acquisition, 6-3 encoders, quadrature, 7-14
generation, 6-5
disk drive power (PCI Express), 3-8
F
features, counter, 7-33 G
field wiring considerations, 4-25 generations
filters analog output data, 5-4
counter, 7-33 buffered hardware-timed, 5-5
PFI, 8-4 clock, 9-1
PXI_STAR, 9-9 continuous pulse train, 7-21
RTSI, 9-7 digital waveform, 6-5
floating signal sources frequency, 7-22
connecting, 4-15 hardware-timed, 5-4
description, 4-15 non-buffered hardware-timed, 5-5
using in differential mode, 4-16 pulse for ETS, 7-24
using in NRSE mode, 4-19 pulse train, 7-21
using in RSE mode, 4-20 retriggerable single pulse, 7-21
when to use in differential mode, 4-15 simple pulse, 7-19
when to use in NRSE mode, 4-15 single pulse, 7-19
when to use in RSE mode, 4-16 single pulse with start trigger, 7-20
FREQ OUT signal, 7-30 software-timed, 5-4
frequency getting started, 1-1
division, 7-24 AI applications in software, 4-40
generation, 7-22 AO applications in software, 5-12
generator, 7-22 DIO applications in software, 6-10
measurement, 7-9 ghost voltages when sampling multiple
Frequency Output signal, 7-30 channels, C-1
fuse replacement ground-reference
USB-6221 BNC, A-23 connections, checking, C-1
USB-6221 Screw Terminal, A-16 settings, 4-1, 4-5
USB-6225 Mass Termination, A-44 analog input, 4-5
USB-6225 Screw Terminal, A-38
Q
quadrature encoders, 7-14
S
sample clock
analog input internal timing, B-15
R edge counting, 7-3
range, analog input, 4-2 scanning speed, 4-10
real-time system integration bus, 9-4 SCC, 2-5
reciprocal frequency measurement, 7-12 SCXI, 2-4
reference semi-period measurement, 7-8
clock buffered, 7-8
10 MHz, 9-3 single, 7-8
external, 9-2 sensors, 2-3
trigger, analog input internal timing, B-13 settings
referenced single-ended connections analog input ground-reference, 4-5
using with floating signal sources, 4-20 AO offset, 5-2
when to use with floating signal AO reference selection, 5-2
sources, 4-16 short high-quality cabling, 4-8
when to use with ground-referenced signal conditioning, 2-3
signal sources, 4-22 options, 2-4
related documentation, xvi signal descriptions, 3-2
retriggerable single pulse generation, 7-21 signal label
routing USB screw terminal devices, 1-2
analog comparison event to an output signal routing, RTSI bus, 9-4
terminal, 11-3