8

CHAPTER

Main Memory
Practice Exercises
8.1 Name two differences between logical and physical addresses.
Answer:
A logical address does not refer to an actual existing address; rather,
it refers to an abstract address in an abstract address space. Contrast
this with a physical address that refers to an actual physical address in
memory. A logical address is generated by the CPU and is translated into
a physical address by the memory management unit(MMU). Therefore,
physical addresses are generated by the MMU.
8.2 Consider a system in which a program can be separated into two
parts: code and data. The CPU knows whether it wants an instruction
(instruction fetch) or data (data fetch or store). Therefore, two base–
limit register pairs are provided: one for instructions and one for data.
The instruction base–limit register pair is automatically read-only, so
programs can be shared among different users. Discuss the advantages
and disadvantages of this scheme.
Answer:
The major advantage of this scheme is that it is an effective mechanism
for code and data sharing. For example, only one copy of an editor or
a compiler needs to be kept in memory, and this code can be shared
by all processes needing access to the editor or compiler code. Another
advantage is protection of code against erroneous modification. The
only disadvantage is that the code and data must be separated, which is
usually adhered to in a compiler-generated code.
8.3 Why are page sizes always powers of 2?
Answer:
Recall that paging is implemented by breaking up an address into a page
and offset number. It is most efficient to break the address into X page
bits and Y offset bits, rather than perform arithmetic on the address
to calculate the page number and offset. Because each bit position
represents a power of 2, splitting an address between bits results in
a page size that is a power of 2.

25
26 Chapter 8 Main Memory

8.4 Consider a logical address space of 64 pages of 1024 words each, mapped
onto a physical memory of 32 frames.
a. How many bits are there in the logical address?
b. How many bits are there in the physical address?
Answer:
a. Logical address: 16 bits
b. Physical address: 15 bits
8.5 What is the effect of allowing two entries in a page table to point to the
same page frame in memory? Explain how this effect could be used to
decrease the amount of time needed to copy a large amount of memory
from one place to another. What effect would updating some byte on the
one page have on the other page?
Answer:
By allowing two entries in a page table to point to the same page frame
in memory, users can share code and data. If the code is reentrant, much
memory space can be saved through the shared use of large programs
such as text editors, compilers, and database systems. “Copying” large
amounts of memory could be effected by having different page tables
point to the same memory location.
However, sharing of nonreentrant code or data means that any user
having access to the code can modify it and these modifications would
be reflected in the other user’s “copy.”
8.6 Describe a mechanism by which one segment could belong to the address
space of two different processes.
Answer:
Since segment tables are a collection of base–limit registers, segments
can be shared when entries in the segment table of two different jobs
point to the same physical location. The two segment tables must have
identical base pointers, and the shared segment number must be the
same in the two processes.
8.7 Sharing segments among processes without requiring that they have the
same segment number is possible in a dynamically linked segmentation
system.
a. Define a system that allows static linking and sharing of segments
without requiring that the segment numbers be the same.
b. Describe a paging scheme that allows pages to be shared without
requiring that the page numbers be the same.
Answer:
Both of these problems reduce to a program being able to reference
both its own code and its data without knowing the segment or page
number associated with the address. MULTICS solved this problem by
associating four registers with each process. One register had the address
of the current program segment, another had a base address for the stack,
another had a base address for the global data, and so on. The idea is
 Practice Exercises 27

that all references have to be indirect through a register that maps to

the current segment or page number. By changing these registers, the
same code can execute for different processes without the same page or
segment numbers.
8.8 In the IBM/370, memory protection is provided through the use of keys.
A key is a 4-bit quantity. Each 2K block of memory has a key (the storage
key) associated with it. The CPU also has a key (the protection key)
associated with it. A store operation is allowed only if both keys are
equal, or if either is zero. Which of the following memory-management
schemes could be used successfully with this hardware?
a. Bare machine
b. Single-user system
c. Multiprogramming with a fixed number of processes
d. Multiprogramming with a variable number of processes
e. Paging
f. Segmentation
Answer:
a. Protection not necessary, set system key to 0.
b. Set system key to 0 when in supervisor mode.
c. Region sizes must be fixed in increments of 2k bytes, allocate key
with memory blocks.
d. Same as above.
e. Frame sizes must be in increments of 2k bytes, allocate key with
pages.
f. Segment sizes must be in increments of 2k bytes, allocate key with
segments.
Virtual
9
CHAPTER

Memory
Practice Exercises
9.1 Under what circumstances do page faults occur? Describe the actions
taken by the operating system when a page fault occurs.
Answer:
A page fault occurs when an access to a page that has not been
brought into main memory takes place. The operating system verifies
the memory access, aborting the program if it is invalid. If it is valid, a
free frame is located and I/O is requested to read the needed page into
the free frame. Upon completion of I/O, the process table and page table
are updated and the instruction is restarted.
9.2 Assume that you have a page-reference string for a process with m
frames (initially all empty). The page-reference string has length p;
n distinct page numbers occur in it. Answer these questions for any
page-replacement algorithms:
a. What is a lower bound on the number of page faults?
b. What is an upper bound on the number of page faults?
Answer:
a. n
b. p
9.3 Consider the page table shown in Figure 9.30 for a system with 12-bit
virtual and physical addresses and with 256-byte pages. The list of free
page frames is D, E, F (that is, D is at the head of the list, E is second,
and F is last).
Convert the following virtual addresses to their equivalent physical
addresses in hexadecimal. All numbers are given in hexadecimal. (A
dash for a page frame indicates that the page is not in memory.)
• 9EF
• 111
29
30 Chapter 9 Virtual Memory

• 700
• 0FF
Answer:
• 9E F - 0E F
• 111 - 211
• 700 - D00
• 0F F - E F F
9.4 Consider the following page-replacement algorithms. Rank these algo-
rithms on a five-point scale from “bad” to “perfect” according to their
page-fault rate. Separate those algorithms that suffer from Belady’s
anomaly from those that do not.
a. LRU replacement

b. FIFO replacement

c. Optimal replacement
d. Second-chance replacement
Answer:

Rank Algorithm Suffer from Belady’s anomaly

1 Optimal no
2 LRU no
3 Second-chance yes
4 FIFO yes

9.5 Discuss the hardware support required to support demand paging.

Answer:
For every memory-access operation, the page table needs to be consulted
to check whether the corresponding page is resident or not and whether
the program has read or write privileges for accessing the page. These
checks have to be performed in hardware. A TLB could serve as a cache
and improve the performance of the lookup operation.
9.6 Consider the two-dimensional array A:

int A[][] = new int[100][100];

where A[0][0] is at location 200 in a paged memory system with pages

of size 200. A small process that manipulates the matrix resides in page
0 (locations 0 to 199). Thus, every instruction fetch will be from page 0.
For three page frames, how many page faults are generated by
the following array-initialization loops, using LRU replacement and
assuming that page frame 1 contains the process and the other two
are initially empty?
 Practice Exercises 31

a. for (int j = 0; j < 100; j++)

for (int i = 0; i < 100; i++)
A[i][j] = 0;
b. for (int i = 0; i < 100; i++)
for (int j = 0; j < 100; j++)
A[i][j] = 0;
Answer:
a. 5,000
b. 50
9.7 Consider the following page reference string:

1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6.

How many page faults would occur for the following replacement
algorithms, assuming one, two, three, four, five, six, or seven frames?
Remember all frames are initially empty, so your first unique pages will
all cost one fault each.
• LRU replacement
• FIFO replacement
• Optimal replacement
Answer:

Number of frames LRU FIFO Optimal

1 20 20 20
2 18 18 15
3 15 16 11
4 10 14 8
5 8 10 7
6 7 10 7
7 7 7 7

9.8 Suppose that you want to use a paging algorithm that requires a reference
bit (such as second-chance replacement or working-set model), but
the hardware does not provide one. Sketch how you could simulate a
reference bit even if one were not provided by the hardware, or explain
why it is not possible to do so. If it is possible, calculate what the cost
would be.
Answer:
You can use the valid/invalid bit supported in hardware to simulate the
reference bit. Initially set the bit to invalid. On first reference a trap to the
operating system is generated. The operating system will set a software
bit to 1 and reset the valid/invalid bit to valid.
32 Chapter 9 Virtual Memory

9.9 You have devised a new page-replacement algorithm that you think may
be optimal. In some contorted test cases, Belady’s anomaly occurs. Is the
new algorithm optimal? Explain your answer.
Answer:
No. An optimal algorithm will not suffer from Belady’s anomaly because
—by definition—an optimal algorithm replaces the page that will not
be used for the longest time. Belady’s anomaly occurs when a page-
replacement algorithm evicts a page that will be needed in the immediate
future. An optimal algorithm would not have selected such a page.
9.10 Segmentation is similar to paging but uses variable-sized “pages.” Define
two segment-replacement algorithms based on FIFO and LRU page-
replacement schemes. Remember that since segments are not the same
size, the segment that is chosen to be replaced may not be big enough
to leave enough consecutive locations for the needed segment. Consider
strategies for systems where segments cannot be relocated, and those
for systems where they can.
Answer:
a. FIFO. Find the first segment large enough to accommodate the
incoming segment. If relocation is not possible and no one segment
is large enough, select a combination of segments whose memories
are contiguous, which are “closest to the first of the list” and
which can accommodate the new segment. If relocation is possible,
rearrange the memory so that the first N segments large enough for
the incoming segment are contiguous in memory. Add any leftover
space to the free-space list in both cases.
b. LRU. Select the segment that has not been used for the longest
period of time and that is large enough, adding any leftover space
to the free space list. If no one segment is large enough, select
a combination of the “oldest” segments that are contiguous in
memory (if relocation is not available) and that are large enough.
If relocation is available, rearrange the oldest N segments to be
contiguous in memory and replace those with the new segment.
9.11 Consider a demand-paged computer system where the degree of mul-
tiprogramming is currently fixed at four. The system was recently mea-
sured to determine utilization of CPU and the paging disk. The results
are one of the following alternatives. For each case, what is happening?
Can the degree of multiprogramming be increased to increase the CPU
utilization? Is the paging helping?
a. CPU utilization 13 percent; disk utilization 97 percent

b. CPU utilization 87 percent; disk utilization 3 percent

c. CPU utilization 13 percent; disk utilization 3 percent

Answer:
a. Thrashing is occurring.
b. CPU utilization is sufficiently high to leave things alone, and
increase degree of multiprogramming.
 Practice Exercises 33

c. Increase the degree of multiprogramming.

9.12 We have an operating system for a machine that uses base and limit
registers, but we have modified the machine to provide a page table.
Can the page tables be set up to simulate base and limit registers? How
can they be, or why can they not be?
Answer:
The page table can be set up to simulate base and limit registers provided
that the memory is allocated in fixed-size segments. In this way, the base
of a segment can be entered into the page table and the valid/invalid bit
used to indicate that portion of the segment as resident in the memory.
There will be some problem with internal fragmentation.