O RAN - WG7.IPC HRD Opt7 2.0 v01.00

ORAN.WG7.IPC-HRD-Opt7-2.0-v01.
00
Technical Specification
O-RAN WG7
Hardware Reference Design Specification for Indoor Picocell FR1
with Split Architecture Option 7-2
Prepared by the O-RAN Alliance. Copyright © 2020 by the O-RAN Alliance.
By using, accessing or downloading any part of this O-RAN specification document, including by copying, saving, distributing,
displaying or preparing derivatives of, you agree to be and are bound to the terms of the O-RAN Adopter License Agreement
contained in Annex ZZZ of this specification. All other rights reserved.
© 2020 O-RAN Alliance All Rights Reserved

Your use is subject to the terms of the O-RAN Adopter License Agreement in Annex ZZZ 1
ORAN.WG7.IPC-HRD-Opt7-2.0-v01.00
1 Revision History
Date Revision Author Description
06/12/2020 v01.00 WG7 First Published Version
________________________________________________________________________________________________
ORAN-WG7.IPC-HRD-Opt7-2.0-v01.00
1 Contents
2 Revision History ................................................................................................................................................. 2
3 Chapter 1 Introductory Material ..................................................................................................................... 8
4 1.1 Scope ................................................................................................................................................................. 8
5 1.2 References ......................................................................................................................................................... 8
6 1.3 Definitions and Abbreviations ........................................................................................................................... 9
7 1.3.1 Definitions .................................................................................................................................................... 9
8 1.3.2 Abbreviations ............................................................................................................................................... 9
9 Chapter 2 Hardware Reference Design 1 ..................................................................................................... 13

10 2.1 O-CU Hardware Reference Design ................................................................................................................. 13
11 2.2 O-DU7-2 Hardware Reference Design .............................................................................................................. 13
12 2.2.1 O-DU7-2 High-Level Functional Block Diagram........................................................................................ 13
13 2.2.2 O-DU7-2 Hardware Design Description ...................................................................................................... 14
14 2.2.3 O-DU7-2 Hardware Components ................................................................................................................ 15
15 2.2.3.1 Digital Processing Unit ......................................................................................................................... 15
16 2.2.3.2 Hardware Accelerator ........................................................................................................................... 16
17 2.2.3.2.1 Accelerator Design Solution 1 ........................................................................................................ 16
20 2.2.3.3 Baseboard Management Controller ...................................................................................................... 23
21 2.2.4 Synchronization and Timing ...................................................................................................................... 23
22 2.2.4.1 Synchronization and Timing Design 1 ................................................................................................. 23
23 2.2.4.2 Synchronization and Timing Design 2 ................................................................................................. 24
24 2.2.5 External Interface Ports .............................................................................................................................. 24
25 2.2.6 O-DU7-2 Firmware ...................................................................................................................................... 25
26 2.2.7 Mechanical ................................................................................................................................................. 25
27 2.2.8 Power Unit ................................................................................................................................................. 27
28 2.2.9 Thermal ...................................................................................................................................................... 28
29 2.2.10 Environmental and Regulations ................................................................................................................. 28
30 2.3 O-RU7-2 Hardware Reference Design .............................................................................................................. 28
31 2.3.1 O-RU7-2 High-Level Functional Block Diagram ........................................................................................ 29
32 2.3.2 O-RU7-2 Hardware Components ................................................................................................................. 31
33 2.3.2.1 Digital Processing Unit......................................................................................................................... 32
34 2.3.2.2 RF Processing Unit ............................................................................................................................... 35
35 2.3.2.2.1 Transceiver Reference Design ........................................................................................................ 35
36 2.3.2.2.2 Power Amplifier (PA) Reference Design ....................................................................................... 41
37 2.3.2.2.3 Low Noise Amplifier (LNA) Reference Design ............................................................................. 42
38 2.3.2.2.4 RF Switch Reference Design .......................................................................................................... 45
39 2.3.2.2.5 Antenna Reference Design ............................................................................................................. 46
42 2.3.5 Mechanical ................................................................................................................................................. 51
43 2.3.6 Power Unit ................................................................................................................................................. 52
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ORAN-WG7.IPC.HRD.Opt7-2.0-v01.00
1 2.3.7 Thermal ...................................................................................................................................................... 53

3 2.4 FHGW7-2 Hardware Reference Design ............................................................................................................ 54
4 2.4.1 FHGW7-2 High-Level Functional Block Diagram ...................................................................................... 54
5 2.4.2 FHGW7-2 Hardware Components ............................................................................................................... 55
9 2.4.5 Mechanical ................................................................................................................................................. 59
10 2.4.6 Power ......................................................................................................................................................... 60
11 2.4.7 Thermal ...................................................................................................................................................... 60
13 2.5 FHGW7-2→8 Hardware Reference Design ........................................................................................................ 61
14 2.5.1 FHGW7-2→8 High-Level Functional Block Diagram ................................................................................. 61
15 2.5.2 FHGW7-2→8 Hardware Components ........................................................................................................... 62
19 2.5.5 Mechanical ................................................................................................................................................. 67
20 2.5.6 Power ......................................................................................................................................................... 67
21 2.5.7 Thermal ...................................................................................................................................................... 68
23 Annex 1: Parts Reference List .......................................................................................................................... 69

24 Annex ZZZ: O-RAN Adopter License Agreement .......................................................................................... 70
25 Section 1: DEFINITIONS ................................................................................................................................................ 70
26 Section 2: COPYRIGHT LICENSE ................................................................................................................................. 71
27 Section 3: FRAND LICENSE .......................................................................................................................................... 71
28 Section 4: TERM AND TERMINATION ........................................................................................................................ 72
29 Section 5: CONFIDENTIALITY ..................................................................................................................................... 72
30 Section 6: INDEMNIFICATION ..................................................................................................................................... 72
31 Section 7: LIMITATIONS ON LIABILITY; NO WARRANTY .................................................................................... 72
32 Section 8: ASSIGNMENT ............................................................................................................................................... 73
33 Section 9: THIRD-PARTY BENEFICIARY RIGHTS .................................................................................................... 73
34 Section 10: BINDING ON AFFILIATES ........................................................................................................................ 73
35 Section 11: GENERAL .................................................................................................................................................... 73
36
37 Tables
38 Table 2-1: The Processor Feature List .............................................................................................................................. 15
39 Table 2-2: The Memory Channel Feature List ................................................................................................................. 15
40 Table 2-3: Accelerator Hardware Feature List ................................................................................................................. 16
41 Table 2-4: Accelerator Firmware Feature List .................................................................................................................. 17
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1 Table 2-5: Accelerator Hardware Component List ........................................................................................................... 19

2 Table 2-6: Accelerator Hardware Feature List ................................................................................................................. 22
3 Table 2-7: Accelerator Firmware Feature List .................................................................................................................. 22
4 Table 2-8: External Port List ............................................................................................................................................ 24
5 Table 2-9: Power supply unit feature list .......................................................................................................................... 28
6 Table 2-10: Environmental Features................................................................................................................................. 28
7 Table 2-11: Resource requirement for 2T2R O-RU7-2 ...................................................................................................... 32
8 Table 2-12: Resource requirement for 4T4R O-RU7-2 ...................................................................................................... 32
9 Table 2-13: Interface requirements of the Transceiver ..................................................................................................... 35
10 Table 2-14: Payload with DPD in Digital Device (GBPS Rx/Tx) .................................................................................... 36
11 Table 2-15: Payload with DPD in Transceiver (GBPS Rx/Tx) ........................................................................................ 36
12 Table 2-16: RF specifications in Transceiver ................................................................................................................... 37
13 Table 2-17: PA Requirements ......................................................................................................................................... 41
14 Table 2-18: Interface requirements of the transmit PA..................................................................................................... 41
15 Table 2-19: One stage LNA Requirements ....................................................................................................................... 42
16 Table 2-20: Two stage LNA Requirements ...................................................................................................................... 43
17 Table 2-21: Interface requirements of the RF switch ....................................................................................................... 45
18 Table 2-22: RF Switch Requirements ............................................................................................................................... 45
19 Table 2-23: Antenna Requirements .................................................................................................................................. 46
20 Table 2-24: Interface requirements of the clocking .......................................................................................................... 47
21 Table 2-25: Clocking RF requirements ............................................................................................................................ 48
22 Table 2-26: External Port List .......................................................................................................................................... 50
23 Table 2-27: power unite requirement for 2T2R and 4T4R O-RU7-2 ................................................................................. 52
24 Table 2-28: Power unite function ..................................................................................................................................... 52
25 Table 2-29: Environmental Features................................................................................................................................. 53
26 Table 2-30: Interface requirements of the FPGA ............................................................................................................ 55
27 Table 2-31: FPGA Resource usage for FHGW7-2 ............................................................................................................. 56
28 Table 2-32: Requirements of the PLL device ................................................................................................................... 57
30 Table 2-34: Requirements of the power unit .................................................................................................................... 60
31 Table 2-35: Interface Requirements of the FPGA ............................................................................................................ 62
32 Table 2-36: FPGA Resource Usage for FHGW7-2-→8 ....................................................................................................... 63
33 Table 2-37: Requirements of the PLL device ................................................................................................................... 64
35 Table 2-39: Power Unit Requirements ............................................................................................................................. 68
36
37 Figures
38 Figure 2-1: O-DU7-2 Functional Block Diagram. .............................................................................................................. 14
39 Figure 2-2: O-DU7-2 Hardware Block Diagram ................................................................................................................ 14
40 Figure 2-3: Accelerator Design 1 without optional NIC Device ...................................................................................... 18
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1 Figure 2-4: Accelerator Design 1 with optional NIC Device ........................................................................................... 18

2 Figure 2-5: Example 2-chip FPGA-based Hardware Acceleration in O-DU7-2 ................................................................ 21
3 Figure 2-6: Structured ASIC Accelerator Design ............................................................................................................. 23
4 Figure 2-7: O-DU7-2 Timing Synchronization .................................................................................................................. 24
5 Figure 2-8: HW Acceleration Board Timing and Synchronization .................................................................................. 24
6 Figure 2-9: External interfaces reference design .............................................................................................................. 25
7 Figure 2-10: Mother Board Layout Diagram .................................................................................................................... 26
8 Figure 2-11: Chassis Mechanical Diagram ....................................................................................................................... 27
9 Figure 2-12: General Block Diagram of Option A (2T2R Shown) ................................................................................. 29
10 Figure 2-13: General Block Diagram of Option A (4T4R Shown) ................................................................................. 29
11 Figure 2-14: General Block Diagram of Option B (2T2R Shown) .................................................................................. 30
12 Figure 2-15: General Block Diagram of Option B (4T4R Shown) .................................................................................. 30
13 Figure 2-16: General Block Diagram of Option C (2T2R Shown) .................................................................................. 31
14 Figure 2-17: General Block Diagram of Option C (4T4R Shown) .................................................................................. 31
15 Figure 2-18: Power estimation for 2T2R O-RU7-2 ............................................................................................................ 33
16 Figure 2-19: Power estimation for 4T4R O-RU7-2 ............................................................................................................ 34
17 Figure 2-20: FPGA Reference Design Diagram ............................................................................................................... 34
18 Figure 2-21: Transceiver Reference Design Diagram (Optional elements are highlighted in Grey ). .............................. 40
19 Figure 2-22: PA Reference Design Diagram .................................................................................................................... 42
20 Figure 2-23: One Stage LNA Diagram ............................................................................................................................. 44
21 Figure 2-24: Two-Stage LNA Diagram ............................................................................................................................ 44
22 Figure 2-25: RF Switch Reference Design Diagram ........................................................................................................ 46
23 Figure 2-26: Whip Antenna .............................................................................................................................................. 47
24 Figure 2-27: PLL Reference Design Diagram .................................................................................................................. 49
25 Figure 2-28: SFP+ case and connector ............................................................................................................................. 50
26 Figure 2-29: RJ45 interface .............................................................................................................................................. 51
27 Figure 2-30: O-RU7-2 Shell Mechanical Diagram............................................................................................................. 51
28 Figure 2-31: PoE Reference Design Diagram .................................................................................................................. 53
29 Figure 2-32: FHGW7-2 General Block Diagram ............................................................................................................... 54
30 Figure 2-33: FHGW7-2 Digital Processing Block Diagram............................................................................................... 56
31 Figure 2-34: CLK reference design for FHGW7-2 ............................................................................................................ 57
34 Figure 2-37: AC power interface ...................................................................................................................................... 59
35 Figure 2-38: Shell Mechanical Diagram .......................................................................................................................... 59
36 Figure 2-39: FHGW7-2→8 General Block Diagram ........................................................................................................... 61
37 Figure 2-40: FHGW7-2→8 Digital Processing Block Diagram ........................................................................................... 63
38 Figure 2-41: CLK reference design for FHGW7-2→8......................................................................................................... 64
41 Figure 2-44: AC power interface ...................................................................................................................................... 66
42 Figure 2-45: Shell Mechanical Diagram .......................................................................................................................... 67
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________________________________________________________________________________________________
1 Chapter 1 Introductory Material
2 1.1 Scope
3 This Technical Specification has been produced by the O-RAN.org.
4 The contents of the present document are subject to continuing work within O-RAN WG7 and may change following
5 formal O-RAN approval. Should the O-RAN.org modify the contents of the present document, it will be re-released by
6 O-RAN Alliance with an identifying change of release date and an increase in version number as follows:
7 Release x.y.z
8 where:
9 x the first digit is incremented for all changes of substance, i.e. technical enhancements,
10 corrections, updates, etc. (the initial approved document will have x=01).
11 y the second digit is incremented when editorial only changes have been incorporated in the
12 document.
13 z the third digit included only in working versions of the document indicating incremental
14 changes during the editing process. This variable is for internal WG7 use only.
15 The present document specifies system requirements and high-level architecture for the FR1 Picocell Indoor
16 deployment scenario as specified in the Deployment Scenarios and Base Station Classes document [1].
17
18 1.2 References
19 The following documents contain provisions which, through reference in this text, constitute provisions of the present
20 document.
21 [1] ORAN-WG7.DSC.0-V01.00 Technical Specification, ‘Deployment Scenarios and Base Station Classes for White
22 Box Hardware’. https://www.o-ran.org/specifications
23 [2] 3GPP TR 21.905: "Vocabulary for 3GPP Specifications".
24 [3] 3GPP TR 38.104: "NR; Base Station (BS) radio transmission and reception".
25 http://www.3gpp.org/ftp//Specs/archive/38_series/38.104/38104-g10.zip
26 [4] ORAN-WG4.CUS.0-v01.00 Technical Specification, ‘O-RAN Fronthaul Working Group Control, User and
27 Synchronization Plane Specification’. https://www.o-ran.org/specifications
28 [5] 3GPP TS 38.113:"NR: Base Station (BS) Electromagnetic Compatibility (EMC)".
29 http://www.3gpp.org/ftp//Specs/archive/38_series/38.113/38113-f80.zip
30 [6] ORAN-WG7. IPC. HAR-v01.00 Technical Specification, ‘Indoor Pico Cell Hardware Architecture and
31 Requirement Specification’. https://www.o-ran.org/specifications.
32 [7] ORAN-WG7. IPC. HRD.O8-v01.00 Technical Specification, ‘Indoor Pico Cell BS Hardware Reference Design
33 Specifications with Fronthaul Split Option 8 and FR1’. https://www.o-ran.org/specifications
34
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1 1.3 Definitions and Abbreviations
2 1.3.1 Definitions
3 For the purposes of the present document, the terms and definitions given in 3GPP TR 21.905 [1] and the following
4 apply. A term defined in the present document takes precedence over the definition of the same term, if any, in 3GPP
5 TR 21.905 [2]. For the base station classes of Pico, Micro and Macro, the definitions are given in 3GPP TR 38.104 [3].
6 Carrier Frequency: Center frequency of the cell.

7 F1 interface: The open interface between O-CU and O-DU7-2 as defined by 3GPP TS 38.473 between CU and DU.
8 Integrated architecture: In the integrated architecture, the O-RU and O-DUx are implemented on one platform. Each
9 O-RU and RF front end is associated with one O-DU7-2. They are then aggregated to O-CU and connected by F1
10 interface.
11 Split architecture: The O-RUx and O-DUx are physically separated from one another in this architecture. A switch
12 may aggregate multiple O-RUxs to one O-DUx. O-DUx switch and O-RUxs are connected by the fronthaul interface as
13 defined in WG4.
14 Transmission Reception Point (TRxP): Antenna array with one or more antenna elements available to the network
15 located at a specific geographical location for a specific area.
16 1.3.2 Abbreviations
17 For the purposes of the present document, the abbreviations given in [2] and the following apply. An abbreviation
18 defined in the present document takes precedence over the definition of the same abbreviation, if any, as in [2].
19 7-2 Fronthaul interface split option as defined by O-RAN WG4, also referred to as 7-2x
20 3GPP Third Generation Partnership Project
21 5G Fifth-Generation Mobile Communications
22 5GC 5G Core
23 ACS Adjacent Channel Selectivity
24 ADC Analog to Digital Converter
25 ASIC Application Specific Integrated Circuit
26 ATA Advanced Technology Attachment
27 BBDEV Baseband Device
28 BH Backhaul
29 BMC Baseboard Management Controller
30 BPSK Binary Phase Shift Keying
31 BS Base Station
32 CISPR International Special Committee on Radio Interference
33 CFR Crest Factor Reduction
34 CU Centralized Unit as defined by 3GPP
35 COM Cluster Communication
36 CPRI Common Public Radio Interface
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1 CPU Central Processing Unit

2 CRC Cyclic Redundancy Check
3 DAC Digital to Analog Converter
4 DDC Digital Down Conversion
5 DDR Double Data Rate
6 DIMM Dual-Inline-Memory-Modules
7 DL Downlink
8 DPD Digital Pre-Distortion
9 DPDK Data Plane Development Kit
10 DSP Digital Signal Processor
11 DU Distributed Unit as defined by 3GPP
12 DUC Digital Up Conversion
13 ECC Error Correcting Code
14 eCPRI evolved Common Public Radio Interface
15 EMC Electro Magnetic Compatibility
16 EVM Error Vector Magnitude
17 FCC Federal Communications Commission
18 FEC Forward Error Correction
19 FFT Fast Fourier Transform
20 FH Fronthaul
21 FHGW Fronthaul Gateway
22 FHGWx Fronthaul gateway with no FH protocol translation, supporting an O-DUx with split option x and
23 an O-RUx with split option x, with currently available options 66, 7-27-2 and 88
24 FHGWxy Fronthaul Gateway that can translate fronthaul protocol from an O-DUx with split option x to an
25 O-RUy with split option y, with currently available option 7-28.
26 FHHL Full Height Half Length
27 FPGA Field Programmable Gate Array
28 GbE Gigabit Ethernet
29 GNSS Global Navigation Satellite System
30 GPP General Purpose Processor
31 GPS Global Positioning System
32 HARQ Hybrid Automatic Repeat request
33 HHHL Half Height Half Length
34 IEEE Institute of Electrical and Electronics Engineers
35 IFFT Inverse Fast Fourier Transform
36 IMD Inter Modulation Distortion
37 I/O Input/Output
38 JTAG Joint Test Action Group
39 L1 Layer 1
40 LDPC Low-Density Parity Codes
41 LRDIMM Load-Reduced Dual In-line Memory Module
42 LTE Long Term Evolution
________________________________________________________________________________________________
1 LVDS Low-Voltage Differential Signaling

2 MAC Media Access Control
3 MCP Multi-Chip Package
4 MH Midhaul
5 MIG Memory Interface Generator
6 MII Media-Independent interface
7 MIMO Multiple Input Multiple Output
8 MU-MIMO Multiple User MIMO
9 NEBS Network Equipment-Building System
10 NetConf Network Configuration Protocol
11 NFV Network Functions Virtualization
12 NIC Network Interface Controller
13 NR New Radio
14 O-CU O-RAN Centralized Unit as defined by O-RAN
15 O-DUx A specific O-RAN Distributed Unit having fronthaul split option x where x may be 6, 7-2 (as
16 defined by WG4) or 8
17 O-RUx A specific O-RAN Radio Unit having fronthaul split option x, where x is 6, 7-2 (as defined by
18 WG4) or 8, and which is used in a configuration where the fronthaul interface is the same at the O-
19 DUx
20 OCXO Oven Controlled Crystal Oscillator
21 PCIe Peripheral Component Interface Express
22 PDCP Packet Data Convergence Protocol
23 PHY Physical Layer
24 PMBus Power Management Bus
25 POE Power over Ethernet
26 PPS Pulse Per Second
27 PRACH Physical Random Access Channel
28 QAM Quadrature Amplitude Modulation
29 QPSK Quadrature Phase Shift Keying
30 QSFP Quad Small Form-factor Pluggable
31 RAN Radio Access Network
32 RDIMM Registered Dual In-line Memory Module
33 RF Radio Frequency
34 RoE Radio over Ethernet
35 RU Radio Unit as defined by 3GPP
36 RX Receiver
37 SATA Serial ATA
38 SDU Service Data Unit
39 SFP Small Form-factor Pluggable
40 SFP+ Small Form-factor Pluggable plus
41 SOC System On Chip
42 SPI Serial Peripheral Interface
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1 SSD Solid State Drive

2 TCXO Temperature Compensate Crystal Oscillator
3 TDP Thermal Design Power
4 TR Technical Report
5 TS Technical Specification
6 TX Transmitter
7 UL Uplink
8 USB Universal Serial Bus
9 WG Working Group
10
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1 Chapter 2 Hardware Reference Design 1

2 This chapter describes a white box hardware reference design example for indoor Picocell deployment scenario. It
3 includes O-CU, O-DU7-2 and FHGW7-2/FHGW7-28 for IPC deployment scenario.
4 2.1 O-CU Hardware Reference Design

5 The O-CU white box hardware is the platform that perform the O-CU function of upper L2 and L3. The hardware
6 systems specified in this document meet the computing, power and environmental requirements of use cases
7 configurations and feature sets of RAN physical node. These requirements are described in the early hardware
8 requirement specification as well as in the use cases document. The O-CU hardware includes the chassis platform,
9 mother board, peripheral devices and cooling devices. The mother board contains processing unit, memory, the internal
10 I/O interfaces, and external connection ports. The midhaul (MH) and backhaul (BH) interface are used to carry the
11 traffic between O-CU and O-DU7-2 as well as O-CU and core network. The other hardware functional components
12 include: the storage for software, hardware and system debugging interfaces, board management controller, just to name
13 a few; the O-CU designer will make decision based on the specific needs of the implementation.
14 The HW reference design of O-CU is the same as O-DU7-2 except for the need of HW accelerator, thus detail design
15 will be described in O-DU7-2 section 2.2.
16 2.2 O-DU7-2 Hardware Reference Design

17 The O-DU7-2 white box hardware is the platform that performs the O- DU7-2 functions such as upper L1 and lower L2
18 functions. The hardware systems specified in this document meet the computing, power and environmental
19 requirements of use case’s configurations and feature sets of RAN physical node. These requirements are described in
20 the early hardware requirement specification as well as in the use cases document. The O-DU7-2 hardware includes the
21 chassis platform, mother board, peripheral devices and cooling devices. The mother board contains processing unit,
22 memory, the internal I/O interfaces, and external connection ports. The fronthaul and backhaul interface are used to
23 carry the traffic between O-RU7-2/FHGW7-2/FHGW7-28 and O-DU7-2 as well as O-CU and O-DU7-2. The O-DU7-2
24 design may also provide an interface for hardware accelerator if that option is preferred. The other hardware functional
25 components include: the storage for software, hardware and system debugging interfaces, board management controller,
26 just to name a few; the O-DU7-2 designer will make decision based on the specific needs of the implementation.
27 Note that the O-DU7-2 HW reference design is also feasible for O-CU and integrated O-CU/ O-DU7-2.
28 2.2.1 O-DU7-2 High-Level Functional Block Diagram
29 Figure 2-1 shows the major functional blocks of O-DU7-2. The digital processing unit handles the baseband processing
30 workload. To make the processing more efficient, an accelerator can be used to assist with the baseband workload
31 processing. The memory devices include the random-access memory (RAM) for temporary storage of data while flash
32 memory is used for codes and logs. The storage device is for persistent storage. The external network cards can be used
33 for fronthaul or backhaul connection. The baseboard management controller (BMC) is a microcontroller which
________________________________________________________________________________________________
1 monitors hardware operation on motherboard. The clock circuits provide digital processing unit with required clock
2 signals.
Accelerator DDR RAM
Flash
Memory
Baseboard
Digital Processing Unit
Management
Controller Storage
Drives
Ethernet
Card
Clock
4 Figure 2-1: O-DU7-2 Functional Block Diagram.
5 2.2.2 O-DU7-2 Hardware Design Description
6 Figure 2 2 describes the various components and connections inside the O-DU7-2 white box.
8 Figure 2-2: O-DU7-2 Hardware Block Diagram

________________________________________________________________________________________________
1 As described in the previous section, the O-DU7-2 hardware can be implemented with difference design choices. Here,
2 we use a SoC design-based as an example which performs most of the workload for O-DU7-2. The accelerator can be
3 used to perform other functions based on the overall performance requirement. Several Ethernet controllers are also
4 used for front haul link, back haul link and remote console control connection. The other parts include: RAM, flash
5 memory, and hard drive storage. The JTAG and USB ports are provided for hardware debug and local connection if
6 needed. Finally, BMC block is mainly responsible for monitoring the hardware status of the motherboard.
7 2.2.3 O-DU7-2 Hardware Components
8 In this section, we describe the details of the O-DU7-2 hardware component’s requirements, their features and
9 parameters. The component selection is based on the use case requirements which are listed in the hardware architecture
10 and requirements document [6].
11 2.2.3.1 Digital Processing Unit

12 This example of the digital processing unit in O-DU7-2 is based on the General Purpose Processor (GPP).
13 a. Digital Processing Unit Requirement

14 The GPP requirements are listed in the following table.
15 Table 2-1: The Processor Feature List

Item Name Description
# of Cores 16
# of Threads 32
Base Frequency 2.20 GHz
Max Turbo Frequency 3.00 GHz
Cache 22 MB
Thermal Design Power (TDP) 100W
Max Memory Size (dependent on memory type) 512 GB
Memory Types DDR4
Max # of Memory Channels 4
16
17 Interfaces: The interface specification on the main board are as follows:

18 Memory Channel Interfaces: The system memory capacity, type and related information are described in the
19 following table.
20
21 Table 2-2: The Memory Channel Feature List

Memory Types DDR4
# of Memory Channels 4
ECC LRDIMM Up to 512GB
ECC RDIMM Up to 256GB
Memory Speed 2666/2400/2133MHz
DIMM Sizes 128GB, 64GB, 32GB, 16GB
Memory Voltage 1.2 V
22
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1 PCIe: PCIe Gen 3 should be supported by the processor. There are total of 32 PCIe lanes with 128 Gb/s
2 bandwidth. The 32 PCIe lanes can be divided into two x16 slots by using a riser card.
3 Ethernet: The system should be capable to offer aggregated 48 Gb/s Ethernet bandwidth. The breakout the
4 ports are discussed in later section. When higher Ethernet bandwidth required, an Ethernet card can be
5 installed in one of the PCIe slot.
6 b. Digital Processing Unit Design
7 The digital processing unit is a system-on-a-chip (SoC) device which is a 64-bit multi-core server class
8 processor. This SoC includes an integrated Platform Controller Hub (PCH), integrated high-speed I/O,
9 Integrated Memory Controllers (IMC), and four integrated 10 Gigabit Ethernet ports.
10 The SOC supports 512-bit wide vector processing instruction set. It also supports hardware virtualization to
11 enable dynamic provisioning of services as communication service providers extend network functions
12 virtualization (NFV). Figure 2-2 shows the major functional blocks of the digital processing unit.
13 2.2.3.2 Hardware Accelerator

14 Hardware accelerators can be used in O-DU7-2 to offload computationally intensive functions and to optimize the
15 performance under varying traffic and loading conditions. The acceleration functional requirements and implementation
16 are system designer’s choice; however, the O-DU7-2 shall meet the minimum system performance requirements under
17 various loading and deployment conditions. In most cases, a Field Programmable Gate Array (FPGA) or Application
18 Specific Integrated Circuit (ASIC) based PCIe card can be used to optimize the system performance. The FPGA(s) are
19 part of a Network Interface Controller (NIC) that further provides connectivity services.
20 2.2.3.2.1 Accelerator Design Solution 1
21 Channel coding for Low-Density Parity Codes (LDPC) and fronthaul compression requires a significant amount of bit
22 level processing and is well suited to a fine-grained FPGA architecture and/or low cost/power structured ASIC. Options
23 include:
24  Virtualization: Multi-channel DMA, Virtual machine integration, load balancing functions
25  Look-aside FEC: LDPC (de)coding, Polar (de)coding, Rate (De)Matcher, (De) Interleaver, Cyclic Redundancy
26 Check (CRC), Hybrid Automatic Repeat request (HARQ) retransmission
27  Bump-in-wire Fronthaul: compression / decompression for latency and bandwidth reduction
28 a. Accelerator Requirements
29 Hardware and firmware requirements for this accelerator design are given in Table 2-3 and Table 2-4,
30 respectively.
31 Table 2-3: Accelerator Hardware Feature List

PCIe (Interface with digital processing

Gen4 x16 (and lower)
unit）
Form factor FHHL
Connectivity 2x QSFP28/56
FPGA Logic Elements: 1437K
________________________________________________________________________________________________
M20K Memory: 139Mb
Quad A53 Hard Processor Sub-system
100Gb xHAUL for FH, BH & MH traffic shaping. Optional FPGA

NIC Device
co-processing.
DDR Main 8+8+1GB DDR4
Flash (FPGA images) >=1 Gbit
BMC Telemetry, Security, remote upgrade
Clocking For O-RAN C1, C2, C3 & C4
Fronthaul eCPRI, RoE IEEE1914.3, O-RAN WG4
GPS SMA for 1 PPS & 10MHz (in/out)
Operating Temperature (ambient) NEBS Compliant
Power <75W (without optional NIC device)
Clock Accuracy Low-Jitter, configurable clock ranging from 10MHz to 750MHz.

Option for OCXO (TCXO as standard)
3 Table 2-4: Accelerator Firmware Feature List

Remote system upgrade Securely upgradable FPGA flash image
Queuing 64 Queues supported equally split between UL & DL.

NR LDPC Encoding with, interleaving and rate-matching.
NR LDPC Decoding with sub-block de-interleaving function of

reverse rate matching.
LDPC Acceleration
Early Termination, CRC attachment and HARQ buffering.
5G Throughput: DL 14.8Gbps, UL 3.2Gbps
Load balancer distributes the pending encoder/decoder requests to

Load Balancing (channel coding)
encoder/decoders
Code block based interface.
Software enablement by BBDEV API (DPDK)
Descriptor Format (channel coding)
https://www.dpdk.org/
https://doc.dpdk.org/guides/prog_guide/bbdev.html
In-line compression/decompression for Mu-Law, block-floating
Fronthaul Compression
point and quantization according to the O-RAN WG4 specification.
Support for:
 FPGA Flashing upgrade
Open programmable acceleration  Firmware version reporting
environment  PCIe diagnostics
 Ethernet diagnostics
 Temperature and voltage telemetry information
________________________________________________________________________________________________
2 b. Accelerator Design
3 Figure 2-3 illustrates Accelerator Design 1 without optional NIC Device. Figure 2-4 illustrates the Accelerator
4 Design 1 with optional NIC Device.
FPGA
Digital
Processing Unit PCIe Gen 4x16 FH 2x2x56Gbps
Or lower (200G) Connectivity & L1 Or lower
Processing.
L3,L2,L1(part)
C1,2,3,4 Sync
1PPS & 10MHz

SMA
5
6 Figure 2-3: Accelerator Design 1 without optional NIC Device
FPGA
Digital
Processing Unit PCIe PCIe Gen 4x8 FH 2x2x56Gbps
Gen4x16 Or lower (100G) Connectivity & L1 Or lower
Processing.
L3,L2,L1(part)
C1,2,3,4 Sync
1PPS & 10MHz
SMA
100Gb
PCIe Gen 4x8

Or lower (100G) NIC
9 Figure 2-4: Accelerator Design 1 with optional NIC Device

11 The O-DU7-2 system is typically implemented using a multi-core processor and one or more hardware accelerators.
12 Parts of O-DU7-2 protocol stack can be implemented in software running on the multi-core processors, some of the
13 computationally intensive L1 and L2 functions are offloaded to FPGA-based or similar hardware accelerators. This is a
14 programmable hardware, which provides both flexibility and high computing capabilities.
15 a. Accelerator Requirement
16 The accelerator unit comprises one or more FPGAs (e.g., two FPGAs), sufficient amount of DDR4 memory,
17 and synchronization circuitry where one of FPGAs is used for L1 functional offload and the other one is used
18 to perform fronthaul connectivity functions/protocols. The FPGA for L1 offload uses dedicated cores for
________________________________________________________________________________________________
1 channel encoding/decoding as well as FPGA and processing resources for running L1 functions such as but
2 not limited to rate matching and de-matching, interleaving and scrambling, demodulation and HARQ buffer
3 management as well as OFDM modulation/demodulation and channel estimation.
4 Key features of the FPGA-based accelerator include:
5  2X10/25G eCPRI or Ethernet open fronthaul interface
6  Built-in SyncE/IEEE 1588v2 synchronization + external reference timing
7  L1 offloading options
8 ‒ LDPC encoding and decoding
9 ‒ Polar encoding and decoding
10 ‒ HARQ management with on board DDR memory (including DDR controller and interfaces)
11 ‒ Other L1 offloading candidates include PRACH detection, MIMO encoding and decoding,
12 channel estimation
13 ‒ Partial or full L1 functions can be offloaded. It is recommended to offload the user-plane
14 channel coding chain and part of or the entire control-plane channel coding chain to the
15 hardware accelerator.
16  PCIe Gen3 x16, two Gen4 x8, or PCIe Gen3 x16 bifurcated to two Gen3 x8
17  GPP supported
18  Standard PCIe FHHL card (It is assumed that the hardware accelerators further perform NIC functions).
19  2x SFP28 for 25G Ethernet
20  8GB DDR4 memory for buffering
21  Power consumption not to exceed 75W
22 The accelerator requirements are summarized in Table 2-5.
23 Table 2-5: Accelerator Hardware Component List
Item Name Description for FPGA 1 Description for FPGA 2
System Logic cells - 930K System Logic cells - 1,143K

CLB LUT - 425K CLB LUT - 523K
SoC SDFEC -8 CLB Flip-Flops -1,045K
Resources DSP Slices - 4,272 DSP Slices - 1,968
BRAM - 38.0Mb BRAM - 34.6Mb
URAM - 22.5Mb URAM - 36.0Mb
Form Factor FHHL PCIe Form Factor
x8 Gen1, Gen2, Gen3 interface to FPGA 2 and
PCIe Interface x8 Gen1, Gen2, Gen3 interface to FPGA 1
have x16 to two x8 bifurcation
On Board Total Capacity 4 GB in PL, upgradeable to 8GB Total Capacity 4 GB in PL, upgradeable to 8GB
Memory Total Capacity 2 GB in PS, upgradeable to 4GB Total Capacity 2 GB in PS, upgradeable to 4GB
________________________________________________________________________________________________
Network 2xSFP28 optical interfaces to FPGA2

Interface(s) (User Configurable, includes 10/25 Ethernet)
Other External
Micro USB for JTAG support (FPGA programming and debug) and access to BMC
Interface(s)
Graphical GUI for monitoring the basic board parameters, monitoring temperature alerts, firmware upgrades for
User interface BMC
• Power sequencing and reset

• Field upgrades
Board
• FPGA configuration and control
Management
• Clock configuration
Controller
• I2C bus access
• USB 2.0
Operating
-5°C - 55°C
Temperature
Power < 75 W
Clocking Low-Jitter, configurable clock ranging from10MHz to 750MHz

Options 1 PPS input and output with assembly option for OCXO and TCXO
1
2
3
4 The following are the accelerator’s functional and interface requirements.
5 Functional offload requirements:
6 One of the candidate functions for offloading is the LDPC encoder and decoder, which typically consists of
7 computationally intensive and relatively highly power consuming functions. It must be noted that neither
8 software implementation in CPU nor soft FPGA logic implementation would provide a highly power efficient
9 solution while meeting/exceeding 3GPP NR user-plane encoder/decoder throughput and latency requirements,
10 rather a hardened implementation of the FEC functions would be very power efficient. Downlink and uplink
11 throughputs of up to 40Gbps and 18Gbps, respectively, are shown feasible with this architecture. Other
12 candidate L1 functions for acceleration include CRC generation, segmentation, bit-level/sub-block
13 interleaving and scrambling as well as FFT/IFFT processing, for which an FPGA can be used.
14 For other symbol processing L1 functions which require heavy multiply and accumulation operations, FPGAs
15 1 and 2 have DSP blocks that can efficiently perform these operations. Polar encoding and/or decoding on the
16 control-plane can also be offloaded to FPGA 1 resulting in high throughputs and low latencies.
17 Interface requirements:
18 PCIe: PCIe interface is widely used to provide interface between the GPP and hardware accelerators. FPGA
19 devices have dedicated PCIe hard IP which facilitate implementation and quick setup of PCIe interface. They
20 support both PCIe Gen3 x16 or PCIe Gen4 x8, which allow the FPGA device to interface with any GPP
21 supporting either PCIe Gen3 x16 or PCIe Gen4 x8 interface.
22 Fronthaul: FPGA devices can support various speed grades and any fronthaul protocols, customers can use
23 off-the-shelf eCPRI or Ethernet IPs to quickly implement and configure any fronthaul interface protocol.
24 Serial transceivers: FPGA devices have SerDes resources to implement various connectivity speeds (e.g., 33
25 Gb/s) per SerDes, 10G/25G/50G/100G Ethernet connections can use these SerDes resources.
________________________________________________________________________________________________
1 Ethernet MAC speed: FPGA devices have hardened implementations of Ethernet MAC that support speeds
2 of 100 Gbps and above. The Ethernet MAC IP allows power-efficient implementation of high speed Ethernet
3 connectivity. In the example shown in Figure 2-3, FPGA 1 and FPGA 2 can use the hard 100Gbps MAC IPs
4 to connect each other, allowing the L1 and fronthaul functions to be distributed across these two FPGAs with
5 less connectivity overhead. For other Ethernet MACs such as 10G/25G Ethernet, they provide soft Ethernet
6 MAC IPs, so when implementing eCPRI or Ethernet fronthaul functions, 10G/25G Ethernet MAC can be
7 used.
9 The hardware accelerator supports GPP. Figure 2-5 illustrates a two-chip acceleration architecture comprising
10 two FPGAs with multi-lane PCIe interfaces toward the CPU and external connectivity toward O-RU7-2(s) via
11 eCPRI and O-CU(s) through GbE connectivity. The example architecture further depicts multi-lane Gen3 or
12 Gen4 PCIe interfaces between each FPGA and the CPU. The FPGAs communicate through high-bandwidth
13 Ethernet (GbE) transport.
FPGA1
X86 or ARM-based (L1 Offload)
CPU
(L2 and Partial L1)
Inter-Chip
Interface
100G Ethernet
F1 Interface
Ethernet (10/25G) FPGA2
(Connectivity)
[Bifurcated] PCIe Interface Fronthaul Interface

PCIe Gen3x16 (Gen4x8) 10/25G
14 100G Ethernet/eCPRI
15 Figure 2-5: Example 2-chip FPGA-based Hardware Acceleration in O-DU7-2
17 Channel coding for LDPC and fronthaul compression requires a significant amount of bit level processing and is well
18 suited to a fine-grained structured ASIC. Features include:
19  Virtualization: Multi-channel DMA, Virtual machine integration, load balancing functions

20  Look-aside FEC: Turbo (de)coding, LDPC (de)coding, Rate (De)Matcher, (De) Interleaver, CRC, HARQ
21 retransmission & (de) interleaver.
22 a. Accelerator Requirement
23 Accelerator Hardware and Firmware features are listed in Table 2-6 and Table 2-7, respectively.
24
________________________________________________________________________________________________
1 Table 2-6: Accelerator Hardware Feature List

PCIe Gen3 x16
Form factor HHHL
DDR DDR4 (64-bit +ECC), 2667Mbps Interface for HARQ buffering
Board Management Controller Telemetry, Security.
Power <35W
5 Table 2-7: Accelerator Firmware Feature List

Queuing 64 Queues supported equally split between UL & DL.
NR LDPC Encoding with, interleaving and rate-matching.
NR LDPC Decoding with sub-block de-interleaving function of

LDPC Acceleration reverse rate matching.
Early Termination, CRC attachment and HARQ buffering.
5G Throughput: DL 23Gbps, UL 8Gbps
Load balancer distributes the pending encoder/decoder requests to

Load Balancing (channel coding)
encoder/decoders
Code block and transport block based interface.
Software enablement by BBDEV API (DPDK)

Descriptor Format (channel coding)
https://www.dpdk.org/
https://doc.dpdk.org/guides/prog_guide/bbdev.html
8 The following diagram shows the structured ASIC based accelerator design.
9
________________________________________________________________________________________________
Structured ASIC
Digital
Processing Unit PCIe Gen 3x16
Or lower (100G) LDPC
Code/Transport
L3,L2,L1(part)
Block
1
2 Figure 2-6: Structured ASIC Accelerator Design
3 2.2.3.3 Baseboard Management Controller

4 BMC is used to perform hardware power control (power on, power off and power cycle), monitor hardware status
5 (temperatures, voltages, etc), monitor Basic I/O System (BIOS)/ Unified Extensible Firmware Interface (UEFI)
6 firmware status, and log system events. It provides remote access via shared or dedicated NIC. System user can do
7 console access via serial or physical/Kernel-based Virtual Machine (KVM). The BMC has dedicated RAM and flash
8 memory. It provides access via serial port or Ethernet port. Figure 2-2 describes the BMC connections with related
9 components.
10 2.2.4 Synchronization and Timing
11 2.2.4.1 Synchronization and Timing Design 1

12 This section describes the synchronization and timing mechanism that is used in the O-DU7-2.
13 a. Hardware Requirements
14 The O-DU7-2 shall support following timing synchronization methods:
15 1. GPS Synchronization
16 2. Ethernet based IEEE1588V2 Synchronization
17 3. BeiDou Synchronization
18 4. BeiDou and GPS switching
19 b. Hardware Design
20 Depending on the timing distribution topologies used, the O-DU7-2 system clock is able to synchronize with
21 the Grand Master Clock (GMC) using IEEE1588 via either the front haul NIC or backhaul NIC, or
22 synchronizing timing using Global Navigation Satellite System (GNSS). In the case of IEEE1588, the
23 Physical Hardware Clock (PHC) within the NIC is synchronized with the GMC first, then the O-DU7-2 system
24 clock is synchronized with the PHC. The O-DU7-2 is also capable to provide clock to the O-RU7-2 via front
25 haul if needed. When GNSS becomes available to O-DU7-2, it will be able to synchronize the system clock to
26 Coordinated Universal Time (UTC). Figure 2-7 outlines the O-DU7-2 timing synchronization mechanisms.
________________________________________________________________________________________________
GNSS
1pps
System
PHC PHC
Clock
NIC NIC
Backhaul Fronthaul
2 Figure 2-7: O-DU7-2 Timing Synchronization
4 2.2.4.2 Synchronization and Timing Design 2

5 This section describes the synchronization and timing mechanism that is used in the hardware accelerator board.
7 Each hardware accelerator board that supports connectivity functions (e.g., O-RAN fronthaul) in O-DU7-2
8 must be able to support external synchronization I/O and to receive or transmit 1 PPS reference clock source
9 in order to ensure synchronization across network.
11 The accelerator board can operate in the master or slave mode when supporting IEEE 1588v2
12 timing/synchronization. It can generate 1 PPS reference clock for synchronization in the master mode and can
13 receive the 1 PPS reference clock in the slave mode for internal synchronization. The timing circuitry of the
14 accelerator board is shown in Figure 2-8. Two FPGA SerDes transceivers are used to receive and transmit
15 SyncE TX and RX clocks.
16
17
SerDes
SyncE TX Clock
SyncE RX Clock SerDesFPGA
TCXO/OCXO Reference
(IEEE 1588v2
1 PPS
PLL Stack)
GPS (1 PPS) Other Clocks
18
19 Figure 2-8: HW Acceleration Board Timing and Synchronization
20 2.2.5 External Interface Ports
21 The external interfaces of O-DU7-2 are described below.
23 The following table shows the external ports or slots that the system provided.
24 Table 2-8: External Port List

________________________________________________________________________________________________
Ethernet Octave Gigabit Ethernet LAN connectors

Dual 10GbE Base-T Ethernet connectors
Dual 10GbE SFP+ Faber Ethernet connectors
2x100G QSFP28 or 2x25G SFP28
USB 2 USB 3.0 ports
Serial Port 1 COM port via RJ45
Antenna port 1 SMA connector for GNSS
1
3 The digital processing unit is a SOC device which provides the external ports described in the hardware
4 requirement section. The system includes 2 USB 3.0 ports, and the serial RS232 port that can be used for
5 Console Redirection, e.g. Out-of-Band Management. The system provides eight 1Gbps and four 10Gbps
6 Ethernet ports. There are two or four 25G eCPRI ports in system depends on the accelerator card used. The
7 system also provides a RF interface to connect GNSS antenna. The following diagram outlines the external
8 interfaces that supported.
2 USB 3.0 GNSS

Ports Antenna
Port
O-DU 7-2
Serial Port
Ethernet
Ports
10 Figure 2-9: External interfaces reference design
11 2.2.6 O-DU7-2 Firmware
12 BIOS and BMC firmware are needed in the system and shall be installed.
13 2.2.7 Mechanical
14 The mechanical design for mother board, chassis, and cooling are listed in this section.
15  Mother Board
16 The mechanical layout of the mother board shows the location of major components and interface ports. The
17 following diagram also provides the dimension of the board.
18
19
________________________________________________________________________________________________
2 Figure 2-10: Mother Board Layout Diagram
3  Chassis
4 The 1U rack mount chassis contains the layout of the power supply, Solid State Drive (SSD) and fans. The
5 chassis dimension is showed in following figure.
________________________________________________________________________________________________
1
2 Figure 2-11: Chassis Mechanical Diagram
5 c. Cooling
6 The system installs 4x 40x28mm PWM fans for the cooling. Up to 6 fans can be installed if needed.
7 2.2.8 Power Unit
8 In a fully loaded system with two PCIe slots populated with 75W each, the system power consumption should be less
9 than 400W. The total system power requirement shall be kept less than 80% of the power supply capacity.
11 The power is provided by 500W High-Efficiency power supply with Power Management Bus (PMBus) 1.2.
12 The power support input and output power rails are listed below.
13 AC Input: 100-240V, 50-60Hz, 6.6A max
14 DC Output: +3.3V: 12A
15 +5V: 15A
16 +5V standby: 3A
17 +12V: 41A
18 -12V: 0.2A
19 b. Hardware Requirements
20 The O-DU7-2 chassis includes one 500W power supply unit. The power supply unit is auto-switching capable,
21 which enables it to automatically sense and operate at a 100v to 240v input voltage. The power supply unit
22 features are listed in the following table.
________________________________________________________________________________________________
1 Table 2-9: Power supply unit feature list

Output connectors 24pin/8pin/4+4pin/HDD/I2C
Dimension (W x D x H) 3.9 x 7.1 x 1.6 inch
Maximum Output Power +3.3V: 12A
+5V: 15A
+12V: 41A
-12V: 0.2A
+5Vsb: 3A
Rated Input Voltage/Current 100-240Vac / 6.6A max
Rated Input Frequency 50-60HZ
Inrush current Less than 30A
2 2.2.9 Thermal
3 Active cooling with up to 6 fans is integrated in the chassis.
4 The hardware acceleration cards described in Section 2.2.2.2 use passive cooling and a custom heatsink and is equipped
5 with temperature sensors. It is designed to operate in temperatures ranging from -5°C to +55°C.
6 2.2.10 Environmental and Regulations
7 The O-DU7-2 hardware system is RoHS Compliant. The power supply unit is EMC FCC/CISPR Class B compliant.
8 Table 2-10 lists the environmental related features and parameters.
9 Table 2-10: Environmental Features

Operating Temperature -5°C to +55°C
Non-operating Temperature -40°C to 70°C
Operating Relative Humidity 8% to 90% (non-condensing)
Non-operating Relative Humidity 5% to 95% (non-condensing)
10 The hardware accelerator described in Section 2.2.2.2 is designed to operate in indoor environments and in
11 temperatures ranging from -5°C to +55°C.
12 2.3 O-RU7-2 Hardware Reference Design

13 In this section we describe, the HW reference design of all O-RU7-2 components including block diagram, HW
14 components, synchronization and timing, mechanical design, power supply, thermal, and environment requirements.
________________________________________________________________________________________________
1 2.3.1 O-RU7-2 High-Level Functional Block Diagram
2 General block diagrams for 2T2R and 4T4R O-RU7-2 examples are shown below.
3 Note that:
4 1. The digital block is referring to the digital processing unit in the reference design section.
5 2. The clock PLL block is referring to the synchronization and timing unit in the reference design section.
6 3. The rest of the blocks are referring to the RF processing unit in the reference design section.
bypass enable
Rx0 RFFE
enable
Tx0 TxVGA
PA
SERDES ORx0
Digital ORx1
Port A
SPI
Tx1 TxVGA PA
enable
RFFE
Network SPI Clean
Clock Clock Rx1
bypass enable
Transceiver
Clock PLL TRx

Reference
8 Figure 2-12: General Block Diagram of Option A (2T2R Shown)
bypass enable
Rx0 RFFE
enable
Tx0 TxVGA
PA
SERDES ORx0
Digital ORx1
SPI
Tx1 TxVGA PA
enable
RFFE
Network SPI Clean
Clock Clock Rx1
bypass enable
Transceiver
Port A
bypass enable
RFFE
Rx0
Tx0 TxVGA
PA
enable
Clock PLL TRx ORx0

Reference
enable
TxVGA PA
ORx1
RFFE
Tx1
bypass enable
Rx1
10 Figure 2-13: General Block Diagram of Option A (4T4R Shown)

________________________________________________________________________________________________
bypass enable
Rx0 RFFE
enable
Tx0
PA
SERDES ORx0
Digital ORx1
Port A
SPI
Tx1
PA
enable
RFFE
Network SPI Clean
Clock Clock Rx1
bypass enable
Transceiver
Clock PLL TRx

Reference
3 Figure 2-14: General Block Diagram of Option B (2T2R Shown)
bypass enable
Rx0 RFFE
enable
Tx0
PA
SERDES ORx0
Digital ORx1
SPI
Tx1
PA
enable
RFFE
Network SPI Clean
Clock Clock Rx1
bypass enable
Transceiver
Port A
bypass enable
RFFE
Rx0
Tx0
PA
enable
Clock PLL TRx ORx0

Reference
enable
ORx1 PA
RFFE
Tx1
bypass enable
Rx1
5 Figure 2-15: General Block Diagram of Option B (4T4R Shown)
________________________________________________________________________________________________
enable
Rx0
enable
Tx0
PA
SERDES ORx0
Digital ORx1
Port A
SPI
Tx1
PA
enable
Network SPI Clean

Clock Clock Rx1
enable
Transceiver
Clock PLL
2 Figure 2-16: General Block Diagram of Option C (2T2R Shown)
enable
Rx0
enable
Tx0
PA
SERDES ORx0
Digital ORx1
SPI
Tx1
PA
enable
Network SPI Clean

Clock Clock Rx1
enable
Transceiver
Port A
Rx0
enable
PA
Tx0
enable
Clock PLL TRx ORx0

Reference
enable
ORx1
PA
Tx1
enable
Rx1
4 Figure 2-17: General Block Diagram of Option C (4T4R Shown)
5 2.3.2 O-RU7-2 Hardware Components
6 In Section 2.3.1, we presented many possible O-RU7-2 block diagrams for reference design. In this section, we describe
7 their functionality, interfaces and performance of every block in the RF Processing Unit. Since device integration is an
8 ongoing activity, chip boundaries may be fluid and some functionalities may move from one block to another or entire
________________________________________________________________________________________________
1 functionalities may be absorbed into other blocks. The sections below describe the functional blocks independent of
2 which physical device they may reside in.

4 The digital processing unit of O-RU7-2 is mainly for performing tasks related to FH interface, lower L1, RF interface,
5 and OAM.
6 i. FPGA Solution Design 1

7 The digital processing unit of O-RU7-2 is mainly for performing FH interface, lower L1, RF interface, and OAM
8 functions.
9 a. FPGA Requirement
10 The following items are the main requirement for the O-RU7-2:
11  Interface requirement: One lane of bi-direction Serdes targeting eCPRI will be @10Gbps for FH split
12 option 7-2. Four lanes of bi-direction JESD204B Serdes will be used for 2T2R. Eight lanes of bi-
13 direction JESD204B Serdes will be used for 4T4R
14  Resource requirement: FPGA resource requirements for 2T2R and 4T4R are shown in Table 2-11 and
15 Table 2-12.
16 Table 2-11: Resource requirement for 2T2R O-RU7-2

Module FF LUT BRAM18 DSP
Model A 343800 171900 1000 900
IFFT & CP+ 7763 5323 27 23
IFFT & CP- 7763 5323 27 23
PRACH frontend 4000 3000 32 50
DUC 4820 4346 0 108
DDC 4820 4346 0 108
CFR 11470 6136 22 36
DPD 34269 13250 188 87
JESD204B 4314 4285 0 0
Fronthaul(eCPRI) 10000 8000 1 0
Other 8000 5000 100 12
Total 97219 59009 397 447
17
18 Table 2-12: Resource requirement for 4T4R O-RU7-2

Module FF LUT DSP BRAM18
Resource Mapping 10000 8000 0 102
PreCoding & pilot lns 5000 4000 16 4
________________________________________________________________________________________________
IFFT+CP 6466 3952 15 75
Resource De-Mapping 10000 8000 0 181
FFT+CP 6466 3952 15 75
PRACH Filtering 8000 6000 36 16
Sub-Total 45932 33904 82 453
ChFIR 2832 2686 84 0
DUC 5148 3756 36 0
CFR 25676 12372 96 48
DPD 45770 17643 105 217
AGC 1000 600 8 4
DDC 1716 1252 12 0
UL_ChFIR 2832 2686 84 0
JESD2048 9900 11127 0 0
eCPRI 15000 14000 0 50
total 155806 100026 507 772
2  Processor requirement: For device model A, the processor will be used, one is used for device control
3 and management plane functions, the other one is for Digital Pre-Distortion (DPD) feedback path. For
4 device model C, dual-core ARM cortex-A53 will be used, similarly one is used for device control and
5 management plane functions, the other one is for DPD feedback path.
6  Power requirement: Power estimations for 2T2R and 4T4R are shown in Figure 2-18 and Figure 2-19.
8 Figure 2-18: Power estimation for 2T2R O-RU7-2
________________________________________________________________________________________________
2 Figure 2-19: Power estimation for 4T4R O-RU7-2
3  Speed grade, environmental requirement: -2L, 0℃ to 110℃
4 b. FPGA Design
5 This solution of the digital processing unit incorporates FPGA and a processor. The FPGA handles high
6 speed digital processing such as low L1, FH, DDC, DUC, CFR and so on. All functions are listed in the
7 previous section. The processor is used for hardware device configuration and the OAM function. The FPGA
8 and the processor core can be integrated into one SOC or implemented into two devices. Here the FPGA and
9 the processor core are integrated into one SOC device.
MIG
DDR JESD204B Transceiver
Processor
SPI
Flash
SPI
FPGA 245.76MHz
1.92MHz PLL
156.25MHz
Debug
IIC
SFP+
Power:3.3V 2.5V 1.8V 1.35V 1.2V 0.9V

10
11 Figure 2-20: FPGA Reference Design Diagram
12 For the processor portion, the internal RAM resource may not be enough. So the external DDR is needed to
13 let the processor handle more RAM consuming functions such as operation system or stack protocols like
14 Network Configuration Protocol (NetConf) Client. For the O-RU7-2 design, the DDR3 with 256Mb*16bit
15 memory capacity is enough. The interface between the DDR and processor can be memory interface
16 generator (MIG).The external Flash is used to store operation system related files, calibration information
________________________________________________________________________________________________
1 of the RF portion, NetConf related files, FPGA firmware and so on. For this O-RU7-2 design, the flash with
2 2Gb memory capacity is enough. The online debug function is performed by external Ethernet PHY with
3 an RJ45 connector. This allows the administrator to visit the internal function of the O-RU7-2 and control it.
4 The interface between the DDR and processor can be Media-Independent interface (MII). The Ethernet
5 PHY device can be very general 100M Ethernet Transceiver. The FPGA has one serdes lane connected to
6 optical module to perform the fronthaul link between O-RU7-2 and O-DU7-2 /FHGW7-2.Another 4 serdes
7 lanes of the FPGA are needed to connect one transceiver of the O-RU7-2 to transmit or receive IQ sample
8 by the interface of JESD204B while the FPGA needs synchronized clock signals to work well. The
9 interface between PLL and FPGA should be Low-Voltage Differential Signaling (LVDS).
10 2.3.2.2 RF Processing Unit

11 For the RF processing unit of O-RU7-2, it will perform functionalities of ADC, DAC, LO, down converter, up converter
12 and etc.
13 2.3.2.2.1 Transceiver Reference Design
14 For the O-RU7-2 the sampling function and frequency conversion function can be performed by transceiver. The
15 purpose of using the transceiver is to saving power and size of the PCB. The Transceiver is to convert between high
16 speed baseband data and a low-level RF for both transmit and receive signal chain. In addition, the transceiver is
17 responsible for orchestration of control signals not limited to the PA enable, LNA enable, LNA bypass as well as other
18 required system level signals.
20 Include the requirements for this component.
21  Interface Requirements: The interface requirements for the Transceivers are list in Table 2-13.
22 Table 2-13: Interface requirements of the Transceiver
High Speed Data High speed data represents the baseband information being transmitted or received.
Depending on the configuration of the ORAN device, various bandwidths may be
supported leading to a range of payload rates. Options for data include parallel data paths,
JESD204B and JESD204C. Up to 8 lanes in each direction may be supported although
fewer is preferred. Options such as DPD and numeric precision will impact the payload
rate. Several options are shown in the following table. All data represents IQ 16-bit
(N=16) precision. Some devices support IQ 12 bit (N’=12) which may reduce the required
data rates accordingly. The tables below assume 1 ORx for 2 TRx. From Table 2-14 and
Table 2-15, the number of lanes required may be determined by dividing the total bit rates
shown by the capacity of a lane, typically 12.5 GBPS for JESD204B and 25 GBPS for
JESD204C.
Reference Clock The transceiver should receive a reference for internal clock and LO synthesis needs. This
(Device Clock) reference clock can function as the JESD204 Device Clock where the interface is by
SERDES. The specific clock frequency is determined by the operation mode of the
transceiver and may range from 1Hz upward.
SYSREF If the transceiver supports SERDES, then it should accept a SYSREF signal from the clock
or data source as appropriate. The number and configuration for the SYSREF is
________________________________________________________________________________________________
dependent on the operating mode of the transceiver.
SYNCB If the transceiver supports SERDES, then it should also support a SYNCB for each link as
appropriate.
Control Control of the transceiver is by way of 3 or 4 wire SPI or IIC functioning as a slave.
Support for 1.8V control is required and tolerance of 3.3V is preferred. The transceiver
may optionally include a separate SPI master for control of peripheral devices as required.
GPIO The transceiver may optionally include GPIO for controlling peripherals including but not
limited to PAs, LNAs and other devices. These GPIOs should at a minimum support 1.8V
outputs but the specifics will be determined by the connected devices. The GPIO should
also support input from peripheral devices. Input should at a minimum support 1.8V logic
with tolerance of 3.3V preferred.
Tx Enable The transceiver should provide an output to support enabling and disabling the external
devices in the transmit chain such as a TxVGA (optional) and PA.
Rx Enable The transceiver should provide an output to support enabling and disabling the external
devices in the transmit chain such as a RF Front End Module or LNA.
LNA Bypass The transceiver should provide an output to support bypassing the LNA appropriately in
the condition of a large blocker if so required.
RF Outputs RF outputs including the main Tx signal should support 50 ohm or 100 ohms signalling.
These outputs can be either single ended or differential.
RF Inputs RF inputs including the main Rx and the Observation Rx (ORx) (for DPD) should support
50 ohm or 100 ohms signalling. These inputs can be either single ended or differential.
The device should support at least 1 ORx.
2 Table 2-14: Payload with DPD in Digital Device (GBPS Rx/Tx)

Bandwidth Parallel JESD204B JESD204C Parallel JESD204B JESD204C
(MHz)
2T2R 4T4R
20 2.95/5.9 3.69/7.37 3.04/6.08 5.9/11.8 7.37/14.75 6.08/12.17
50 5.9/11.8 7.37/14.75 6.08/12.17 11.8/23.59 14.75/29.49 12.17/24.33
100 11.8/23.59 14.75/29.49 12.17/24.33 23.59/47.19 29.49/58.98 24.33/48.66
4 Table 2-15: Payload with DPD in Transceiver (GBPS Rx/Tx)

Bandwidth Parallel JESD204B JESD204C Parallel JESD204B JESD204C
(MHz)
2T2R 4T4R
20 1.97/1.97 2.46/2.46 2.03/2.03 3.93/3.93 4.92/4.92 4.06/4.06
________________________________________________________________________________________________
50 3.93/3.93 4.92/4.92 4.06/4.06 7.86/7.86 9.83/9.83 8.11/8.11
100 7.86/7.86 9.83/9.83 8.11/8.11 15.73/15.73 19.66/19.66 16.22/16.22
1  Algorithm Requirements: The transceiver is required to provide appropriate algorithms to sustain RF

2 operation including but not limited to Rx AGC, Tx Power control. DPD and CFR may be included
3 either in the transceiver or in the digital baseband device making the trade-offs in Payload shown in
4 Table 2-11 and Table 2-12.
5  Device Configuration: The transceiver should support either 2T2R or 4T4R. In addition, at least one
6 ORx path should be supported. Additional ORx paths are allowed as required for the application.
7  Power Dissipation: Total dissipation of the TRx should be less than 6W for 4T4R.
8  RF Specifications are given in Table 2-16.
10 Table 2-16: RF specifications in Transceiver

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS
Center Frequency 650 6000 MHz
Transmitter Synthesis 450 MHz
Bandwidth
Transmitter Large 200 MHz
Signal Bandwidth
Transmitter Attenuation 0 32 dB Signal-to-noise ratio (SNR)
Power Control Range maintained for attenuation between
0 dB and 20 dB
Transmitter Attenuation 0.05 dB
Power Control
Resolution
Adjacent Channel 20 MHz LTE at −12 dBFS
Leakage Ratio
(ACLR)
−66 dB 75 MHz < f ≤ 2800 MHz
In Band Noise Floor 0 dB attenuation; in band noise
falls 1 dB for each dB of
attenuation for attenuation
between 0 dB and 20 dB
−154.5 dBm/Hz 600 MHz < f ≤ 3000 MHz
Out of Band Noise 0 dB attenuation; 3 ×bandwidth/2
Floor offset
−153 dBm/Hz 600 MHz < f ≤ 3000 MHz
Maximum Output 0 dBFS, continuous wave tone
Power into 50 Ω load, 0 dB transmitter
attenuation
6 dBm 600 MHz < f ≤ 3000 MHz
Third Order Output OIP3 0 dB transmitter attenuation
Intermodulation
Intercept Point
27 dBm 600 MHz < f ≤ 5700 MHz
________________________________________________________________________________________________

Error Vector Magnitude EVM
(Third Generation
Partnership Project
(3GPP) Test Signals)
1900 MHz LO 0.6 % 50 kHz RF PLL loop bandwidth
3800 MHz LO 0.53 % 300 kHz RF PLL loop bandwidth
OBSERVATION ORx
RECEIVER
Center Frequency 450 6000 MHz
Gain Range 30 dB IIP3 improves decibel for decibel
for the first 18 dB of gain
attenuation; QEC performance
optimized for 0 dB to 6 dB of
attenuation only
Analog Gain Step 0.5 dB For attenuator steps from 0 dB to
6 dB
Receiver Bandwidth 450 MHz
Maximum Useable PHIGH 0 dB attenuation; increases
Input Level decibel
for decibel with attenuation;
continuous wave corresponds to
−1 dBFS at ADC
−11 dBm 75 MHz < f ≤ 3000 MHz
Integrated Noise −58.5 dBFS 450 MHz integration bandwidth
−57.5 dBFS 491.52 MHz integration
bandwidth
Third-Order Input IIP3 Maximum observation receiver
Intermodulation gain; test condition: PHigh - 11
Intercept Point dB/tone
Narrow Band
1900 MHz 15 dBm
2600 MHz 16.5 dBm
3800 MHz 18 dBm
Wide Band
IM3 products>130 MHz at
1900 MHz 13 dBm baseband; test condition: PHigh -
2600 MHz 11 dBm 11 dB/tone ; 491.52 MSPS
38000 MHz 13 dBm
Third-Order IM3
Intermodulation
Product
−70 dBc 600 MHz < f ≤ 3000 MHz
Spurious-Free Dynamic SFDR 64 dB Non IMx related spurs, does not
Range include HDx; (PHIGH − 11) dB input
signal
Harmonic Distortion (PHIGH − 11) dB input signal
Second Order Harmonic HD2 −80 dBc In band HD falls within ±100
________________________________________________________________________________________________

Distortion Product MHz
−73 dBc Out of band HD falls within ±225
MHz
Third-Order Harmonic HD3 −70 dBc In band HD falls within ±100
Distortion Product MHz
−65 dBc Out of band HD falls within ±225
MHz
RECEIVERS
Center Frequency 6000 MHz
Gain Range 30 dB
Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6
dB
1 dB Attenuator steps from 6 dB to 30
dB
Receiver Bandwidth 200 MHz
Maximum Useable PHIGH 0 dB attenuation, increases
Input Level decibel
for decibel with attenuation;
continuous wave = 1800 MHz;
corresponds to −1 dBFS at ADC
−11 dBm 75 MHz < f ≤ 3000 MHz
Noise Figure NF 0 dB attenuation, at receiver port
12 dB 600 MHz < f ≤ 3000 MHz
Input Third-Order IIP3
Intercept Point
Difference Product, IIP3, d

2600 MHz (Wideband) 17 dBm Two (PHIGH − 9) dB tones near band
2600 MHz (Midband) 21 dBm edge
Sum Product, IIP3, s
2600 MHz (Wideband_ 20 dBm Two (PHIGH − 9) dB tones, at
bandwidth/6 offset from the LO
HD3 HD3 (PHIGH − 6) dB continuous wave
tone at bandwidth/6 offset from
the LO
−66 dBc 600 MHz < f ≤ 4800 MHz
1
3 For the O-RU7-2 the sampling function and frequency conversion function can be performed by transceiver.
4 Usually the transceiver is integrated by ADC, DAC, LO, down converter, up converter and so on. The block
5 diagram of transceiver design is shown in Figure 2-21.
________________________________________________________________________________________________
SCLK
CSB
SPI Port SDO
SDIO
REF Clock In Clock,
SYSREF
Synchronization
Ext LO/Clock In
& Synthesis CPIO1
GPIO2
Control
GPIO3
Interface
GPIO#
Receiver Block 4
Receiver Block 3
Receiver Block 2 Decimation
Receiver Block 1 pFIR
Decimation
AGCpFIR
Decimation
Rx4 ADC Tuning
AGCpFIR
Decimation
Rx3 ADC RSSI
Tuning
AGCpFIR
Rx2 ADC Overload
RSSI
TuningAGC
Rx1 ADC Device Managemen
Overload
RSSI
Tuning
t
Device Managemen
Overload
RSSIt
Device Managemen
Overload t
Device Management
Transmit Block 4 SYNCIN

Transmit Block 3
Transmit Block 2
SERDES Out
Transmit Block 1
Interpolation
Interpolation
pFIR JESD204B/C SERDES In
Tx4 DAC Tuning
Interpolation
pFIR Serial Interface
Tx3 DAC Device Managemen
TuningInterpolation
pFIRt
Tx2 DAC SYNC OUT
Device Managemen
TuningpFIRt
Tx1 DAC Device Management
Tuning
Device Managemen t
DPD Engine
Obs ervation
Receiver
Decimation
pFIR
ORx1 AGC
ORx2
ADC Tuning
ORx3
ORx4 RSSI
Overload
Device Management
Optional
Features
1
2 Figure 2-21: Transceiver Reference Design Diagram (Optional elements are highlighted in Grey ).
3 The definition of the input/output lines are as follows:

4  REF Clock In is the differential reference input to the on-chip synthesizer. This may also function as the
5 SERDES Device Clock.
6  SYSREF is a JESD204B/C differential synchronization signal.
7  Ext LO/Clock Input is an optional input that can be used as an alternate LO or clocking signal.
8  Rx1 through Rx4 are differential receiver inputs to their respective cores.
9  Tx1 through Tx4 are differential transmitter output from their respective cores.
10  ORx1 through ORx4 are differential observation receiver inputs.
11  SCLK is the serial control clock input.
12  CSB is the active low device select for the control interface.
13  SDO is the serial data output for the control interface. This pin may be omitted for 3-pin control
14 implementations.
15  SDIO is a bidirectional serial data interface. In 4-pin mode, this pin functions as the serial data input.
16  GPIO1 – GPIO# are general purpose IO signals used for interrupts, enables, test mode and resets. These
17 are used as interface and control for peripheral devices including controllers, TxVGAs, PA, LNA and
18 similar devices where SPI control is too slow.
19  SYNCIN are differential pins associated with the receiver channels of the JESD204 interface. In not
20 used, they are typically grounded. Up to 4 pair may be supported.
21  SERDES Out are differential JESD204B/C data output interfaces. Up to 8 lanes may be active.
22  SERDES In are differential JESD204B/C data input interfaces. Up to 8 lanes may be active.
________________________________________________________________________________________________
1  SYNCOUT are differential pins associated with the transmitter channels of the JESD204 interface. If
2 not used, do not connect. Up to 4 pair may be supported.
3 2.3.2.2.2 Power Amplifier (PA) Reference Design
4 The Power Amplifier boosts the RF output to the level required for the base station class.
6 The PA should have large enough gain to reduce the need for an additional driver. This will reduce cost and
7 PCB space. The output power should be at least 27dBm (30dBm for 500mW/port to compensate for the loss of
8 switch and antenna filter). The ACLR should be greater than 47dBc according to the related 3GPP test mode.
9 DPD is needed to reduce the power consumption. The P1 dB requirement is closely related to the DPD
10 algorithm.
11 Table 2-17: PA Requirements
Frequency band Band41 Band78 Additional Information
Gain >33dB >33dB
P3dB >34dBm >34dBm ACLR>=47dBc with DPD@100MHz NR

27dBm (30dBm for 500mW/port)
>37dBm(500mW/port)
Input return loss <-15dB <-15dB
Output return loss <-15dB <-15dB
Switching Speed <1us <1us
HD2 >28dBc >28dBc CW 27dBM
HD3 >30dBc >30dBc CW 27dBm
12
13  Interface Require
14 The interface requirements of the transmit PA are listed in Table 2-17.

15
16 Table 2-18: Interface requirements of the transmit PA
Enable The enable input should be compatible with 1.8V logic and tolerate 3.3V as required. A
logic high enables the PA. A logic low disables the device and places it in a minimum
dissipation mode.
RF Outputs RF outputs support 50-ohm single ended to properly interface to a directional coupler,
isolator, switch or antenna.
________________________________________________________________________________________________
RF Inputs RF inputs should support 50 ohm, single ended match to the transceiver output or preamp.
RF power detector Power detector (optional)
2  Power Dissipation: Dissipation while enabled should not exceed ~3W.
5 RFin is the input to the PA, RFout is the output of the PA. Vcc and Vbias are the power inputs of the PA. PAEN is
6 the control pin to disable or enable the PA. The input and output should match to 50 ohm as much as possible
7 to reduce the reflection. Vcc and Vbias need capacitors to reduce the DC power ripples and give a short route to
8 reduce the RF energy leakage. Figure 2-22 shows the details.
Vcc
RFout
RFin
RFEN
9
10 Figure 2-22: PA Reference Design Diagram
11 2.3.2.2.3 Low Noise Amplifier (LNA) Reference Design
12 The purpose of the LNA is to boost the Rx signal to a level that can nominally interface directly to the transceiver. This
13 block will typically be a 2-stage amplifier with a 2nd stage bypass. The frontend will also include a TR switch to shunt
14 any Tx signal to a termination away from the amplifier.
16 The requirements of the LNA are listed here.
17  Interface Requirements: The interface requirements of the transmit LNA are listed in Table 2-19.
18 Table 2-19: One stage LNA Requirements
Parameter Band 41 Band 78 Additional Information
NF <1dB <1dB
Gain >15dB >15dB
P1dB >18dBm >18dBm
________________________________________________________________________________________________
IP3 >30dBm >30dBm 2 Tone CW -15dBm
K >1 >1 up to f = 12.5 GHz
Max input power >15dBm >15dBm
2  Device Configuration: Single or dual device.
3  Power Dissipation: Less than 500 mW for a dual when device is fully enabled in receive mode.
4  RF Specifications: For LNA unit, it should have larger enough gain to reduce extra driver amplifier for
5 cost and PCB space. The NF figure of LNA should small enough to overcome the loss of switch and
6 filter.
7 Table 2-20: Two stage LNA Requirements
Frequency band Band41 Band78 Additional Information
NF <1 dB <1.5 dB
High gain >=32 dB High gain >=32 dB
Gain
Low gain >=16 dB Low gain >=16 dB
P1dB >18dBm >18dBm
IP3 >30dBm >30dBm 2 Tone CW -15dBm
K >1 >1 up to f = 12.5 GHz
Max input power >15dBm >15dBm
10 The reference designs for one stage LNA and two-stage LNA are given.
11  One stage LNA
________________________________________________________________________________________________
1 RFin is the input port of the LNA. RFout is the output of the LNA. Vcc is the power input of the LNA. LNA
2 EN is the control pin to disable or enable the LNA. The input match to 50 ohm as much as possible to
3 reduce the reflection. But for output of the LNA, it is hard to get best Noise figure and the output return loss.
4 Compromise is needed between NF and return loss. Usually the return loss should be around -10dB or -
5 12dB. Also is should be very careful to assure the stability of the LNA in a large bandwidth. Vcc needs
6 capacitors to reduce the DC power ripples and give a short route to reduce the RF energy leakage. Figure
7 2-23 shows the details.
Vcc
RFout
RFin
LNAEN
8
9 Figure 2-23: One Stage LNA Diagram
10  Two stage LNA
11 RFin is the input port of the LNA. RFout is the output of the LNA. Vcc is the power input of the LNA. LNA
12 EN is the control pin to disable or enable the LNA. The input matches to 50 ohm as much as possible to
13 reduce the reflection. But for output of the LNA, it is hard to get best Noise figure and the output return loss.
14 Compromise is needed between NF and return loss. Usually the return loss should be around -10dB or -
15 12dB. Also is should be very careful to assure the stability of the LNA in a large bandwidth. Vcc needs
16 capacitors to reduce the DC power ripples and give a short route to reduce the RF energy leakage. Figure
17 2-24 shows the details.
Vcc Vcc
RFout
RFin
LNAEN
LNAbypass
18
19 Figure 2-24: Two-Stage LNA Diagram
________________________________________________________________________________________________
1 2.3.2.2.4 RF Switch Reference Design
2 For TDD use, the TX and RX links work spiritedly by time duplex. The switch is used to change the RF link according
3 to the TDD duplex. In the TDD TX mode, the switch is switched to connect PA and antenna. In TDD RX mode, the
4 switch is switched to LNA and antenna.
6 The requirements of the RF switch are listed here.
7  Interface Requirements
8 The interface requirements of the switch are listed in Table 2-21.
9 Table 2-21: Interface requirements of the RF switch
Control Control the switch working mode
RF COM The port connected to the antenna
RF inputs should support 50 ohm, single ended to match the antenna.
RF Outputs The port connected to the LNA.
RF inputs should support 50 ohm, single ended to match the LNA.
RF Inputs The port connected to the PA.
RF inputs should support 50 ohm, single ended to match the PA output.
10
11  RF Specifications
12 For switch, it should have larger P1dB to not degrade the ACLR or damage the switch itself. The output
13 power should be at least 26dBm (29dBm for 500mW/port) count on the loss of antenna filter so it must
14 have low loss. Also the isolation needs to be high to protect the LNA. Higher HD2 and HD3 are needed to
15 reduce the out of band emissions.
16 Table 2-22: RF Switch Requirements
Frequency band Band 41 Band 78 Additional Information
Loss <0.8dB <0.8dB
P1dB >36dBm >36dBm
>39dBm(500mW/port)
________________________________________________________________________________________________
Isolation >30dB >30dB
3 RF Com is the input port of the switch, also can be the output of the switch. RF in is the input of the switch.
4 RF out is the output of the switch. Control 1 and control 2 are the control pin to switch the RFin to RF Com or
5 from RF Com to RF out. Figure 2-25 shows the details.
Control1
RFin
RF com
RFout
Control2
6
7 Figure 2-25: RF Switch Reference Design Diagram
8 2.3.2.2.5 Antenna Reference Design
9 The antenna is used to radiate the TX power on to the air and receive the RX power from the air. For indoor Picocell
10 scenario, the isotropic antenna is the first choice.
12 The following table shows the antenna requirement for the O-RU7-2.
13
14 Table 2-23: Antenna Requirements

Frequency band Band 41 Band 78
VSWR ≤1.8 ≤1.8
Power capacity ≥1 W ≥2 W
Gain ≥2 dBi ≥2.5 dBi
Beam width on ≥35° ≥35°

vertical direction
pattern roundness on ±3 dB ±3 dB
horizontal direction
________________________________________________________________________________________________
1
3 One possible choice of the isotropic antenna is the whip antenna. Following figure shows a design of one kind
4 of whip antenna.
6 Figure 2-26: Whip Antenna
8 The purpose of the Clocking device is to accept the network reference clock, typically 1 pps, and generate a jitter free
9 reference clock(s) for other devices in the system including the RF transceiver and digital block. The clock is typically
10 part of an IEEE 1588 implementation either controlled by an external stack or implemented in the clock device itself
11 which could be part of the baseband implementation.
13 Hardware requirements are:
14  Interface Requirements: The interface requirements of the transmit Clocking are listed in Table
15 2-24.
16 Table 2-24: Interface requirements of the clocking
Reference Clock The clock device should receive a network reference clock from the FPGA/ASIC. This
Input typically could be a 1pps, 10 MHz or other standard reference as determined by the
specific implementation. More than one input is allowed that may be selected between
when the reliability of one reference is compromised. Standard differential clocking
should be used to preserve signal integrity.
Control Control of the transceiver is by way of 3 or 4 wire SPI or IIC functioning as a slave.
Support for 1.8V control is required and tolerance of 3.3V is preferred. Typically, the
clock devices will be part of an IEEE1588v2 protocol loop controlled by way of this
control interface or other GPIO lines as required by the hardware implementation.
Clock Outputs One or more clock outputs are required to drive the digital device and transceiver clock
inputs. Each output should be independently programmable in frequency to suit the
application. The outputs should nominally be differential to preserve clocking edge and to
________________________________________________________________________________________________
maximize tolerance of high common mode signals.
RF Inputs RF inputs should support 50 ohm or 100 ohms, single ended or differential signalling to
match the transceiver output.
2  Power Dissipation: Total dissipation should be about less than 2W.
3  RF Specifications: Clocking RF requirements are given in the following table.
4 Table 2-25: Clocking RF requirements
Absolution Phase Noise, Dual Loop Typical Additional Information

Mode - LVDS OUTPUT
fOUT = 122.88 MHz Example is using an external 122.88 MHz

VCXO (Crystek CVHD-950); reference =
122.88 MHz; channel divider = 10 or 1;
PLL2 loop bandwidth (LBW) = 450 kHz.
10 Hz Offset −86 dBc/Hz
1 kHz Offset −126 dBc/Hz
1 MHz Offset −148 dBc/Hz
Absolute Phase Noise, Single

Loop Mode – LVDS OUTPUT Typical
LVDS OUTPUT
fOUT = 122.88 MHz Example is using an external 122.88 MHz

reference (SMA100A generator); reference
= 122.88 MHz; channel divider = 10; PLL2
LBW = 450 kHz.
________________________________________________________________________________________________
CLOCK OUTPUT ADDITIVE Example is using an external 122.88 MHz

TIME JITTER (BUFFER source driving VCXO inputs (distribution
MODE) section only, does not include PLL and
Typical VCO)
fOUT = 122.88 MHz 79 fS Integrated BW = 200 kHz to 5 MHz
101 fS Integrated BW = 200 kHz to 10 MHz
176 fS Integrated BW = 1 MHz to 40 MHz
3 For the clocking function, it is usually performed by a synchronization IC which may include one or more
4 PLLs. And it also can supply numbers of output port to support different frequency clocking.
VCX
O
LF2_EXT_CAP LDO_VCO
LF1 VCXO VT VCXO VCXO
PLL 1
Fine
D Q
8-bit Divider
delay OUT0
w/ Coarse
10-bit Delay
REFA Divider SYNC
Fine
D Q
8-bit Divider delay OUT1
Switch- w/ Coarse
REF_SEL over Lock Loop Delay
control filter PLL 2 SYNC
Det
10-bit
REFB
Divider 5-bit
...
...
...
P Divider Charge Loop Divider
Charge PFD VCO
F Pump filter ÷3, ÷4, ÷5
Pump x2 OUT2 to OUT 11
10-bit D
Divider
8-bit
Divider
SYNC
Fine
D Q
8-bit Divider delay OUT12
w/ Coarse
Delay
SYNC
Fine
D Q
SYSREF 8-bit Divider delay OUT13
w/ Coarse
Delay
SYNC
D Q D Q
Lock
SDIO Detect
SDO Control
SCLK Interface SYS_REF
CS (SPI & I2C) Generation
RESET Trigger
D Q
SPI_SYS_REF
Request
Serial Port
Address
Monitor
Detect/
Status
Status_0,1
Lock
/SP0,1
SYSREF
REQUEST (CMOS)
6 Figure 2-27: PLL Reference Design Diagram
7 REFA and REFB are differential reference clock inputs from the source to be cleaned up and used as the
8 system reference. REF_SEL is the control pin used to select between REFA and REFB signals. LF1 is PLL1
9 external loop filter. VCXO_VT is the VCXO control voltage. This pin is connected to the voltage control pin
10 of the external VCXO. VCXO_IN are differential signals from the external VCXO. These typically can be
________________________________________________________________________________________________
1 configured for single ended operation as well. LF2_CAP is the external loop filter capacitor for loop 2. This
2 cap is connected between this pin and LDO_VCO pin. LDO_VCO is the onchip LDO regular decoupling for
3 the VCO. RESET(bar) is an active low pin to reset the internal logic to their default states. CS(bar) is an
4 active low chip select for serial control. SCLK/SCL is a serial control port clock for both SPI and I2C.
5 SDIO/SDA is a bidirectional serial data pin for both SPI and I2C. SDO is the serial data out pin for 4-wire
6 mode. OUT0 through OUT13 are differential programmable output clock signals. These are the primary
7 outputs of this device and provide high performance clock signals to the transceiver, baseband device and
8 other key elements. This device is also responsible for providing SYSREF to various devices in the system if
9 required. It may also use an external SYSREF as a source that may be retimed for local timing if necessary.
10 STATUS0/SP0 is a lock detect and other status signal. STATIS1/SP1 is a lock detect and other status signal.
11 SYSREF_IN is an external SYSREF input clock is a differential input representing the JESD204
12 synchronization from the external source.
15 The following table shows the external ports or slots provided by O-RU7-2.

Port Name Feature Description
Fronthaul interface One 10Gbps SFP+ transceiver interface
Or one RJ45 Ethernet interface
Debug interface RJ45 for debug usage
Power interface Two-pin male plug for power cable
17
19  SFP+ case and connector: The SFP+ case and connector are standardized component on the market;
20 following figure describe the form factor of one SFP case which is integrated with connector.
Figure 2-28: SFP+ case and connector
21
________________________________________________________________________________________________
1  RJ45 Ethernet interface: The RJ45 Ethernet interface is standardized component on the market; following
2 figure describe the form factor of one RJ45 interface.
4 Figure 2-29: RJ45 interface
5 2.3.5 Mechanical
6 The shell of O-RU7-2 is showing in the following figure. The O-RU7-2 should be quiet, so it depends on the natural heat
7 dissipation method. Usually the bottom of the shell is built by metal. All hot component should make its surfaces
8 contact to metal shell through thermal pad.
10 Figure 2-30: O-RU7-2 Shell Mechanical Diagram
11
12 .
________________________________________________________________________________________________
1 2.3.6 Power Unit
2 For Picocell, for the power solution of the O-RU7-2 can be over Ethernet cable (cat5E, cat6A) by POE (POE+, POE++)
3 or directly power cable with fibre. And for the board power solution, LDO and DCDC can be used.
5 For PA unit, it should have larger enough gain to reduce extra driver amplifier for cost and PCB space. The
6 output power should be at least 27dBm count on the loss of switch and antenna filter. The ACLR should larger
7 than 47dBc according to the related 3GPP test mode. To reduce the power consumption, DPD is needed. And
8 the P1 dB requirement is closely related to the DPD algorithm.
9 Table 2-27: power unite requirement for 2T2R and 4T4R O-RU7-2
Module Power consumption
2T2R 4T4R Unit
FPGA 9 11 W
Transceiver 5.74 11.48 W
PLL 1.78 1.78 W
PA 5 10 W 0.75 TDD ratio
LAN 0.15 0.3 W 0.25 TDD ratio
Ethernet PHY 1 1 W
DDR 0.9 0.9 W
Flash 0.1 0.1 W
others 1.65 1.65 W
component total power consumption 25.3 38 W
O-RU7-2 power consumption 29.7 45 W on board power efficiency 0.85
10
11 Table 2-28: Power unite function
Function Priority
Enable/Disable Mandatory
Power good Optional
Input voltage Mandatory 48V
Output voltage Mandatory 0.85V 1.2V 1.3V 1.5V 1.8V

2.5V 3.3V 5V 12V etc.
12
13
________________________________________________________________________________________________
2 The block diagram of POE reference design is shown in Figure 2-31. Data Pair and Spare Pair are the POE
3 connections on the data transformers used to source the power over Ethernet. V AUX is a local backup power
4 source if desired. Isolated Output is the isolated raw output from the PoE sub-circuit.
5
VAUX (9V to 60 V)
CPORT
DATA ~ + VPORT
CPD
PAIR 0.1uF 3 .3k
~ - VIN
47 nF
Isolated
SPARE ~ + Power
Isolated
Output
PAIR Supply
VPORT HSGATE HSSRC
~ - Run
AUX PWRGD
Power over Ethernet

Controller
GND
7 Figure 2-31: PoE Reference Design Diagram
8 2.3.7 Thermal
9 O-RU7-2 will use passive cooling.
11 The O-RU7-2 hardware system is RoHS Compliant. The power supply unit is EMC FCC/CISPR Class B compliant.
12 Table 2-29 lists the environmental related features and parameters.
13 Table 2-29: Environmental Features

Operating Temperature -5°C to +55°C
Non-operating Temperature -40°C to 70°C
Operating Relative Humidity 8% to 90% (non-condensing)
Non-operating Relative Humidity 5% to 95% (non-condensing)
14
________________________________________________________________________________________________
1 2.4 FHGW7-2 Hardware Reference Design

2 The FHGW7-2 is used to bridge the connation between O-DU7-2 and O-RU7-2. It needs to power the O-RU7-2
3 and reduces the front haul bandwidth.
4 2.4.1 FHGW7-2 High-Level Functional Block Diagram
5 Figure 2-29 shows the FHGW7-2 block diagram for this reference design. Following sections below describe the
6 functionality, interface and performance for each respective block of the Digital Processing Unit. As device integration
7 is an ongoing activity, chip boundaries may be fluid and some functionality may move from one block to another or
8 entire functionalities may be absorbed into other blocks. The sections below describe the functional blocks independent
9 of which physical device they may reside in.
10
Uplink Cascade
25G 25G
RJ45
SFP+ SFP+
220V
AC
RS232 DDR
Power FPGA+ARM
Flash
CLK
Serdes Serdes
48V FAN
Power Power 10G 10G

11 interface1 … interface8 SFP+.1 … SFP+.8
12 Figure 2-32: FHGW7-2 General Block Diagram
13
________________________________________________________________________________________________
1 2.4.2 FHGW7-2 Hardware Components

3 The FHGW7-2 need a lot of high speed interface. And for the shared cell application, the uplink need combining
4 function.
5 i. FPGA Solution Design 1

6 In this section, the requirement and reference design based on FPGA are described.
8 The requirements are as follows:
9  Interface requirement are shown in Table 2-30
10 Table 2-30: Interface requirements of the FPGA
At least 8 lanes of bi-direction10Gb Serdes

Serdes lane
11
12 b. FPGA Design
13 This unit handles multiple high speed interfaces and the digital signal processing. The main chipset is based on
14 FPGA with ARM multi-core processor while FPGA is responsible for high speed data processing and ARM cores
15 are mainly for configuration and management.
16 The FPGA function is shown below:
17 For the uplink processing, the eCPRI interface module is used to receiver eCPRI link form O-RU7-2 and generate
18 the reference frequency and time slot for time and frequency synchronization. Then the eCPRI de-frame module
19 get the uplink IQ bit stream of the time domain the carrier from O-RU7-2. If the uplink IQ stream is compressed,
20 then it needs the de-compression module to translate them into original bit width.
21 After that all the O-RU7-2 uplink IQ streams are combined together and the precondition for the combine function is
22 that each stream from different O-RU7-2 are aligned in time domain.
23 Then the time domain IQ date go to the Low PHY function module to change to frequency domain IQ samples by
24 FFT. Other function is not detailed at here.
25 If the FHGW7-2 can support two separate cells then the two cell uplink signal should be aggregated or interleaved
26 together. Then capture the IQ streams in the eCPRI frame and transmitted by eCPRI interface to the O-DU7-2.
27 For the downlink processing, the procedure is much the same with uplink but with an inverse sequence. The
28 difference is that the downlink signal is duplicated with 8 copies and sends to different O-RU7-2.
29 There is also a eCPRI OAM module; actually this module will work with the processor (Arm) to accommodate the
30 OAM of different O-RU7-2 and the FHGW7-2 itself.
________________________________________________________________________________________________
FHGW 7-2-7-2
De- eCPRI eCPRI

Buffer
compress de-frame interface
De- eCPRI eCPRI

Buffer
Other cell I/Q compress de-frame interface
eCPRI eCPRI Compress
aggregati combiniti
interface frame ion
on on
De- eCPRI eCPRI

Buffer
Other cell
Ethernet
OAM
eCPRI eCPRI
Buffer
frame interface
eCPRI eCPRI
Buffer
Other cell frame interface
eCPRI eCPRI de-
aggregati I/Q mux
interface frame
on
eCPRI eCPRI
Buffer
frame interface
1
2 Figure 2-33: FHGW7-2 Digital Processing Block Diagram
3 The resource needed for the FPGA is listed below:
4 Table 2-31: FPGA Resource usage for FHGW7-2
Device FF LUT URAM BRAM DSP
IQ MUX 1000 1000 0 0 0

Cascade 2000 2000 0 0 0
IQ combine 2000 2000 0 32 0
eCPRI deframe*9 63000 63000 0 180 0
eCPRI frame*9 63000 63000 0 180 0
Fronthaul(eCPRI)x
100000 80000 0 10 0
10
compress*1 3000 3000 0 24 32
de_compress*8 24000 24000 0 192 208
ethernet_cm 3000 3000 0 15 0
Other 20000 15000 0 200 0
5
________________________________________________________________________________________________
2 In this section we describe the internal and external timing and synchronization that are managed by this
3 entity.
5  CLK requirement
6 The FHGW7-2 may support some kinds of synchronization method:
7 1) IEEE 1588/SyncE
8 2) Support GPS/GLONASS/GALILEO/BEIDOU
9 So the PLL must support 1pps or eCPRI CDR as the reference frequency.
10 Table 2-32: Requirements of the PLL device
Device Description
1PPS Supported
Synchronizer at least 1
number
Output At least 5
channel
VCO Supported
integrated
11
13 This unit is to recover clock from external source and generate the synchronized clock to other devices. Upon
14 scenarios, there will be external sync source via eCPRI.
Reference clock from FPGA 390.625MHz To FPGA 25G Serdes
390.625MHz 156.25MHz To FPGA 10 Serdes0
156.25MHz To FPGA 10G Serdes1

CLK 125MHz
For FPGA sys
250MHz
For DDR function
15
16
17 Figure 2-34: CLK reference design for FHGW7-2
18 For general FPGA device, each bank may have 4 Serdes channel. It is better to have separated clk to each bank.
19 So two clk of 156.25 MHz are needed for the FHGW 7-2, which is used for the 8 10G serdes interfaces with O-
20 RU7-2. One 390.625MHz is used for 2 25G serdes interface with O-DU7-2 or cascaded FHGW7-2. One 125MHz
________________________________________________________________________________________________
1 is used for FPGA system. One 250MHz clk for DDR device function. One 390.625MHz is used for 25G
2 eCPRI interface between O-DU7-2 and FHGW7-2. The input of the CLK module comes from FPGA CDR
3 function which get reference clk from the eCPRI line rate. Usually, one PLL device which is integrated with
4 VCO is needed.
6 List and provide description of all external interfaces.
8 The following table shows the external ports or slots provided by FHGW7-2.

Fronthaul interface Eight 10Gbps SFP+ transceiver interfaces
Two 25Gbps SFP+ transceiver interfaces
Power interface PLUG AC FEMALE for power cable
10
12  SFP+ case and connector
13 The SFP+ case and connector are standardized component on the market; following figure describes the form
14 factor of one SFP case which is integrated with connector.
15
16
17 Figure 2-35: SFP+ case and connector
18  RJ45 Ethernet interface
19 The RJ45 Ethernet interface is standardized component on the market; following figure describes the form
20 factor of one RJ45 interface.
21
22
23
________________________________________________________________________________________________
3  Power interface
4 The 220V AC power connector is standardized component on the market; following figure describes the form
5 factor of one 220V AC power connector.
6
8 Figure 2-37: AC power interface
9 2.4.5 Mechanical
10 The 1U rack mount chassis can contains the layout of the power unit and processing unit. The shell of FHGW7-2 is
11 showing in the following figure. The power consumption of FHGW 7-2 is huge, so it may need a fan to accelerate the
12 heat dissipation.
13 Figure 2-38: Shell Mechanical Diagram
________________________________________________________________________________________________
1 2.4.6 Power
2 At minimum, fully describe the power consumptions for this white box. Include all AC/DC input or outputs
3 and their ratings. Not mandatory but if you like you can add summary of all component's power requirement
4 and overall white box.
6  Power requirement: The power solution is divided into two parts.
7 1. Input power module: This power module must support AC to DC conversion. Usually
8 it converts 220V AC to 48V DC.
9 2. Output power module: It will supply power to the O-RU7-2 connected to the FHGW7-2
10 and also the device on the FHGW7-2 itself.
11
12 Table 2-34: Requirements of the power unit
Item Description
Input voltage AC:100V~264V
Output DC: 48V

voltage
Output At least 600W

power
14 Describe hardware reference design for this power unit.
15 This unit has two main functions which are internal power supply and external/remote power supply. The input
16 power is normally AC (100V to 250V) but DC input could be optional. For remote power supply, it will support
17 -48V DC via either standalone cable or cat-6A cable.
18 Usually a separated AC-DC power supply is used for the 220V to 48V conversion. It is very common power
19 supply on the market.
20 It should have fan to cool itself and handle for easy plug in and out.
21 Then the output power is divided into two portions. One for O-RU7-2 power supply, the other is for the device
22 on the FHGW7-2 board.
23 For the on-board power solution, 48V to 12V converter is needed as standard 1/8 brick module. Then the power
24 voltage is further changer to lower level such as 5V, 3.3V, 1.1V, 1.0V and so on by DC/DC or LDO devices.
25 2.4.7 Thermal
26 Active cooling.
28 The FHGW will fulfil the requirement in 4.6.3 of [6].
________________________________________________________________________________________________
1 2.5 FHGW7-2→8 Hardware Reference Design

2 The FHGW7-2→8 is used to bridge the connation between O-DU7-2 and O-RU8. It needs to power the O-RU8 and reduces
3 the front haul bandwidth.
4 2.5.1 FHGW7-2→8 High-Level Functional Block Diagram
5 Figure 2-39 depicts the FHGW7-2→8 block diagram for this reference design. Following sections will describe the
6 functionality, interface and performance for each respective block within the figure. Since device integration is an
7 ongoing activity, chip boundaries may be fluid and some functionality may move from one block to another or entire
8 functionalities may be absorbed into other blocks. The descriptions below describe the functional blocks independent
9 of which physical device they may reside in.
10
Uplink Cascade
25G 25G
RJ45
SFP+ SFP+
220V
AC
RS232 DDR
Power FPGA+Processor
Flash
CLK
Serdes Serdes
48V FAN
Power Power 10G 10G

11 interface1 … interface8 SFP+.1 … SFP+.8
12 Figure 2-39: FHGW7-2→8 General Block Diagram
13
________________________________________________________________________________________________
1 2.5.2 FHGW7-2→8 Hardware Components

3 The FHGW7-2→8 need a lot of high speed interface. It would need the function of transforming the FH protocol with
4 split Option 8 to one of with split Option 7-2. This requires availability of the Low PHY function as required by option
5 7-2. For the shared cell application, the uplink will also need a combining function for aggregation and dis aggregation
6 of data.
7 i. FPGA Design Solution 1

8 In this section, the requirement and reference design based on FPGA are described.
10  Interface requirement: Interface requirements for this FPGA design solution are provided in the
11 following table.
12 Table 2-35: Interface Requirements of the FPGA

Serdes lane
13
14 b. FPGA Design
15 This unit handles multiple high speed interfaces and the digital signal processing. The main chipset is based
16 on FPGA with multi-core processor while FPGA is responsible for high speed data processing and processor
17 cores are mainly for configuration and management.
18 The FPGA function is shown below:
19 For the uplink processing, the CPRI interface module is used to receive CPRI link from O-RU8 for
20 generation of the reference frequency and time slot for time and frequency synchronization. Then the CPRI
21 de-frame module gets the uplink IQ bit stream of the time domain the carrier from O-RU8. If the uplink IQ
22 stream is compressed, then it needs the de-compression module to translate them into original bit width. All
23 the O-RU8 uplink IQ streams are combined and the precondition for the combine function is that each stream
24 from different O-RU8 are aligned in time domain. Then the time domain IQ data go to the Low PHY
25 function module to change to frequency domain IQ samples by performing FFT function.
26 If the FHGW7-2-→8 can support two separate cells then the two cell uplink signal should be aggregated or
27 interleaved together. Then FHGW7-2-→8 should capture the IQ streams in the eCPRI frame and transmit it via
28 eCPRI interface to the O-DU7-2. For the downlink processing, the procedure is very much the same as uplink
29 but in reverse order. The difference is that the downlink signal is duplicated with 8 copies and transmits that
30 to different O-RU8. There is also one eCPRI/CPRI OAM module. Actually this module will work with the
31 processor to accommodate the OAM of different O-RU8 and the FHGW7-2-→8 itself.
________________________________________________________________________________________________
FHGW 7-2-8
De- CPRI CPRI

Buffer
De- CPRI CPRI

Buffer
Other cell I/Q compress de-frame interface
eCPRI eCPRI Compress
aggregati Low - PHY combiniti
interface frame ion
on on
De- CPRI CPRI

Buffer
Other cell
Ethernet
OAM
CPRI CPRI
Buffer
frame interface
CPRI CPRI
Buffer
Other cell frame interface
eCPRI eCPRI de-
Low - PHY aggregati I/Q mux
interface frame
on
CPRI CPRI
Buffer
frame interface
1
2 Figure 2-40: FHGW7-2→8 Digital Processing Block Diagram
3 The FPGA resource needed for the FPGA is listed below:
4 Table 2-36: FPGA Resource Usage for FHGW7-2-→8
Device FF LUT URAM BRAM DSP
IQ MUX 1000 1000 0 0 0

Cascade 2000 2000 0 0 0
IQ combine 2000 2000 0 32 0
eCPRI deframe*2 14000 14000 0 40 0
eCPRI frame*2 14000 14000 0 40 0
CPRI deframe*8 40000 40000 0 0 0
CPRI frame*8 40000 40000 0 0 0
Fronthaul(eCPRI)x2 20000 16000 0 2 0
Fronthaul(CPRI)x8 37890 24804 0 8 0
compress*1 3000 3000 0 24 32
de_compress*8 24000 24000 0 192 208
Ethernet CM 3000 3000 0 15 0
iFFT & CP+ 7763 5323 0 27 23
FFT & CP- 7763 5323 0 27 23
PRACH front end 4000 3000 0 32 50
Other 20000 15000 0 200 0
5
________________________________________________________________________________________________
2 This section describes the synchronization and timing mechanism that is used in the FHGW7-2→8.
4  CLK requirement
5 The FHGW7-2→8 may support some kinds of synchronization method:
6 1) IEEE 1588/SyncE
7 2) Support GPS/GLONASS/GALILEO/BEIDOU
8 So the PLL must support 1pps or eCPRI CDR as the reference frequency.
9 Table 2-37: Requirements of the PLL device
1PPS Supported
Synchronizer at least 1
number
Output At least 6
channel
VCO Supported
integrated
10
12 This unit is to recover clock from external source and generate the synchronized clock to other devices. Upon
13 scenarios, there will be external sync source via eCPRI.
Reference clock from FPGA 390.625MHz To FPGA 25G Serdes
390.625MHz 122.88MHz To FPGA 10 Serdes0
122.88MHz To FPGA 10G Serdes1

CLK 125MHz
For FPGA sys
250MHz
For DDR function
122.88MHz For Low PHY function
14
15 Figure 2-41: CLK reference design for FHGW7-2→8
16 For general FPGA device, each bank may have four Serdes channels. It is better to have separated CLK signal to
17 each bank. Three CLK signals of 122.88MHz are needed for the FHGW 7-2→8. One CLK signal of 125MHz is
18 used for FPGA system, while one CLK signal of 250MHz is used for DDR device function. One CLK signal of
19 390.625MHz is used for 25G eCPRI interface between O-DU7-2 and FHGW7-2→8, and one CLK signal of
20 122.8MHz is used for low PHY function. The input of the CLK module comes from FPGA CDR function which
________________________________________________________________________________________________
1 can get reference CLK from the sync-plane of eCPRI. Usually, one PLL device integrated with VCO and two
2 separated synthesizers is needed.
4 This section describes the external interface ports that are needed in the FHGW7-2→8.
6 The following table shows the external ports or slots provided by FHGW7-2→8.

Fronthaul interface Eight 10Gbps SFP+ transceiver interfaces
Two 25Gbps SFP+ transceiver interfaces
Power interface PLUG AC FEMALE for power cable
8
10  SFP+ case and connector
11 The SFP+ case and connector are standardized component on the market; following figure describes the
12 form factor of one SFP case which is integrated with connector.
13
14 Figure 2-42: SFP+ case and connector
15  RJ45 Ethernet interface
16 The RJ45 Ethernet interface is standardized component on the market; following figure describes the form
17 factor of one RJ45 interface.
________________________________________________________________________________________________
3  Power interface
4 The 220V AC power connector is standardized component on the market; following figure describes the
5 form factor of one 220V AC power connector.
6
7 Figure 2-44: AC power interface
________________________________________________________________________________________________
1 2.5.5 Mechanical
2 The 1U rack mount chassis can contain the layout of the power unit and processing unit. The shell of FHGW7-2→8 is
3 showing in the following figure. The power consumption of FHGW 7-2→8 is huge, so it may need a fan to accelerate the
4 heat dissipation.
6 Figure 2-45: Shell Mechanical Diagram
7 2.5.6 Power
8 At minimum, fully describe the power consumptions for this white box. Include all AC/DC input or outputs and their
9 ratings. Not mandatory but if you like you can add summary of all component's power requirement and overall white
10 box.
12  Power requirement: The power solution is divided into two parts.
13 1. Input power module

14 This power module must support AC to DC conversion. Usually it converts 220V AC to 48V DC.
15 2. Output power module

16 It will supply power to the O-RU8 connected to the FHGW7-28 and also the device on the FHGW7-2→8
17 itself.
18
19
20
________________________________________________________________________________________________
1 Table 2-39: Power Unit Requirements
Input voltage AC:100V~264V
Output DC: 48V

voltage
Output power At least 600W
4 This unit has two main functions which are internal power supply and external/remote power supply. The input
5 power is normally AC (100V to 250V) but DC input could be optional. For remote power supply, it will support
6 -48V DC via either standalone cable or cat-6A cable. Usually a separated AC-DC power supply is used for the
7 220V to 48V conversion. It is very common power supply on the market. It should have fan to cool itself and
8 handle for easy plug in and out. Then the output power is divided into two portions. One for O-RU8 power
9 supply, the other is for the device on the FHGW 7-2→8 board. For the on board power solution, 48V to 12V
10 converter is needed as standard 1/8 brick module. Then the power voltage is further changer to lower level such
11 as 5V, 3.3V, 1.1V, 1.0V and so on by DC/DC or LDO devices.
12 2.5.7 Thermal
13 Active cooling shall be used for this fronthaul gateway.
15 This FHGW7-2→8 will fulfil the requirements as described in 4.6.3 of [6].

16
________________________________________________________________________________________________
1 Annex 1: Parts Reference List

2 According to WG7 scope and charter, component selection for example implementation of white box hardware is
3 allowed for WG7 but would not be mandatory in any Specification.
4 Recommended O-DU7-2 parts reference is given in table below:
No. Part Number Descriptions
1 Intel® Xeon® Processor D-2183IT Intel® Xeon® Skylake D D-2100 SoC processor
2 Intel® I350 Intel® 1GbE x4 Ethernet controller
3 Intel® X557-AT2 Intel® 10GbE x2 Ethernet controller
4 Intel® I210 Intel® 1GbE Ethernet controller
5 ASPEED® AST-2500 ASPEED® BMC controller
6 UniIC® SCQ08GU03H1F1C-26V UniIC® DDR4 8GB
7 Powerleader® MTFDDAK480TDC- Powerleader® SSD 480GB

1AT1ZABYY
8 Accelink® RTXM228-551 Accelink® 10Gbps Optical module
________________________________________________________________________________________________
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2 BY DOWNLOADING, USING OR OTHERWISE ACCESSING ANY O-RAN SPECIFICATION, ADOPTER
3 AGREES TO THE TERMS OF THIS AGREEMENT.
4 This O-RAN Adopter License Agreement (the “Agreement”) is made by and between the O-RAN Alliance and the
5 entity that downloads, uses or otherwise accesses any O-RAN Specification, including its Affiliates (the “Adopter”).
6 This is a license agreement for entities who wish to adopt any O-RAN Specification.
7 Section 1: DEFINITIONS
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12 software or combinations thereof) that fully conforms to a Final Specification.
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32 allowing the licensor to suspend the license against a licensee who brings a patent infringement suit against the
33 licensing Member, Contributor, Academic Contributor, Adopter, or any of their Affiliates.
________________________________________________________________________________________________
1 Section 2: COPYRIGHT LICENSE

2 2.1 Subject to the terms and conditions of this Agreement, O-RAN Alliance hereby grants to Adopter a nonexclusive,
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30 product in which a Compliant Implementation is incorporated that is not itself part of the Compliant Implementation; or
31 (b) to any Members, Contributors, Academic Contributors, Adopters and their Affiliates that is not making a reciprocal
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33 the distribution by the Members’, Contributors’, Academic Contributors’, Adopters’ and their Affiliates’ distributors
34 and the use by the Members’, Contributors’, Academic Contributors’, Adopters’ and their Affiliates’ customers of such
35 licensed Compliant Implementations.
________________________________________________________________________________________________
1 Section 4: TERM AND TERMINATION

2 4.1 This Agreement shall remain in force, unless early terminated according to this Section 4.
3 4.2 O-RAN Alliance on behalf of its Members, Contributors and Academic Contributors may terminate this Agreement
4 if Adopter materially breaches this Agreement and does not cure or is not capable of curing such breach within thirty
5 (30) days after being given notice specifying the breach.
6 4.3 Sections 1, 3, 5 - 11 of this Agreement shall survive any termination of this Agreement. Under surviving Section 3,
7 after termination of this Agreement, Adopter will continue to grant licenses (a) to entities who become Adopters after
8 the date of termination; and (b) for future versions of ORAN Specifications that are backwards compatible with the
9 version that was current as of the date of termination.
10 Section 5: CONFIDENTIALITY
11 Adopter will use the same care and discretion to avoid disclosure, publication, and dissemination of O-RAN
12 Specifications to third parties, as Adopter employs with its own confidential information, but no less than reasonable
13 care. Any disclosure by Adopter to its Affiliates, contractors and consultants should be subject to an obligation of
14 confidentiality at least as restrictive as those contained in this Section. The foregoing obligation shall not apply to any
15 information which is: (1) rightfully known by Adopter without any limitation on use or disclosure prior to disclosure; (2)
16 publicly available through no fault of Adopter; (3) rightfully received without a duty of confidentiality; (4) disclosed by
17 O-RAN Alliance or a Member, Contributor or Academic Contributor to a third party without a duty of confidentiality
18 on such third party; (5) independently developed by Adopter; (6) disclosed pursuant to the order of a court or other
19 authorized governmental body, or as required by law, provided that Adopter provides reasonable prior written notice to
20 O-RAN Alliance, and cooperates with O-RAN Alliance and/or the applicable Member, Contributor or Academic
21 Contributor to have the opportunity to oppose any such order; or (7) disclosed by Adopter with O-RAN Alliance’s prior
22 written approval.
23 Section 6: INDEMNIFICATION
24 Adopter shall indemnify, defend, and hold harmless the O-RAN Alliance, its Members, Contributors or Academic
25 Contributors, and their employees, and agents and their respective successors, heirs and assigns (the “Indemnitees”),
26 against any liability, damage, loss, or expense (including reasonable attorneys’ fees and expenses) incurred by or
27 imposed upon any of the Indemnitees in connection with any claims, suits, investigations, actions, demands or
28 judgments arising out of Adopter’s use of the licensed O-RAN Specifications or Adopter’s commercialization of
29 products that comply with O-RAN Specifications.
30 Section 7: LIMITATIONS ON LIABILITY; NO WARRANTY

31 EXCEPT FOR BREACH OF CONFIDENTIALITY, ADOPTER’S BREACH OF SECTION 3, AND ADOPTER’S
32 INDEMNIFICATION OBLIGATIONS, IN NO EVENT SHALL ANY PARTY BE LIABLE TO ANY OTHER
33 PARTY OR THIRD PARTY FOR ANY INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL
34 DAMAGES RESULTING FROM ITS PERFORMANCE OR NON-PERFORMANCE UNDER THIS AGREEMENT,
________________________________________________________________________________________________
1 IN EACH CASE WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, AND WHETHER OR
2 NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. O-RAN
3 SPECIFICATIONS ARE PROVIDED “AS IS” WITH NO WARRANTIES OR CONDITIONS WHATSOEVER,
4 WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. THE O-RAN ALLIANCE AND THE
5 MEMBERS, CONTRIBUTORS OR ACADEMIC CONTRIBUTORS EXPRESSLY DISCLAIM ANY WARRANTY
6 OR CONDITION OF MERCHANTABILITY, SECURITY, SATISFACTORY QUALITY, NONINFRINGEMENT,
7 FITNESS FOR ANY PARTICULAR PURPOSE, ERROR-FREE OPERATION, OR ANY WARRANTY OR
8 CONDITION FOR O-RAN SPECIFICATIONS.
9 Section 8: ASSIGNMENT
10 Adopter may not assign the Agreement or any of its rights or obligations under this Agreement or make any grants or
11 other sublicenses to this Agreement, except as expressly authorized hereunder, without having first received the prior,
12 written consent of the O-RAN Alliance, which consent may be withheld in O-RAN Alliance’s sole discretion. O-RAN
13 Alliance may freely assign this Agreement.
14 Section 9: THIRD-PARTY BENEFICIARY RIGHTS

15 Adopter acknowledges and agrees that Members, Contributors and Academic Contributors (including future Members,
16 Contributors and Academic Contributors) are entitled to rights as a third-party beneficiary under this Agreement,
17 including as licensees under Section 3.
18 Section 10: BINDING ON AFFILIATES

19 Execution of this Agreement by Adopter in its capacity as a legal entity or association constitutes that legal entity’s or
20 association’s agreement that its Affiliates are likewise bound to the obligations that are applicable to Adopter hereunder
21 and are also entitled to the benefits of the rights of Adopter hereunder.
22 Section 11: GENERAL

23 This Agreement is governed by the laws of Germany without regard to its conflict or choice of law provisions.
24 This Agreement constitutes the entire agreement between the parties as to its express subject matter and expressly
25 supersedes and replaces any prior or contemporaneous agreements between the parties, whether written or oral, relating
26 to the subject matter of this Agreement.
27 Adopter, on behalf of itself and its Affiliates, agrees to comply at all times with all applicable laws, rules and
28 regulations with respect to its and its Affiliates’ performance under this Agreement, including without limitation, export
29 control and antitrust laws. Without limiting the generality of the foregoing, Adopter acknowledges that this Agreement
30 prohibits any communication that would violate the antitrust laws.
31 By execution hereof, no form of any partnership, joint venture or other special relationship is created between Adopter,
32 or O-RAN Alliance or its Members, Contributors or Academic Contributors. Except as expressly set forth in this
________________________________________________________________________________________________
1 Agreement, no party is authorized to make any commitment on behalf of Adopter, or O-RAN Alliance or its Members,
2 Contributors or Academic Contributors.
3 In the event that any provision of this Agreement conflicts with governing law or if any provision is held to be null,
4 void or otherwise ineffective or invalid by a court of competent jurisdiction, (i) such provisions will be deemed stricken
5 from the contract, and (ii) the remaining terms, provisions, covenants and restrictions of this Agreement will remain in
6 full force and effect.
________________________________________________________________________________________________

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ORAN.WG7.IPC-HRD-Opt7-2.0-v01.

Prepared by the O-RAN Alliance. Copyright © 2020 by the O-RAN Alliance.

© 2020 O-RAN Alliance All Rights Reserved

06/12/2020 v01.00 WG7 First Published Version

9 Chapter 2 Hardware Reference Design 1 ..................................................................................................... 13

1 2.3.7 Thermal ...................................................................................................................................................... 53

23 Annex 1: Parts Reference List .......................................................................................................................... 69

1 Table 2-5: Accelerator Hardware Component List ........................................................................................................... 19

1 Figure 2-4: Accelerator Design 1 with optional NIC Device ........................................................................................... 18

1 Chapter 1 Introductory Material

1 1.3 Definitions and Abbreviations

6 Carrier Frequency: Center frequency of the cell.

1 CPU Central Processing Unit

1 LVDS Low-Voltage Differential Signaling

1 SSD Solid State Drive

1 Chapter 2 Hardware Reference Design 1

4 2.1 O-CU Hardware Reference Design

16 2.2 O-DU7-2 Hardware Reference Design

28 2.2.1 O-DU7-2 High-Level Functional Block Diagram

Accelerator DDR RAM

4 Figure 2-1: O-DU7-2 Functional Block Diagram.

5 2.2.2 O-DU7-2 Hardware Design Description

8 Figure 2-2: O-DU7-2 Hardware Block Diagram

7 2.2.3 O-DU7-2 Hardware Components

11 2.2.3.1 Digital Processing Unit

13 a. Digital Processing Unit Requirement

15 Table 2-1: The Processor Feature List

17 Interfaces: The interface specification on the main board are as follows:

21 Table 2-2: The Memory Channel Feature List

13 2.2.3.2 Hardware Accelerator

20 2.2.3.2.1 Accelerator Design Solution 1

24  Virtualization: Multi-channel DMA, Virtual machine integration, load balancing functions

27  Bump-in-wire Fronthaul: compression / decompression for latency and bandwidth reduction

31 Table 2-3: Accelerator Hardware Feature List

PCIe (Interface with digital processing

Form factor FHHL

FPGA Logic Elements: 1437K

M20K Memory: 139Mb

Quad A53 Hard Processor Sub-system

100Gb xHAUL for FH, BH & MH traffic shaping. Optional FPGA

DDR Main 8+8+1GB DDR4

Flash (FPGA images) >=1 Gbit

BMC Telemetry, Security, remote upgrade

Clocking For O-RAN C1, C2, C3 & C4

Fronthaul eCPRI, RoE IEEE1914.3, O-RAN WG4

GPS SMA for 1 PPS & 10MHz (in/out)

Operating Temperature (ambient) NEBS Compliant

Power <75W (without optional NIC device)

Clock Accuracy Low-Jitter, configurable clock ranging from 10MHz to 750MHz.

3 Table 2-4: Accelerator Firmware Feature List

Remote system upgrade Securely upgradable FPGA flash image

Queuing 64 Queues supported equally split between UL & DL.

NR LDPC Decoding with sub-block de-interleaving function of

5G Throughput: DL 14.8Gbps, UL 3.2Gbps

Load balancer distributes the pending encoder/decoder requests to

1PPS & 10MHz

6 Figure 2-3: Accelerator Design 1 without optional NIC Device

PCIe Gen 4x8

9 Figure 2-4: Accelerator Design 1 with optional NIC Device