Module 5 VLSI Design (18EC72)

Module 5
Semiconductor Memories
Introduction
Semiconductor memory arrays capable of storing large quantities of digital information are essential
to all digital systems.
• The area efficiency of the memory array, i.e., the number of stored data bits per unit area, is one
of the key design criteria that determine the overall storage capacity and, hence, the memory cost
per bit.
• Another important issue is the memory access time, i.e., the time required to store and/or retrieve
a particular data bit in the memory array, which determines the memory speed.
• Finally, the static and dynamic power consumption of the memory array is a significant factor to
be considered in the design.
Memory circuits are generally classified as:
• Read-Only Memory (ROM) that allow only the retrieval of previously stored data and do not
permit modifications of the stored information contents during normal operation. ROMs are non-
volatile memories, i.e., the data storage function is not lost even when the power supply voltage is
off. Depending on the type of data storage (data write) method, ROMs are classified as mask-
programmed ROMs, Programmable ROMs (PROM), Erasable PROMs (EPROM), and
Electrically Erasable PROMs (EEPROM).

Fig 5.1. Overview of semiconductor memory types

• Read-write (R/W) memory circuits, permit the modification (writing) of data bits stored in the
memory array, as well as their retrieval (reading) on demand. This requires that the data storage
function be volatile, i.e., the stored data are lost when the power supply voltage is turned off. The
read-write memory circuit is commonly called Random Access Memory (RAM), as any cell in
the R/W memory array can be accessed with nearly equal access time. Based on the operation

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type of individual data storage cells, RAMs are classified into two main categories: Static RAMs
(SRAM) and Dynamic RAMs (DRAM).
Fig 5.1 shows an overview of the different memory types and their classifications.

A typical memory array organization is shown in Fig. 5.2. The data storage structure, or core, consists
of individual memory cells arranged in an array of horizontal rows and vertical columns. Each cell is
capable of storing one bit of binary information. Also, each memory cell shares a common connection
with the other cells in the same row, and another common connection with the other cells in the same
column. In this structure, there are 2N rows, also called word lines, and 2M columns, also called bit
lines. Thus, the total number of memory cells in this array is 2N x 2M.

Fig 5.2. Typical random-access memory array organization.

To access a particular memory cell, i.e., a particular data bit in this array, the corresponding
bit line and the corresponding word line must be activated (selected). The row and column
selection operations are accomplished by row and column decoders, respectively. The row
decoder circuit selects one out of 2N word lines according to an N-bit row address, while the
column decoder circuit selects one out of 2M bit lines according to an M-bit column address.
Once a memory cell or a group of memory cells are selected in this fashion, a data read

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and/or a data write operation may be performed on the selected single bit or multiple bits on a
particular row. The column decoder circuit serves the double duties of selecting the particular
columns and routing the corresponding data content in a selected row to the output.

Dynamic Read-Write Memory (DRAM) Circuits

In a dynamic RAM cell, binary data is stored simply as charge in a capacitor, where the
presence or absence of stored charge determines the value of the stored bit. The data stored as
charge in a capacitor cannot be retained indefinitely, because the leakage currents eventually
remove or modify the stored charge. Thus, all dynamic memory cells require a periodic
refreshing of the stored data, so that unwanted modifications due to leakage are prevented
before they occur.
Unlike SRAM cell, the DRAM cell access circuitry is very simple but it also requires access
devices, for "read" and "write" operations. In addition, it also requires additional peripheral
circuitry for scheduling and performing the periodic data refresh operations. The hardware
overhead of the refresh circuitry, however, does not overshadow the area advantages gained
by the small cell size.
Fig 5.3 shows the historical evolution of the DRAM cell. The four-transistor cell shown in
Fig. 5.3(a) is the simplest dynamic memory cells. The cell has two storage nodes, i.e., the
parasitic oxide and diffusion capacitances. Since no current path is provided to the storage
nodes for restoring the charge being lost to leakage, the cell must be refreshed periodically.
The three-transistor DRAM cell shown in Fig. 5.3(b) utilizes a single transistor as the storage
device and one transistor each for the "read" and "write" access switches. The cell has two
control and two I/O lines. Its separate read and write select lines make it relatively fast, but
the four lines with their additional contacts tend to increase the cell area.
The one-transistor DRAM cell shown in Fig. 5.3(c) is widely used dynamic RAM cell in
high-density DRAM arrays. With only one transistor and one capacitor, it has the lowest
component count and, hence, the smallest silicon area of all the dynamic memory cells. The
cell has one read-write control line (word line) and one I/O line (bit line).

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Fig 5.3. Various configurations of the dynamic RAM cell. (a) Four-transistor DRAM cell
with two storage nodes. (b) Three-transistor DRAM cell with two bit lines and two word lines. (c)
One-transistor DRAM cell with one bit line and one word line.

Three-Transistor DRAM Cell

The circuit diagram of a typical three-transistor dynamic RAM cell is shown in Fig. 5.4 as
well as the column pull-up (precharge) transistors and the column read/write circuitry. Here,
the binary information is stored in the form of charge in the parasitic node capacitance Cl.
The storage transistor M2 is turned on or off depending on the charge stored in C1, and the
pass transistors Ml and M3 act as access switches for data read and write operations. The cell
has two separate bit lines for "data read" and "data write," and two separate word lines to
control the access transistors.
The operation of the three-transistor DRAM cell and its peripheral circuitry is based on a
two-phase non-overlapping clock scheme. The precharge events are driven by 𝞥1, whereas
the "read" and "write" events are driven by 𝞥2. Every "data read" and "data write" operation
is preceded by a precharge cycle, which is initiated with the precharge signal PC going high.
During the precharge cycle, the column pull-up transistors are activated, and the

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corresponding column capacitances C2 and C3 are charged up to logic-high level. All "data
read" and "data write" operations are performed during the active 𝞥2 phase, i.e., when PC is
low.

Fig 5.4 Three-transistor DRAM cell with the pull-up and read/write circuitry.
Fig 5.5 depicts the typical voltage waveforms associated with the 3-T DRAM cell during a
sequence of four consecutive operations: write " 1," read "1," write "0," and read "0." The
four precharge cycles shown in Fig. 5.4 are numbered 1, 3,5, and 7, respectively. During this,
the two column capacitances C2 and C3 are charged. These capacitances are larger than the
internal storage capacitance C1.
Write "1" operation
̅̅̅̅̅̅̅̅ is at the logic ‘0’, because the data to be written onto
✓ For the write "1" operation, 𝐷𝐴𝑇𝐴
the DRAM cell is logic "1." Consequently, the "data write" transistor is turned off, and
the voltage level on column Din remains high.
✓ Now the "write select" signal WS is pulled high during the active phase of 𝞥2. As a
result, the write access transistor Ml is turned on.
✓ With Ml conducting, the charge on C2 is now shared with Cl. Since the capacitance C2 is
very large compared to C1, the storage node capacitance Cl attains approximately the

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same logic-high level as the column capacitance C2 at the end of the charge-sharing
process.

Read "1" operation

✓ After the write "1" operation is completed, the write access transistor MI is turned off.
With the storage capacitance C1 charged-up to a logic-high level, transistor M2 is now
conducting.
✓ In order to read this stored "1," the "read select" signal RS must be pulled high during the
active phase of 𝞥2, following a precharge cycle.
✓ As the read access transistor M3 turns on, M2 and M3 create a conducting path between
the "data read" column capacitance C3 and the ground.
✓ The capacitance C3 discharges through M2 and M3, and the falling column voltage is
interpreted by the "data read" circuitry as a stored logic "1."

Fig 5.5 Typical voltage waveforms associated with the 3-T DRAM cell during four
consecutive operations: write "1," read "1," write "0," and read "O."
Write "0" operation
̅̅̅̅̅̅̅̅ is at the logic “1”, because the data to be written onto
✓ For the write "0" operation, 𝐷𝐴𝑇𝐴
the DRAM cell is a logic "0." Consequently, the data write transistor is turned on, and the
voltage level on column Din is pulled to logic "0."

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✓ Now, the "write select" signal WS is pulled high during the active phase of 𝞥2. As a
result, the write access transistor Ml is turned on. The voltage level on C2, as well as that
on the storage node Cl, is pulled to logic "0" through MI and the data write transistor.
✓ Thus, at the end of the write "0" sequence, the storage capacitance C1 contains a very low
charge, and the transistor M2 is turned off since its gate voltage is approximately equal to
zero.
Read "0" operation
✓ In order to read this stored "0," the "read select" signal RS must be pulled high during the
active phase of 𝞥2, following a precharge cycle. The read access transistor M3 turns on,
but since M2 is off, there is no conducting path between the column capacitance C3 and
the ground.
✓ Consequently, C3 does not discharge, and the logic-high level on the Dout column is
interpreted by the data read circuitry as a stored "0" bit.

One-Transistor DRAM Cell

The one-transistor (1-T) DRAM cell consists of one storage capacitor and one access
transistor is shown in Fig. 5.6. Cl represents the storage capacitor and C2 represents the much
larger parasitic column capacitance. Binary data are stored as the presence or absence of
charge in the storage capacitor.

Fig 5.6. (a) Typical one-transistor (1-T) DRAM cell with its access lines
Write Operation:
✓ For the write "1" operation, the bit line (D) is raised to logic " 1 " by the write circuitry,
while the selected word line is pulled high by the row address decoder.

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✓ The access transistor Ml turns on, allowing the storage capacitor C to charge up to a
logic-high level.
✓ For the write "0" operation, the bit line (D) is pulled to logic "0" and the word line is
pulled high by the row address decoder.
✓ In this case, the storage capacitor C discharges through the' access transistor, resulting in
a stored "0" bit.
Read Operation:
✓ In order to read stored data out of a 1T DRAM cell, on the other hand, we have to
build a fairly elaborate read-refresh circuit. The reason for this is the fact that the "data
read" operation on the one-transistor DRAM cell is by necessity a "destructive readout."
This means that the stored data must be destroyed or lost during the read operation.
✓ The read operation starts with precharging the column capacitance C.
✓ Then, 'the word line is pulled high in order to activate the access transistor Ml.
✓ Charge sharing between C1 and C2 occurs and, depending on the amount of stored charge
on C1, the column voltage either increases or decreases slightly.
✓ This charge sharing inevitably destroys the stored charge on C1. Hence, we also have to
refresh data every time we perform a "data read" operation.

Static Read-Write Memory (SRAM) Circuits

The memory circuit is said to be static if the stored data can be retained indefinitely (as long
as a sufficient power supply voltage is provided), without any need for a periodic refresh
operation.
The 1-bit memory cell in static RAM arrays, consists of a simple latch circuit with two stable
operating points (states). The states of the two-inverter latch circuit, is interpreted either as a
logic "0" or as a logic " 1." To access (read and write) the data contained in the memory cell
via the bit line, one switch each controlled by the corresponding word line is used. (Fig.
5.7(a)).
Fig 5.7(b) shows the generic structure of the MOS static RAM cell, consisting of two cross-
coupled inverters and two access transistors. The load devices may be polysilicon resistors
(Fig. 5.7(c)), depletion-type nMOS transistors, or pMOS transistors, depending on the type of
the memory cell. The pass gates acting as data access switches are enhancement-type nMOS
transistors.

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The six-transistor depletion-load nMOS SRAM cell shown in Fig. 5.6(d) can be easily implemented
with one polysilicon and one metal layer, and the cell size tends to be relatively small, especially with
the use of buried metal-diffusion contacts.
The full CMOS SRAM cell shown in Fig. 5.6(e) achieves the lowest static power dissipation among
the various circuit configurations.

Fig 5.7. Various configurations of the static RAM cell. (a) Symbolic representation of the
two-inverter latch circuit with access switches. (b) Generic circuit topology of the MOS static
RAM cell. (c) Resistive-load SRAM cell. (d) Depletion-load nMOS SRAM cell. (e) Full CMOS
SRAM cell.

Full CMOS SRAM Cell

The circuit structure of the full CMOS static RAM cell is shown in Fig. 5.8, along with the
pMOS column pull-up transistors on the complementary bit lines. The memory cell consists
of a simple CMOS latch and two complementary access transistors (M3 and M4). The cell
will preserve one of its two possible stable states, as long as the power supply is available.
The access transistors are turned on whenever a word line is activated for read or write
operation, connecting the cell to the complementary bit-line columns. The most important
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advantage of this circuit topology is that the static power dissipation is even smaller;
essentially, it is limited by the leakage current of the pMOS transistors.

Fig 5.8. Circuit topology of the CMOS SRAM cell.

CMOS SRAM Cell Design Strategy

Read “0” operation: Consider the data read operation first, assuming that a logic "0" is
stored in the cell. The voltage levels in the CMOS SRAM cell at the beginning of the "read"
operation are depicted in Fig. 5.9. Here, the transistors M2 and M5 are turned off, while the
transistors Ml and M6

Fig 5.9. Voltage levels in the SRAM cell at the beginning of the "read" operation

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in the linear mode. Thus, the internal node voltages are V1 = 0 and V2 = VDD before the cell
access (or pass) transistors M3 and M4 are turned on.
After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage
level of column C’ will not show any significant variation since no current will flow through
M4. On the other half of the cell, however, M3 and Ml will conduct a nonzero current and the
voltage level of column C will begin to drop slightly. The data read circuitry is responsible
for detecting this small voltage drop and amplifying it as a stored "0. "
Write “0” operation: Consider the write "0" operation, assuming that a logic "1" is stored in
the SRAM cell initially. Fig 5.10 shows the voltage levels in the CMOS SRAM cell at the
beginning of the data-write operation. The transistors M1 and M6 are turned off, while the
transistors M2 and M5 operate in the linear mode. Thus, the internal node voltages are V =
VDD and V2= 0 V before the cell access (or pass) transistors M3 and M4 are turned on.

Fig 5.10 Voltage levels in the SRAM cell at the beginning of the "write" operation.

The column voltage VC is forced to logic "0" level by the data-write circuitry. Once the pass
transistors M3 and M4 are turned on by the row selection circuitry, the node voltage V2
remains below the threshold voltage of Ml, since M2 and M4 are designed accordingly.
Consequently, the voltage level at node (2) would not be sufficient to turn on Ml. To change
the stored information, i.e., to force V1 to 0 V and V2 to VDD, the node voltage V1 must be
reduced below the threshold voltage of M2, so that M2 turns off first. When V1 = VTh, the
transistor M3 operates in the linear region while M5 operates in saturation. M3 and M5 are
designed such that, the transistor M2 will be forced into cut-off mode during the write "0"
operation. This will guarantee that Ml subsequently turns on, changing the stored
information.

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