8086 MEMORY INTERFACING:

 Most the memory ICs are byte oriented i.e., each memory location can store only
one byte of data.

 The 8086 is a 16-bit microprocessor, it can transfer 16-bit data.

 So in addition to byte, word (16-bit) has to be stored in the memory.

 To implement this , the entire memory is divided into two memory banks: Bank0
and Bank1.

 Bank0 is selected only when A0 is zero and Bank1 is selected only when
BHE’ is zero.

 A0 is zero for all even addresses, so Bank0 is usually referred as even addressed
memory bank.

 BHE’ is used to access higher order memory bank, referred to as odd

 Almost all systems contain two basic types of memory, read only memory
(ROM) and random access memory (RAM) or read/write memory.

 ROM contains system software and permanent system data such as lookup
tables, IVT..etc.

 RAM contains temporary data and application software.

 ROMs/PROMs/EPROMs are mapped to cover the CPU’s reset address,

 When the 8086 is reset, the next instruction is fetched from the memory location
FFFF0H.

 So in the 8086 system the location FFFF0H must be in ROM location.

2. Linear decoding

3. Block decoding

1. Absolute Decoding:

 In the absolute decoding technique the memory chip is selected only for the
specified logic level on the address lines: no other logic levels can select the
chip.

 Below figure the memory interface with absolute decoding. Two 8K EPROMs (2764)
are used to provide even and odd memory banks.

 Control signals BHE and A0 are use to enable output of odd and even memory
banks respectively. As each memory chip has 8K memory locations, thirteen
address lines are required to address each locations, independently.
 All remaining address lines are used to generate an unique chip select signal.
This address technique is normally used in large memory systems.
Linear Decoding:

In small system hardware for the decoding logic can be eliminated by using only required
number of addressing lines (not all). Other lines are simple ignored. This technique is referred as
linear decoding or partial decoding. Control signals BHE and Ao are used to enable odd and even
memory banks, respectively. Figure shows the addressing of 16K RAM (6264) with linear
decoding.
  The address line A19 is used to select the RAM chips. When A19 is low, chip is selected,
otherwise it is disabled. The status of A14 to A18 does not affect the chip selection
logic. This gives you multiple addresses (shadow addresses). This technique reduces the
cost of decoding circuit, but it gas drawback of multiple addresses.

Block Decoding:

In a microcomputer system the memory array is often consists of several blocks of memory
chips. Each block of memory requires decoding circuit. To avoid separate decoding for each
memory block special decoder IC is used to generate chip select signal for each block.
 Interfacing RAM, ROM, EPROM to 8086:

 The general procedure of static memory interfacing with 8086

1. Arrange the available memory chips so as to obtain 16-bit data bus width.

• The upper 8-bit bank is called ‘odd address memory bank’.

• The lower 8-bit bank is called ‘even address memory bank’.

2. Connect available memory address lines of memory chips with those of the
microprocessor and also connect the RD and WR inputs to the corresponding processor
control signals.

3. Connect the 16-bit data bus of memory bank with that of the microprocessor 8086.

4. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the
required chip select signals for the odd and even memory banks. The CS of memory is
derived from the output of the decoding circuit.

Interface two 4Kx8 EPROM and two 4Kx8 RAM chips with 8086. Select suitable maps

We know that, after reset, the IP and CS are initialized to form address FFFF0H. Hence, this address
must lie in the EPROM. The address of RAM may be selected anywhere in the 1MB address space of
8086, but we will select the RAM address such that the address map of the system is continuous

8K bytes of EPROM need 13 address lines A0-A12 (since z13 = 8K). Address lines A13 - A19 are used
for decoding to generate the chip select. The 𝐵𝐻𝐸 signal goes low when a transfer is at odd address
or higher byte of data is to be accessed. Let us assume that the latched address, 𝐵𝐻𝐸 and
demultiplexed data lines are readily available for interfacing. The memory system in this problem
contains in total four 4K x 8 memory chips. The two 4K x 8 chips of RAM and ROM are arranged in
parallel to obtain 16-bit data bus width. If A0 is 0, i.e., the address is even and is in RAM, then the
lower RAM chip is selected indicating 8-bit transfer at an even address. If A0 is i.e., the address is
odd and is in RAM, the 𝐵𝐻𝐸 goes low, the upper RAM chip is selected, further indicating that the 8-
bit transfer is at an odd address. If the selected addresses are in ROM, the respective ROM chips are
selected. If at a time A0 and 𝐵𝐻𝐸 both are 0, both the RAM or ROM chips are selected, i.e., the data
transfer is of 16 bits.

Memory Chip Selection Table:

Decoder I/P --> A2 A13 A1 A0 Sel

Address/BHE --> A0 BHE

Word transfer on D0 - D15 0 0 0 Even and odd address in

Byte transfer on D8 - D15 0 1 0 Only odd address in RAM

Word transfer on D0 - D15 1 0 0 Even and odd address in

Byte transfer on D8 - D15 1 1 0 Only odd address in ROM

2.Design an interface between 8086 CPU and two chips of 16K×8 EPROM and two chips of
32K×8 RAM. Select the starting address of EPROM suitably. The RAM address must start at
00000 H.

The last address in the map of 8086 is FFFFF H. after resetting, the processor starts from FFFF0 H.
hence this address must lie in the address range of EPROM.
 It is better not to use a decoder to implement the above map because it is not continuous, i.e.
there is some unused address space between the last RAM address (0FFFF H) and the first
EPROM address (F8000 H). Hence the logic is implemented using logic gates.

3. It is required to interface two chips of 32K×8 ROM and four chips of 32K×8 RAM with 8086,
according to following map.
 ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and RAM 2 D0000H - DFFFFH, RAM 3 and RAM 4
E0000H - EFFFFH. Show the implementation of this memory system.

1. 20-bit addresses are provided for IO devices. 1. 8-bit or 16-bit address are provided for IO
devices
2. The IO ports or peripherals can be treated like memory
2. Only IN and OUT instructions can be used for
locations and so all instructions related to memory can
data transfer between IO device and the
be used for data transfer.
processor.

3. In memory mapped ports, the data can be moved from 3. In IO mapped ports, the data transfer can
any register to port and vice versa take only between the accumulator and
the ports