Features of Intel 8279 Programmable Keyboard Display

Interface:

The Intel 8279 is a general purpose programmable keyboard and

display I/O interface device designed for use with Intel
microprocessors. The Features of Intel 8279 Programmable Keyboard
Display Interface are
1. It provides a scanned interface to a 64-contact key matrix, with two
more keys CONTROL and SHIFT.
2. It provides three input modes for keyboard interface;
 Scanned Keyboard Mode
 Scanned Sensor Matrix Mode
 Strobed Input Mode
3. It has built-in hardware to provide key debounce.
4. It allows key depressions in 2 key lockout or N-key rollover mode,
which eliminates software required to implement 2 key lockout and N-
key rollover
5. The interrupt output of 8279 can be used to tell CPU that the
keypress is This eliminates the need of software polling.
6. Features of Intel 8279 provides 8 byte FIFO RAM to store keycodes.
This allows to store 8 key board inputs when CPU is busy in performing
his own computation.
7. It provides multiplexed display interface with blanking and inhibit
options.
8. It provides sixteen byte display RAM to store display codes for 16
digits, allowing to interface 16 digits.
9. In auto increment mode, address of display RAM and FIFO RAM is
incremented automatically which eliminates extra command after each
read/write operation to access successive locations of display RAM and
FIFO
10. Features of Intel 8279 provides two output modes for display
interface.
 Left Entry (typewriter type)
 Right Entry (calculator type)
11. Simultaneous keyboard and display operation facility allows to
interleave keyboard and display software

Pin Diagram of 8279:

Fig. 14.83 shows functional and pin diagram of 8279. It is a 40 pin

device and looking at Fig. 14.83 (a) we can see that these pins are
divided in four functional groups :
1. CPU interface

2. Key data

3. Display data

4. Scan
CPU Interface Pins:

As shown in Fig. 14.83 (a), it consists of 8-bit data bus, RD, WR, A 0, CS,
RESET, CLK and IRQ lines.
DB0-DB7 : Bi-directional data bus :
All data, commands and status information between the CPU and the
8279 are transmitted on these bi-directional 8-bit data bus.
RD : Read:
It is an active low signal. When RD signal is low CPU reads the contents
of selected register (display RAM, status register or FIFO RAM) from
8279; depending on the type of command and the status of the A0
signal.
WR : Write:
It is an active low signal. When WR signal is low, CPU loads the data into
selected register (control register or display register) depending on the
status of A0 signal.
A0 : Address line:
When A0 is high, signals are interpreted as a command or status. When
A0 is low, signals are interpreted as a data.
CS : Chip select :
It is an active low signal. When low, enables the communication
between CPU and 8279.
RESET : A high signal on this pin resets 8279. After being reset 8279 is
configured in the following mode.
1. Sixteen 8-bit character display-left entry

2. Encoded scan keyboard- 2 key lockout

3. The program clock prescaler is set to 31.

CLK : This signal is usually driven by the system dock and used to
generate internal timings.
IRQ : Interrupt Request :
This signal is used to implement interrupt driven input system. In
scanned keyboard mode, the interrupt line goes low when there is data
in the FIFO/sensor RAM. The interrupt line goes low with each
FIFO/sensor RAM read and returns high if there is still information in
the RAM. In sensor matrix mode, the interrupt line goes high whenever
a change in a sensor is detected. The IRQ line is cleared by the first data
read operation if the auto increment flag is set to zero, or by the End
interrupt command if the Auto-increment flag is set to one. The
interrupt feature of Pin Diagram of 8279 eliminates the need of polling
the keyboard.
Keyboard Data:

This group consists of return, SHIFT and CNTL/STB lines.

RL0-RL7 : Return lines : These input lines are used to interface matrix
keyboard. These lines have active internal pullups which keep their
status high. When the key from, the matrix keyboard is pressed
corresponding return line goes low. In the strobed input mode these
lines are used as 8 input lines.
SHIFT : It is a special key input line. Its status is stored along with the
key position on the key closure in the scanned keyboard modes. It has
an active internal pullup to keep it high until, a switch closure pulls it
low.
CNTL/STB : Control/strobe
For scanned keyboard mode this line is used as a control input. Like
SHIFT key, its status is stored along with the key position on the key
closure. It also has an active internal pullup to keep it high until a switch
closure pulls it low.
In the strobed input mode this line is used as a strobe input. When
activated, loads the status of keyboard into the FIFO RAM.
Display Data:

This group consists of OUT A3-A0, OUT B3-B0 and BD lines.

OUT A3-A0 and OUT B3-B0 : These two four bit output ports; which can
be considered as an one 8-bit port. These are used for sending data to
display drivers from display RAM and connected to the segment inputs
of 7 segment display or row inputs of dot matrix displays. These lines
are synchronized to the scan lines (SL0-SL3) for multiplexed digit display.
In other words we can say that when the data on the scan lines is 0000,
ports will have data from register 0 of display RAM and when the data
on the scan lines is 1111, ports will have data from register 15 of display
RAM. The two 4-bit ports can be blanked independently.
BD : Blank Display :
This is an active low output used to blank the display during digit
switching or by a display blanking command.

8279 Block Diagram:

Fig. 14.84 shows the 8279 Block Diagram. It consists of four main
sections
1. CPU interface and control section
2. Scan section
3. 8279 Keyboard section
4. Display section
1.CPU Interface and Control Section:

This section consists of data buffers, I/O control, control and timing
registers, and timing and control logic.
Data Buffers

The data buffers are 8-bit bi-directional buffers that connect the
internal data bus to the external data bus.
I/O Control

The I/O control section uses the A0, CS, RD and WR signals to control
data flow to and from the various internal registers and buffers. The
data flow to and from the Block Diagram of 8279 is enabled only when
CS = 0; otherwise the 8279 signals are in a high impedance state. The
Block Diagram of 8279 interprets the data given or desired by the CPU
with the help of A0, RD and WR signals, as shown in table 14.8. When
A0 is logic 0 data is transferred and when A 0 is logic 1 command word or
status word is transferred. RD and WR determine -the direction of data
flow through the data buffers.

Control and Timing Registers:

The control and timing registers store the keyboard and display modes
and other operating conditions programmed by the CPU. The modes
are programmed by sending the proper command on the data lines
with A0 = 1. The command is latched on the rising edge of WR. The
command is then decoded and the appropriate mode/function is set.
Timing Control:

The timing control consists of the basic timing counter chain. The first
counter is divided by N prescaler that can be programmed to give an
internal frequency of 100 kHz. The other counters divide down the
basic internal frequency, to provide the proper keyscan, row scan,
keyboard matrix scan, and display scan times. The internal frequency of
100 KHz gives the internal timings as shown in the table 14.9.

2. Scan Section (Scan counter):

The scan section has a scan counter which has two modes : Encoded
mode and decoded mode.
Encoded Mode:

In the encoded mode, the scan counter provides a binary count from
0000 to 1111 on the four scan lines (SC3 — SC0) with active high
outputs. This binary count must be externally decoded to provide 16
scan lines.
Display can use all 16 scan lines to interface 16 digit 7-segment display,
but keyboard can use only 8 scan lines out of 16 scan lines.
Decoded Mode:

In the decoded mode, the internal decoder decodes the least significant
2 bits of binary count and provides four possible combinations on the
scan lines (SC3 — SC0) :1110, 1101, 1011 and 0111. Thus the output of
decoded scan is active low. These four active low output lines can be
used directly to interface 4 digit 7 segment display, 8 x 4 matrix
keyboard, eliminating the external decoder.
3. 8279 Keyboard section:

This section consists of return buffers, keyboard debounce and control,

FIFO/sensor RAM and FIFO/sensor RAM status. There functions depend
on selected keyboard mode out of three keyboard input modes :
scanned keyboard, sensor matrix and strobed input.
Return buffers:

The 8 return lines (RL7 — RL0) are buffered and latched by the return
buffers during each row scan in scanned keyboard or sensor matrix
imode In strobed input mode, the contents of the return lines are
transferred to the FIFO RAM on the rising edge of the CNTL/STB line
pulse.
Keyboard debounce and control:

Keyboard and debounce control is enabled only when scanned

keyboard mode is selected. In the scanned keyboard mode, return lines
are scanned, looking for key closures in that row. If the debounce
circuit detects a close switch, it waits about 10 msec to check if the
switch remains closed. If it does, the address of the switch in the matrix
plus the status of SHIFT and CONTROL keys are transferred to the FIFO
RAM.
FIFO/Sensor RAM:

This is a dual function 8 x 8 RAM. In scanned keyboard and strobed

input modes, it is a FIFO. Each new entry is written into successive RAM
positions and then read in order of entry. In sensor matrix mode, the
memory is referred to as sensor RAM. Each row of the sensor RAM is
loaded with the status of the corresponding row of sensor in the sensor
matrix.
FIFO/sensor RAM status:

FIFO RAM status keeps track of the number of characters in the FIFO
and whether it is full or empty. The status logic also makes IRQ signal
high when the FIFO is not empty, which can be used to interrupt CPU
telling that key press is detected and keycode is available in FIFO RAM.
4. Display section:

The display section consists of display RAM, display address registers

and display registers.
Display RAM:

It is 16 x 8 RAM, which stores the display codes for 16 digits. It can be

accessed directly by CPU. In decoded mode, 8279 uses only first four
locations of display RAM. In encoded mode, Block Diagram of 8279 uses
first eight locations for 8 digit display and all 16 lorntions for 16 digits
display.
Display address registers:

The display address registers hold the address of the byte currently
being written or read by the CPU and scan count value. The read/write
addresses are programmed by CPU command. If set in auto
increment mode, address in the address register is incremented for
each read or write.
Display registers:

Display registers are two 4-bit registers A and B. They hold the bit
pattern of character to be displayed. The contents of display registers A
and B can be blanked and inhibited individually.

Operating Modes of 8279:

The Operating Modes of 8279 provides 3 basic input modes :

1. Scanned keyboard

2. Scanned sensor matrix

3. Strobed input

Scanned Keyboard:

In this mode, keyboard can be scaned in two ways : Encoded scan and
decoded scan.
Encoded scan : In the encoded scan, scan lines (SL2-SL0) are decoded
externally to provide 8 scan lines. We know that Operating Modes of
8279 provides 8 returns lines. Therefore, the maximum size of
keyboard matrix is 8 x 8 = 64. When the key is pressed, 8279 stores the
encoded status of scan lines and return lines along with the status of
SHIFT and CNTL/STB keys into the FIFO RAM, as shown in the Fig. 14.85.
 CNTL is
the MSB of the character and shift is the next most significant bit. The
next three bits are from the scan counter. The last three bits indicate to
which return line the key is connected. With this 8-bit key code
Operating Modes of 8279 can recognize 256 (28) different characters.
Display Modes:

The Operating Modes of 8279 provides 2 basic output modes

1. Left Entry (type writer type)

2. Right Entry (calculator type) Left Entry

In the left entry mode, Operating Modes of 8279 displays characters

from left to right in the multiplexed displays like a typewriter. In this,
each display position is directly corresponds to a byte (or nibble) in the
display RAM. Address 0 in the RAM is the left-most display character
and address 15 (or address 7 in 8 character display) is the right most
display character, as shown in the Fig. 14.86 (a) and (b).
Entering characters from possible zero causes the display to fill from
the left. The 17th (9th in case 8 character display) character is entered
back in the left most position and filling again proceeds from there, as
shown in the Fig. 14.87 (a). The characters can be displayed on the
specific digit by loading character code in the corresponding location in
the display RAM
Autoincrement in Left Entry:

In left entry mode, if autoincrement flag is set to 1 after each write

operation display RAM address is incremented by one so that it will
point the next location in the display RAM. This autoincrement facility
allows user to load display RAM in a sequential manner, and it is not
necessary to specify display RAM address for each write operation.
Right Entry:

In the right entry mode, Operating Modes of 8279 displays characters

from right to left in the multiplexed display like a calculator. The first
entry is displayed on the right most display. The next entry is also
displayed on the right most display after the display is shifted left one
character, as shown in the Fig. 14.87 (b).

When new character is entered, it shifts all previous characters left by

one position and displays new entry on the right most display.
Autoincrement in Right Entry:

In the right entry mode, auto incrementing and non autoincrementing

have the same effect as in the left entry except if the address sequence
is changed. Some examples with changed address sequence
First character is displayed on the right most digit of the display. After
second entry first character is shifted left and second character is
displayed on the right most digit of the display. In the third entry,
address of display RAM is changed to 5, displaying the third character
at fifth digit after shifting the previous characters 1 digit left. In the
4th Entry the new character is displayed at 5 th digit after shifting all
previous characters 1 digit left, and this sequence is continued (Fig.
14.88).
8279 Commands:

In the last sections we have seen various operating modes of Operating

Modes of 8279. To program 8279 in the desired mode it provides eight
command words. The command words are sent on the data bus with CS
low and A0 high and are loaded to the 8279 on the rising edge of WR.
8279 differentiate these commands by checking 3 most significant bits
of the command word.
Keyboard/Display Mode Set Command (000):

This command is used to program operating modes of keyboard and

display. Three least significant bits decide the keyboard mode and next
two bits decide the display mode, as shown in the tables.
Command Word Format:
Program Clock Command (001):

All timing and multiplexing signals for the Operating Modes of 8279 are
generated by an internal prescaler. This prescaler divides the external
clock by a programmable integer value given in the program clock
command word, to generate internal frequency Fig. 14.90 shows
format for program clock command word.

Bits PPPPP determine the value of this integer which ranges from 2 to
31. To give proper scan and key debounce times the internal frequency
should be 100 kHz. Therefore, prescaler integer value should be
selected to get 100 kHz internal frequency.

Read FIFO/Sensor RAM Command (010):

To read data from FIFO/sensor RAM, it is necessary to set 8279 in read

FIFO/sensor RAM mode. Read FIFO/sensor RAM command is used for
this purpose Fig. 14.91 shows the format for Read FIFO/Sensor RAM
command.
Here, three least significant bits, (AAA) specify the address of the
sensor RAM and bit B4, if 1 enables autoincrement mode. In the scan
keyboard mode, the autoincrement flag (AI) and the FIFO RAM address
bits (AAA) are irrelevant. In this mode, Operating Modes of 8279
provides data for each subsequent read in the same sequence in which
the data first entered in the FIFO RAM.
In the sensor matrix mode, the sensor RAM address bits AAA select one
of the 8 rows of the sensor RAM. If the autoincrement flag is set (AI =
1), each successive read will be from the subsequent row of the sensor
RAM.
Read Display RAM Command (011):

To read data from display RAM, it is necessary to set 8279 in read

display RAM mode. Read display RAM command is used for this
purpose. Fig. 14.92 shows the format for Read Display RAM command

Here, four least significant bits (AAAA) Specify the address ‘of the 16
byte display RAM and bit B4, if 1, enables autoincrement mode. If the
bit B4 (AI) is set, display RAM address is incremented after each read
command to display RAM.
Write Display RAM Command (100):

To write data into display RAM, it is necessary to set 8279 in write

display RAM mode. Write display RAM command is used for this
purpose. Fig. 14.93 shows the format for write Display RAM command.

Here, four least significant bits (AAAA) specify the address of the 16
byte display RAM and bit B4, if 1, enables autoincrement mode. If the
bit B4 (AI) is set, display RAM address is incremented after each write
command to display RAM.
Display Write Inhibit/Blanking Command (101):

We know that, display RAM data is sent on the two 4-bit ports (B 3 —
B0 and A3 —A0) This two 4-bit pots can be individually inhibited or
blanked with display write inhibit/blanking command. Fig. 14.94 shows
the format for display write Inhibit/Blanking Command

The IW bits are used to mask nibble A (4-bit port A) and nibble B (4-bit
port B) in applications requiring separate 4-bit display ports. By setting
the IW flag (I/W = 1) for one of the ports, the port can be masked so
that entries to the display RAM from the CPU do not affect other port.
The BL bits are used to blank the individual nibbles. This command
loads the blank code (All zeros, 20H, or All ones) determined by the last
issued clear command, in the display RAM to blank the display.
Note : After reset blank code is set to all zeros.
Clear Command (110):

Clear command is used to clear all the rows of the display RAM with a
selectable blanking code, to clear status of FIFO RAM and to reset
interrupt output line. Fig. 14.95 shows the format of display command

CD bits (CD0 — CD1 ) are used to select the blanking code as given below

Bit CD2, when set to one, enables clear display

Bit CF, when set to one, clears the status of the FIFO, resets the
interrupt output line and sets the sensor RAM address to 000.
CA, the clear all bit, has the combined effect of CD and CF; it uses the
CD clearing code on the displays RAM and also clears FIFO status. It also
resynchronizes the internal timing chain.
End Interrupt/Error Mode Set Command (111):

In the sensor matrix mode, if any change in sensor value is detected,

IRQ line goes high at the end of a sensor matrix scan. The IRQ line is
cleared by the first data read operation if the autoincrement flag is set
to zero. But if autoincrement flag is set to one then it is necessary to
issue End Interrupt Command to clear the IRQ line. Fig. 14.96 shows the
format for End Interrupt/Error mode set command.

For the N key rollover mode, if the E bit is programmed to ‘1’, the 8279
will operate in the Special Error Mode. In the special error mode, if two
keys are depressed during single debounce, the error flag in the FIFO
status word is set.

Interfacing 8279 with 8086 in I/O Mapped I/O:

Fig. 14.100 shows the interfacing of 8279 with 8086 in I/O mapped I/O
technique. Here RD and WR signals are activated when M/IO signal is
low, indicating I/O bus cycle. Reset out signal from 8086 system is
connected to the Reset signal of the 8279. CLK input of 8279 is driven
from the clock signal of 8086 system. A1 signal from the 8086 is
connected to the A0 input of 8279. The chip select signal, CS is
generated using decoding circuit. Interrupt signal from the 8279 is
connected to the interrupt input of 8086.
Interfacing 8279 with 8086 in Memory Mapped I/0:

Fig. 14.101 shows the interfacing of 8279. with 8086 in memory

mapped,I/O technique. Here, RD and WR signals are activated when
M/IO signal is high, indicating memory bus, cycle. To get absolute
address, all remaining address lines (A 2-A19) are used to decode the
address for 8279. Other signal connections are same as in I/O mapped
I/O.