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Code Conversion
A code converter is a combinational circuit that modifies data presented in one (1) type of binary code to another type of binary code.
Types of binary codes:
• Weighted codes follow the positional weighting principles; each position of the number represents a specific weight. The binary
counting sequence is an example.
o 8421 Code/BCD Code represents each decimal digit using a 4-bit code with weights 8, 4, 2, and 1. The binary combinations
1010 through 1111 (10 to 15 in decimal) are not used and have no meaning in BCD.
Sample Problem: Represent the decimal number 342.61 in BCD code.
Solution:

Thus, given the example, 342.6110 when represented in BCD code becomes
𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝑩𝑩𝑩𝑩𝑩𝑩

o 2421 Code represents each decimal digit in a 4-bit form with weights 2, 4, 2, and 1. The binary combinations 0101 through
1010 (5 to 10 in decimal) are not used and have no meaning in the 2421 code. Note that according to the weights, certain
digits may have alternative codes. For instance, the digit three (3) could be represented as 0011 or 1001. However, we pick
the former in the standard 2421 coding so that the codes for the first five digits 0 – 4 begin with 0, whereas the codes for the
last five digits 5 – 9 begin with 1.
Sample Problem: Represent the decimal number 168 in 2421 code.
Solution:

Thus, given the example, 16810, when represented in 2421 code becomes
0001110011102421

o 5211 Code – It represents each decimal digit in a 4-bit form with weights 5, 2, 1, and 1. The binary combinations 0010, 0100,
0110, 1001, 1011, and 1101 (2, 4, 6, 9, 11, and 13 in decimal) are not used and have no meaning in the 5211 code.

• Non – Weighted Codes are codes that are not positionally weighted. That is, each position within the binary number is not
assigned a fixed value.
o Excess-3 Code – It is a non-weighted code that uses a bias value of three – each binary code is the corresponding 8421 code
plus 0011(3). The binary combinations 0000 through 0100 and 1101 through 1111 (0 to 4 and 13 to 15 in decimal) are not
used and have no meaning in this code.

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Sample Problem: Convert BCD code to Excess-3 code.

Solution:
 Specification: A, B, C, and D are assigned as the input variables for BCD code and W, X, Y, and Z as the output variables
for Excess-3.

 Formulation: The Excess-3 code is derived from the natural BCD code by adding 3 to
each coded number. Thus, the relationship between the BCD code (which is the input)
and Excess-3 (which is the output) is shown in the truth table on the right side.

 Optimization: The simplified Boolean expression for the output variables of Excess-3 is
obtained by using the Karnaugh map method below. Note that the binary combinations
1010 through 1111 (10 to 15 in decimal) in BCD code (input) serve as the “don’t cares”
(X).

For W: For X:

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For W: For X:

For Y: For Z:

For Y: For Z:

 Technology Mapping: The W, X, Y, and Z equations are translated into a circuit shown below:

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o Gray Code – It is a non-weighted code in which every transition from one value to the next value involves only one-bit change.

Rules for converting a binary code to Gray code:

1. Copy the leftmost digit (most significant bit) of the binary code.
2. Add each adjacent pair of binary code bits to get the next Gray code bit.
3. Discard carries.
Sample Problem: Represent the binary number 1000 in Gray code.
Solution:

Rules for converting Gray code to binary code:

1. Copy the leftmost digit (most significant bit) of the Gray code.
2. Add each binary code bit generated to the Gray code bit in the next adjacent
position
3. Discard carries
Sample Problem: Represent 1000 in Gray code to binary code.
Solution:

• Reflective Codes are codes that are self-complementing. It can be observed in the following table for 2421 and 5211 codes below:
Note: 8421 code is not reflective.

For 2421 code, it can be seen that:

o The decimal 9 (1111) code complements the code for decimal 0 (0000).
o The decimal 8 (1110) code complementsthe code for decimal 1 (0001).
o The decimal 7 (1101) code complements the code for decimal 2 (0010).
o The decimal 6 (1100) code complementsthe code for decimal 3 (0011).
o The decimal 5 (0101) code complementsthe code for decimal 4 (0100).

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• Sequential Codes are the codes in which two (2) succeeding numbers in binary representation differ by only one digit. The 8421
and Excess-3 codes are sequential, whereas the 2421 and 5211 codes do not come under this code.

Sequential Logic
The combinational logic circuit is the opposite of sequential logic,.The values of both inputs influence the output from the outside of
the circuit design and the present state of the memory elements. Thus, it employs memory (a. k. a. storage) elements that form a
previous output state’s feedback path to the combinational circuit.
Two Types of Sequential Circuits:
• Asynchronous sequential circuit: Its circuit output can change at any time (clockless). In asynchronous sequential circuits, the
storage elements are time-delay devices (i.e., storage is because of their propagation delay). They are implemented by the
feedback that may cause instability in asynchronous circuits.

Figure 1. Block Diagram of an Asynchronous Sequential

Logic Circuits.

• Synchronous sequential circuit: Its circuit output changes only at some discrete instants of time. This type of circuits achieves
synchronization by clock generators or simply, the clock. A clock produces a periodic train of clock pulses from which the required
changes in the storage devices are timed. Clock pulses are timed pulses of high and low-logic level electric signals. The storage
elements used in clocked sequential circuits are called flip-flops.
Figure 2. Block Diagram of a Synchronous Sequential Logic
Circuits.

The flip-flops in Figure 2 receive their inputs from the

combinational circuit and from a clock signal with pulses
that occur at fixed intervals of time, as shown in the clock
pulses’ timing diagram below.

Latches and Flip-flops

• Latches are building blocks of sequential circuits built from logic gates and from which flip-flops are usually constructed. These
are asynchronous, which means that their outputs are constantly affected by their inputs as long as the enable signal is asserted.
In other words, when they are enabled, their content changes immediately when their inputs change.
Types of Latches:
a. SR (Set-Reset) Latch works independently of control signals and relies only on the state of the S and R inputs. This latch can
be created with two NOR gates that have a cross-feedback loop. It can also be made from the NAND gates, but the inputs are
swapped and negated. In this case, it is sometimes called S’R’ Latch.

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For Cross NOR SR Latch:

o When the Set and Reset inputs of an SR latch are both low, feedback maintains the Q and Q’ outputs in a constant state,
with Q’ the complement of Q.
o When a high input on the Reset input of an SR latch is applied, and the Set is held low, the Q output goes low (and Q’
high), effectively resetting the latch's "memory".
o Conversely, when a high input is applied to the Set input of an SR latch, and the Reset is held low, the Q output goes high
(and Q’ low).
o When both inputs of an SR latch are high, it is called a restricted combination or a forbidden state because both gates
output zeros, which breaks the logical equation Q = not Q. The combination is also inappropriate in circuits. This produces
a "race condition" within the circuit where the output would lock at either 1 or 0 depending on the gates’ propagation
time relations.

b. Gated SR (Set-Reset) Latch is a simple extension of the SR latch that provides an Enable line that must be driven high before
data can be latched. This latch can be made by adding a second level of AND gates to the direct SR latch (or a second level of
NAND gates to the inverted SR latch). Even though a control line is now required, the SR latch is not synchronous because the
inputs can change the output if the enable line is held high at length. The enable input is sometimes a clock signal, but more
often a read or write strobe. When the enable input is a clock signal, the gated SR latch becomes an SR flip flop because the
output changes only when edge-triggered by the clock.
o When the Enable input is low, the outputs from the AND gates are also low; thus, the Q and Q’ outputs remain in the
state it was left.
o Only when the enable input is high can the state of the latch change.

c. D (Data) Latch or Transparent Latch is an improvement of the gated SR latch because it prevents the problem when both
inputs are logic 1.
o When the D latch’s enable input is high, the Q output will always reflect the logic level, which is present at the D input.
o When the D latch’s input falls to logic 0, the latch is disabled or "closed", and the Q output retains its last value
independent of the D input.

d. JK (Jack Kilby) Latch is similar to SR latch except with 11 input; an SR latch does nothing, while a JK latch toggles. Due to this
additional enable input, a JK flip-flop has four possible input combinations: “logic 1”, “logic 0”, “no change”, and “toggle”.

e. T (Toggle) Latch is formed when the inputs of the JK latch are shorted. This specifically happens when the input is high, then
the output toggles.

• Flip-Flops are also building blocks of sequential circuits that are made up of latch circuitry. Their content change only either at the
rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge
of the clock, the flip-flop content remains constant even if the input changes.
Types of Flip-Flops:
a. SR (Set-Reset) Flip-Flop is the basic flip-flop consists of two AND gates and a basic NOR flip-flop. This flip-flop is used in control
circuits.
o The outputs of the two AND gates remain at 0 as long as the clock pulse is 0, irrespective of S and R’s input values.
o When the clock pulse is 1, the SR flip-flop changes its contents, which means zero to one or one to zero.
o When S = R = 1, it causes both the outputs to go to 0 because of a clock pulse.
o When the clock pulse is removed, the state of the flip-flop is unstated.

b. D (Data) Flip-Flop is the modification of the SR flip-flop where the input D goes directly into the input S. The complement of
the input D goes to the input R. This flip-flop is used in counters and shift registers for data transfer application.
o The D input is sampled during the existence of a clock pulse. Whenever the clock signal is low and if the input changes at
other times, the output will be unaffected.
o The clock has to be high for the inputs to get active. Meaning, the change of state of the output is dependent on the
rising edge of the clock. The output (Q) is the same as the input.

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c. JK (Jack Kilby) Flip-Flop augments the SR flip-flop behavior where J = Set and K = Reset. It improves the SR flip-flop since the
output state of the input condition, J = K = 1, is inverted. To synthesize a D flip-flop, set K equal to J’s complement (input J will
act as input D). Similarly, to synthesize a T flip-flop set K equal to J. Therefore, the JK flip-flop is universal because it can be
configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
o If J and K data input are both low, then no change occurs.
o If J and K data input are different (i.e., high and low), then the output Q takes t J’s value at the next clock edge.
o If J and K are both high at the clock edge, then the output will toggle from one state to another.

d. T (Toggle) Flip-Flop is called a single input version of the JK flip-flop since both the J and K inputs are connected. This flip-flop
has only one input along with the clock input and is used in the frequency division circuit. It acts as a digital toggle switch as
well.
o Whenever the clock signal is low, the input is never going to affect the output state.
o The clock has to be high for the inputs to get active.

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References:
Karim, M., & Chen, X. (2017). Digital design: Basic concepts and principles. Boca Raton, FL: CRC Press/Taylor & Francis
LaMeres, B. (2019). Introduction to logic circuits & logic design with VHDL (1st ed.). Springer International
Ndjountche, T. (2016). Digital electronics 2: Sequential and arithmetic logic circuits. John Wiley & Sons

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