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Semiconductor and Programmable Logic Device

This document provides an outline for a presentation on semiconductor memories and programmable logic devices. It discusses memory organization and operation, types of memory including ROM, RAM, flash memory and CAM. It also covers topics like programmable logic array, programmable array logic, complex programmable logic devices and field programmable gate arrays.

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367 views35 pages

Semiconductor and Programmable Logic Device

This document provides an outline for a presentation on semiconductor memories and programmable logic devices. It discusses memory organization and operation, types of memory including ROM, RAM, flash memory and CAM. It also covers topics like programmable logic array, programmable array logic, complex programmable logic devices and field programmable gate arrays.

Uploaded by

THE PAINKILLERS
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer Engineering Department

Digital Fundamentals (3130704)


Unit 5
Semi conductor memories and Programmable logic device

Presented By
Prof. Nirali Kapadia

GANDHINAGAR INSTITUTE OF TECHNOLGY


Outline

• Memory organization and operation


• Types of Memory
• Memory Chips
• Programmable logic array
• Programmable logic devices
• Field Programmable Gate Array
Memory organization and operation
• The number of inputs required to store the data into or read the data from any memory
location is N.
• One set of N lines is required for storing the data into the memory, referred to as data
inputs and another set of N lines is required for reading the data already stored in the
memory, which is referred to as data outputs.
• The concept of bus is used to refer to a group of conductors carrying related set of signals.
• Therefore, the set of lines meant for data inputs is input data bus and for data outputs is
output data bus.
• Input and output data buses are unidirectional, i.e. the data can flow in one direction only.
Memory organization and operation
• In most of the memory chips available, the same set of lines is used for data input as
well as data output and is referred to as bidirectional bus.
• It is used as input bus for some
• specific time and as output bus for some other time depending upon a Read/Write control
input
• A number of control inputs are required to give commands to the device to perform the
desired operation.
• For example, a command signal is required to tell the memory whether a read or a write
(R/W in figure) operation is desired.
• When R/W is HIGH, the data bus will be used for reading the memory (output bus)
whereas when R/W is LOW, the bus will be acting in the input direction and the data on
the bus will go into the memory
Memory organization and operation
There are mainly two types of operations performed by memory unit.
Write operation
The chip select signal is applied to the CS terminal.
The word to be stored is applied to the data-input terminal.
The address of the desired memory location is applied to the address-input terminals.
A write command signal is applied to the write control input terminal with R/W = 0.
•
Read operation
The chip select signal is applied to the CS terminal.
Theaddressofthedesiredmemorylocationisappliedtotheaddress-inputterminals.
A read command signal is applied to the read control input terminal with R/W = 1.
Memory organization and operation

Fig. 1 Block diagram of Memory


Memory organization and operation
• The no of inputs required to store the data into or read the data from
any memory locations in N.
• For this, we have data inputs and data outputs. If separate lines are
used it is unidirectional and if there are separate lines then there is
bidirectional bus.
• Data bus is time multiplexed. It is used as input bus for some specific
time and as output bus for some specific time.
Memory organization and operation
• A no of control inputs are required to give commands to the device to
perform the desired operation. Example : A command signal is
required to tell the memory whether a read or a write operation is
desired.
• If High then Read, if Low the write operation.
Fig. 2 Block diagram of Memory with bidirectional data bus
Fig. 3 Internal organization of 16 X 4 Memory Chip
Expanding Memory Size
• In main memory application the required memory capacity cannot be satisfied by a single
available memory IC chip.
• Example: Obtain a 16X8 memory using 16x4 memory ICs
• N = 4 n =8
• n/N = 2 . So 2 chips are required.
Classification and characteristics of Memories
• Memories can be classified according to their principle of operation.
• ROM
• Read and write memories (RWM or RAM)
• Flash memory
• Content addressable memory (CAM)
• First - in – first – out memory
ROM
• Reading the information from it. It is used to store the information which is fixed, such as
tables for various functions, fixed data and instructions.
• A read-only memory (ROM) is a sem iconductor memory device used to store
information which is permanent in nature.
• It has become an important part of many digital systems because of its low cost,
high speed, system-design flexibility and data non-volatility.
ROM
• The read-only memory has a variety of applications in digital systems, such as
implementation of combinational logic and sequential logic, character generation,
look-up table, microprocessor program storage, etc.
• ROMS are well-suited for LSI manufacturing processes and are available in many forms.
•
• Two major semiconductor technologies are used for the manufacturing of ROM
integrated circuits, v iz. bipolar techno logy and MOS technology, which differ primarily
in access time.
Content Addressable Memory(CAM)
• It is a special purpose RAM that can be accessed by searching for data content.
• For this purpose, it is addressed by associating the i/p data, referred to as key,
simultaneously with all the stored words and produces o/p signals to indicate the match
conditions between the key and stored words.
• This operation is referred to as association or interrogation and this type of memory is
also known as associative memory.
Fig. 4 Block diagram of CMM
Charged Coupled device Memory(CCD)
The charge-coupled device (CCD) memory is a type of dynamic memory, in which
packets of charges (electrons) are continuously transferred from one MOS device to
another.
The structure of a single MOS device is quite simple and is shown in figure.

When a high voltage is applied to the metal gate, holes are repelled from a region
beneath the gate in the P-type substrate.
This region called a potential well is then capable of accepting a packet of negative
charges.
Charged Coupled device Memory(CCD)
Data in the form of charge is transferred from one device to an
adjacent one by clocking their gates.
The CCD memory is inherently serial. Practical memories are
constructed in the form of shift registers, each shift register being a
line of CCOs.
Charged Coupled device Memory(CCD)
• By controlling the timing of the clock signals applied to the shift registers, data can be
accessed one bit at a time from a single register or several bits at a time from multiple
registers.
• The principle advantage of the ccd memory is that, its single cell structure makes it
• possible to construct large capacity memor ies at low cost.
• On the other hand. like other dynamic memories, it must be periodically refreshed and
driven by rather complex, multi-phase clock signals.
• Since data are stored serially, the average access time is long compared with the
semiconductor RAM memory.
ROM as PLD
• The information is embedded in the ROM, in the form of bits, by a process known as
programming the ROM .
• Here, programming is used to refer to the hardware procedure which specifies the bits that
are going to be inserted in the hardware configuration of the device . And this is what
makes ROM a Programmable Logic Device (PLD) .
ROM as PLD
• A Programmable Logic Device (PLD) is an IC (Integrated Circuit) with internal logic
gates connected through electronic paths that behave similar to fuses . In the original
state, all the fuses are intact, but when we program these devices, we blow away certain
fuses along the paths that must be removed to achieve a particular configuration. And this
is what happens in ROM, ROM consists of nothing but basic logic gates arranged in such
a way that they store the specified bits.
• Typically, a PLD can have hundreds to millions of gates interconnected through hundreds
to thousands of internal paths . In order to show the internal logic diagram of such a
device a special symbology is used, as shown below
Programmable Logic Array
Programmable Logic Array
• PLA is used for the implementation of various combinational circuits using a buffer, AND
gate and OR gate. In PLA, all the minterms are not realized but only required minterms
are implemented. As PLA has programmable AND gate array and programmable OR gate
array, it provides more flexibility but the disadvantage is, it is not easy to use.
• Applications:
• PLA is used to provide control over datapath.
• PLA is used as a counter.
• PLA is used as a decoder.
• PLA is used as a BUS interface in programmed I/O.
Programmable Array Logic
•
• Programmable array logic (a registered trade mark of Monolithic Memories) is a
particular family of programmable logic devices (PLDs) that is widely used and
available from a number of manufacturers.
• The PAL circuits consist of a set of AND gates whose inputs can be programmed and
whose outputs are connected to an OR gate, i.e. the inputs to the OR gate are hard-
wired, i.e. PAL is a PLD with a fixed OR array and a programmablele AND array.
• Because only the AND gates are programmable, the PAL is easier to program but is not as
flexible as the PLA.
Complex Programmable Logic Device

• The simple programmable logic devices (SPLDs), such as PALs, EEPLDs, and GALs
etc. have limited number of inputs, product terms, and outputs.
• These devices, therefore, can support up to about 32 total number of inputs and outputs
• only.
• For implementation of circuits that require more inputs and outputs than that are
availab le in a single SPLD chip,either multiple SPLD chips can be employed or
more sophisticated type of chip, referred to as complex programmable logic device
(CPLD) can be used.
Complex Programmable Logic Device
•• The expansion of PLD using multiple SPLD chips have the following disadvantages:
• PC board area requirement increases with the number of chips.
THANK YOU

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