ARM® Developer Suite Assembler Guide Chapter 4.

ARM Instruction Reference 11/1/17 10&55 ARM® Developer Suite Assembler Guide Chapter 4. ARM Instruction Reference 11/1/17 10&55

MAR Move from registers to 40-bit MAR, MRA XScale[3]

ARM® Developer Suite Assembler Guide Version 1.2 accumulator

MCR, MCR2, MCRR Move from register(s) to MCR, MCR2, MCRR 2, 5, 5E[4]
Chapter 4. ARM Instruction Reference
coprocessor
This chapter describes the ARM instructions that are supported by the ARM assembler. It contains the
following sections: MIA, MIAPH, Multiply with internal 40-bit MIA, MIAPH, and MIAxy XScale
Conditional execution MIAxy accumulate
ARM memory access instructions MLA Multiply accumulate MUL and MLA 2
ARM general data processing instructions
ARM multiply instructions MOV Move MOV and MVN All
ARM saturating arithmetic instructions MRA Move from 40-bit accumulator to MAR, MRA XScale
ARM branch instructions registers
ARM coprocessor instructions
MRC, MRC2 Move from coprocessor to register MRC, MRC2 2, 5
Miscellaneous ARM instructions
ARM pseudo-instructions. MRRC Move from coprocessor to 2 MRRC 5Ed
registers
See to Table 4.1 to locate individual instructions. Pseudo-instructions are listed on ARM pseudo-
instructions. MRS Move from PSR to register MRS 3
Table 4.1. Location of ARM instructions
MSR Move from register to PSR MSR 3
Mnemonic Brief description Page Architecture[1]
MUL Multiply MUL and MLA 2
ADC, ADD Add with carry, Add ADD, SUB, RSB, ADC, All
MVN Move not MOV and MVN All
SBC, and RSC
ORR Logical OR AND, ORR, EOR, and BIC All
AND Logical AND AND, ORR, EOR, and BIC All
PLD Cache preload PLD 5Ed
B Branch B and BL All

BIC Bit clear AND, ORR, EOR, and BIC All QADD, QDADD, Saturating arithmetic QADD, QSUB, QDADD, 5ExP[5]
QDSUB, QSUB and QDSUB
BKPT Breakpoint BKPT 5
RSB, RSC, SBC Reverse sub, Reverse sub with ADD, SUB, RSB, ADC, All
BL Branch with link B and BL All carry, Sub with carry SBC, and RSC

BLX Branch, link and exchange BLX 5T[2] SMLAL Signed multiply-accumulate (64 <= UMULL, UMLAL, SMULL M[6]
32 x 32 + 64) and SMLAL
BX Branch and exchange BX 4Tb
SMLALxy Signed multiply-accumulate (64 <= SMLALxy 5ExPe
CDP, CDP2 Coprocessor data operation CDP, CDP2 2, 5 16 x 16 + 64)

CLZ Count leading zeroes CLZ 5

SMLAWy Signed multiply-accumulate (32 <= SMLAWy 5ExPe
32 x 16 + 32)
CMN, CMP Compare negative, Compare CMP and CMN All
SMLAxy Signed multiply-accumulate (32 <= SMLAxy 5ExPe
EOR Exclusive OR AND, ORR, EOR, and BIC All 16 x 16 + 32)

LDC, LDC2 Load coprocessor LDC, STC 2, 5 SMULL Signed multiply (64 <= 32 x 32) UMULL, UMLAL, SMULL Mf
and SMLAL
LDM Load multiple registers LDM and STM All
SMULWy Signed multiply (32 <= 32 x 16) SMULWy 5ExPe
LDR Load register ARM memory access All
instructions SMULxy Signed multiply (32 <= 16 x 16) SMULxy 5ExPe

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ARM® Developer Suite Assembler Guide Chapter 4. ARM Instruction Reference 11/1/17 10&55 ARM® Developer Suite Assembler Guide 4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC 11/1/17 11%00

STC, STC2 Store coprocessor LDC, STC 2, 5ExPe

ARM® Developer Suite Assembler Guide Version 1.2
STM Store multiple registers LDM and STM All

4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC

STR Store register ARM memory access All
instructions Add, subtract, and reverse subtract, each with or without carry.

SUB Subtract ADD, SUB, RSB, ADC, All Syntax

SBC, and RSC op{cond}{S} Rd, Rn, Operand2

SWI Software interrupt SWI All where:

op
SWP Swap registers and memory SWP 3
is one of ADD, SUB, RSB, ADC, SBC,or RSC.
TEQ, TST Test equivalence, Test TST and TEQ All cond
UMLAL, UMULL Unsigned MLA, MUL (64 <= 32 x 32 UMULL, UMLAL, SMULL Mf is an optional condition code (see Conditional execution).
(+ 64)) and SMLAL S
is an optional suffix. If S is specified, the condition code flags are updated on the result of the
[1] n : available in ARM architecture version n and above operation (see Conditional execution).

[2] nT : available in T variants of ARM architecture version n and above Rd

is the ARM register for the result.
[3] XScale: XScale coprocessor instructions
Rn
[4] nE : available in E variants of ARM architecture version n and above, except ExP variants is the ARM register holding the first operand.

[5] nE : available in all E variants of ARM architecture version n and above, including ExP variants Operand2
is a flexible second operand. See Flexible second operand for details of the options.
[6] M : available in ARM architecture version 3M, and 4 and above, except xM versions

Usage
The ADD instruction adds the values in Rn and Operand2.
Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
The SUB instruction subtracts the value of Operand2 from the value in Rn.
Non-Confidential
The RSB (Reverse SuBtract) instruction subtracts the value in Rn from the value of Operand2. This is
useful because of the wide range of options for Operand2.

ADC, SBC, and RSC are used to synthesize multiword arithmetic (see Multiword arithmetic examples).

The ADC (ADd with Carry) instruction adds the values in Rn and Operand2, together with the carry flag.

The SBC (SuBtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the
carry flag is clear, the result is reduced by one.

The RSC (Reverse Subtract with Carry) instruction subtracts the value in Rn from the value of Operand2.
If the carry flag is clear, the result is reduced by one.

In certain circumstances, the assembler can substitute one instruction for another. Be aware of this
when reading disassembly listings. See Instruction substitution for details.

Condition flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.

Use of r15
If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

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ARM® Developer Suite Assembler Guide 4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC 11/1/17 11%00 ARM® Developer Suite Assembler Guide 4.3.3. AND, ORR, EOR, and BIC 11/1/17 11%00

Execution branches to the address corresponding to the result.

If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to ARM® Developer Suite Assembler Guide Version 1.2
return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer
Guide).
4.3.3. AND, ORR, EOR, and BIC
Caution
Logical AND, OR, Exclusive OR and Bit Clear.
Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an
instruction is unpredictable, but the assembler cannot warn you at assembly time.
Syntax
You cannot use r15 for Rd or any operand in any data processing instruction that has a register- op{cond}{S} Rd, Rn, Operand2
controlled shift (see Flexible second operand).
where:
Architectures op
These instructions are available in all versions of the ARM architecture. is one of AND, ORR, EOR,or BIC.
cond
Examples
is an optional condition code (see Conditional execution).
ADD r2,r1,r3
SUBS r8,r6,#240 ; sets the flags on the result S
RSB r4,r4,#1280 ; subtracts contents of r4 from 1280 is an optional suffix. If S is specified, the condition code flags are updated on the result of the
ADCHI r11,r0,r3 ; only executed if C flag set and Z
operation (see Conditional execution).
; flag clear
RSCLES r0,r5,r0,LSL r4 ; conditional, flags set Rd
is the ARM register for the result.
Incorrect example
Rn
RSCLES r0,r15,r0,LSL r4 ; r15 not allowed with register
; controlled shift is the ARM register holding the first operand.
Operand2
Multiword arithmetic examples is a flexible second operand. See Flexible second operand for details of the options.
These two instructions add a 64-bit integer contained in r2 and r3 to another 64-bit integer contained
in r0 and r1, and place the result in r4 and r5. Usage
ADDS r4,r0,r2 ; adding the least significant words The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values
ADC r5,r1,r3 ; adding the most significant words in Rn and Operand2.
These instructions subtract one 96-bit integer from another: The BIC (BIt Clear) instruction performs an AND operation on the bits in Rn with the complements of
the corresponding bits in the value of Operand2.
SUBS r3,r6,r9
SBCS r4,r7,r10 In certain circumstances, the assembler can substitute BIC for AND, or AND for BIC. Be aware of this
SBC r5,r8,r11 when reading disassembly listings. See Instruction substitution for details.
For clarity, the above examples use consecutive registers for multiword values. There is no
requirement to do this. The following, for example, is perfectly valid: Condition flags
SUBS r6,r6,r9
If S is specified, these instructions:
SBCS r9,r2,r1 update the N and Z flags according to the result
SBC r2,r8,r11
can update the C flag during the calculation of Operand2 (see Flexible second operand)
do not affect the V flag.
Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
Non-Confidential Use of r15
If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

Execution branches to the address corresponding to the result.
If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to
return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer
Guide).

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ARM® Developer Suite Assembler Guide 4.3.3. AND, ORR, EOR, and BIC 11/1/17 11%00 ARM® Developer Suite Assembler Guide 4.3.4. MOV and MVN 11/1/17 10&56

Caution
Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an ARM® Developer Suite Assembler Guide Version 1.2
instruction is unpredictable, but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register- 4.3.4. MOV and MVN
controlled shift (see Flexible second operand).
Move and Move Not.
Architectures
Syntax
These instructions are available in all versions of the ARM architecture.
MOV{cond}{S} Rd, Operand2

Examples MVN{cond}{S} Rd, Operand2

AND r9,r2,#0xFF00 where:
ORREQ r2,r0,r5
EORS r0,r0,r3,ROR r6 cond
BICNES r8,r10,r0,RRX is an optional condition code (see Conditional execution).

Incorrect example S

EORS r0,r15,r3,ROR r6 ; r15 not allowed with register is an optional suffix. If S isspecified, the condition code flags are updated on the result of the
; controlled shift operation (see Conditional execution).
Rd

Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B is the ARM register for the result.

Non-Confidential Operand2
is a flexible second operand. See Flexible second operand for details of the options.

Usage
The MOV instruction copies the value of Operand2 into Rd.

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value,
and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this
when reading disassembly listings. See Instruction substitution for details.

Condition flags
If S is specified, these instructions:

update the N and Z flags according to the result

can update the C flag during the calculation of Operand2 (see Flexible second operand)
do not affect the V flag.

Use of r15
If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

Execution branches to the address corresponding to the result.
If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to
return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer
Guide).

Caution
Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an
instruction is unpredictable, but the assembler cannot warn you at assembly time.

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ARM® Developer Suite Assembler Guide 4.3.4. MOV and MVN 11/1/17 10&56 ARM® Developer Suite Assembler Guide 4.3.5. CMP and CMN 8/2/17 11'03

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-
controlled shift (see Flexible second operand). ARM® Developer Suite Assembler Guide Version 1.2
Architectures
These instructions are available in all versions of the ARM architecture. 4.3.5. CMP and CMN
Compare and Compare Negative.
Examples
MOV r5,r2 Syntax
MVNNE r11,#0xF000000B CMP{cond} Rn, Operand2
MOVS r0,r0,ASR r3
CMN{cond} Rn, Operand2
Incorrect examples where:
MVN r15,r3,ASR r0 ; r15 not allowed with register
; controlled shift cond
is an optional condition code (see Conditional execution).

Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B Rn

Non-Confidential is the ARM register holding the first operand.

Operand2
is a flexible second operand. See Flexible second operand for details of theoptions.

Usage
These instructions compare the value in a register with Operand2. They update the condition flags on
the result, but do not place the result in any register.

The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS
instruction, except that the result is discarded.

In certain circumstances, the assembler can substitute CMN for CMP, or CMP for CMN. Be aware of this
when reading disassembly listings. See Instruction substitution for details.

Condition flags
These instructions update the N, Z, C and V flags according to the result.

Use of r15
If you use r15 as Rn, the value used is the address of the instruction plus 8.

You cannot use r15 for any operand in any data processing instruction that has a register-controlled
shift (see Flexible second operand).

Architectures
These instructions are available in all versions of the ARM architecture.

Examples
CMP r2,r9
CMN r0,#6400
CMPGT r13,r7,LSL #2

Incorrect example
CMP r2,r15,ASR r0 ; r15 not allowed with register
; controlled shift

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ARM® Developer Suite Assembler Guide 4.3.6. TST and TEQ 8/2/17 11'02 ARM® Developer Suite Assembler Guide 4.3.6. TST and TEQ 8/2/17 11'03

TEQ r15,r1,ROR r0 ; r15 not allowed with register

ARM® Developer Suite Assembler Guide Version 1.2 ; controlled shift

Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.3.6. TST and TEQ
Non-Confidential
Test and Test Equivalence.

Syntax
TST{cond} Rn, Operand2

TEQ{cond} Rn, Operand2

where:
cond
is an optional condition code (see Conditional execution).
Rn
is the ARM register holding the first operand.
Operand2
is a flexible second operand. See Flexible second operand for details of theoptions.

Usage
These instructions test the value in a register against Operand2. They update the condition flags on the
result, but do not place the result in any register.

The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2.
This is the same as a ANDS instruction, except that the result is discarded.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of
Operand2. This is the same as a EORS instruction, except that the result is discarded.

Condition flags
These instructions:

update the N and Z flags according to the result

can update the C flag during the calculation of Operand2 (see Flexible second operand)
do not affect the V flag.

Use of r15
If you use r15 as Rn, the value used is the address of the instruction plus 8.

You cannot use r15 for any operand in any data processing instruction that has a register-controlled
shift (see Flexible second operand).

Architectures
These instructions are available in all versions of the ARM architecture.

Examples
TST r0,#0x3F8
TEQEQ r10,r9
TSTNE r1,r5,ASR r1

Incorrect example

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ARM® Developer Suite Assembler Guide 4.2.1. LDR and STR, words and unsigned bytes 11/1/17 10&53 ARM® Developer Suite Assembler Guide 4.2.1. LDR and STR, words and unsigned bytes 11/1/17 10&53

more information.
ARM® Developer Suite Assembler Guide Version 1.2 label must be within ±4KB of the current instruction.
!

4.2.1. LDR and STR, words and unsigned bytes is an optional suffix. If ! is present, the address including the offset is written back into Rn. You
cannot use the ! suffix if Rn is r15.
Load register and store register, 32-bit word or 8-bit unsigned byte. Byte loads are zero-extended to
32 bits.
Zero offset
Syntax The value in Rn is used as the address for the transfer.
Both LDR and STR have four possible forms:
Pre-indexed offset
zero offset
The offset is applied to the value in Rn before the data transfer takes place. The result is used as the
pre-indexed offset memory address for the transfer. If the ! suffix is used, the result is written back into Rn. Rn must not
program-relative be r15 if the !suffix is used.
post-indexed offset.
Program-relative
The syntax of the four forms, in the same order, are:
This is an alternative version of the pre-indexed form. The assembler calculates the offset from the PC
op{cond}{B}{T} Rd, [Rn] for you, and generates a pre-indexed instruction with the PC as Rn.
op{cond}{B} Rd, [Rn, FlexOffset]{!} You cannot use the ! suffix.
op{cond}{B} Rd, label
Post-indexed offset
op{cond}{B}{T} Rd, [Rn], FlexOffset
The value in Rn is used as the memory address for the transfer. The offset is applied to the value in Rn
where: after the data transfer takes place. The result is written back into Rn. Rn must not be r15.

op
Flexible offset syntax
is either LDR (Load Register)or STR (Store Register).
Both pre-indexed and post-indexed offsets can be either of the following:
cond
#expr
is an optional condition code (see Conditional execution).
{-}Rm{, shift}
B
is an optional suffix. If B is present, the least significant byte of Rd is transferred. If op is LDR, the where:
other bytes of Rd are cleared. -
Otherwise, a 32-bit word is transferred. is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset
T is added to Rn.
is an optional suffix. If T is present, the memory system treats the access as though the expr
processor was in User mode, even if it is in a privileged mode (see Processor mode). T has no is an expression evaluating to an integer in the range –4095 to +4095. This is often a numeric
effect in User mode. You cannot use T with a pre-indexed offset. constant (see examples below).
Rd Rm
is the ARM register to load or save. is a register containing a value to be used as the offset. Rm must not be r15.
Rn shift
is the register on which the memory address is based. is an optional shift to be applied to Rm. It can be any one of:
Rn must not be the same as Rd, if the instruction:
ASR n
is pre-indexed with writeback (the ! suffix) arithmetic shift right n bits. 1 = n = 32.
is post-indexed LSL n
uses the T suffix. logical shift left n bits. 0 = n = 31.
FlexOffset LSR n
is a flexible offset applied to the value in Rn (see Flexible offset syntax). logical shift right n bits. 1 = n = 32.
label ROR n
is a program-relative expression. See Register-relative and program-relative expressions for rotate right n bits. 1 = n = 31.

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ARM® Developer Suite Assembler Guide 4.2.1. LDR and STR, words and unsigned bytes 11/1/17 10&53 ARM® Developer Suite Assembler Guide 4.2.1. LDR and STR, words and unsigned bytes 11/1/17 10&53

RRX These instructions are available in all versions of the ARM architecture.
rotate right one bit, with extend.
In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb
instructions if bit[0] of the value loaded is set.
Address alignment for word transfers
In most circumstances, you must ensure that addresses for 32-bit transfers are 32-bit word-aligned. Examples
If your system has a system coprocessor (cp15), you can enable alignment checking. Non word- LDR r8,[r10] ; loads r8 from the address in r10.
LDRNE r2,[r5,#960]! ; (conditionally) loads r2 from a word
aligned 32-bit transfers cause an alignment exception if alignment checking is enabled.
; 960 bytes above the address in r5, and
If your system does not have a system coprocessor (cp15), or alignment checking is disabled: ; increments r5 by 960.
STR r2,[r9,#consta-struc] ; consta-struc is an expression evaluating
For STR, the specified address is rounded down to a multiple of four. ; to a constant in the range 0-4095.
STRB r0,[r3,-r8,ASR #2] ; stores the least significant byte from
For LDR:
; r0 to a byte at an address equal to
1. The specified address is rounded down to a multiple of four. ; contents(r3) minus contents(r8)/4.
; r3 and r8 are not altered.
2. Four bytes of data are loaded from the resulting address.
STR r5,[r7],#-8 ; stores a word from r5 to the address
3. The loaded data is rotated right by one, two or three bytes according to bits [1:0] of the ; in r7, and then decrements r7 by 8.
address. LDR r0,localdata ; loads a word located at label localdata
For a little-endian memory system, this causes the addressed byte to occupy the least significant
byte of the register.
Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
For a big-endian memory system, it causes the addressed byte to occupy:
Non-Confidential
bits[31:24] if bit[0] of the address is 0
bits[15:8] if bit[0] of the address is 1.

Loading to r15
A load to r15 (the program counter) causes a branch to the instruction at the address loaded.
Bits[1:0] of the value loaded:
are ignored in ARM architecture v3 and below
must be zero in ARM architecture v4.
In ARM architecture v5 and above:
bits[1:0] of a value loaded to r15 must not have the value 0b10
if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.
You cannot use the B or T suffixes when loading to r15.

Saving from r15

In general, avoid saving from r15 if possible.
If you do save from r15, the value saved is the address of the current instruction, plus an
implementation-defined constant. The constant is always the same for a particular processor.

If your assembled code might be used on different processors, you can find out what the constant is at
runtime using code like the following:
SUB R1, PC, #4 ; R1 = address of following STR instruction
STR PC, [R0] ; Store address of STR instruction + offset,
LDR R0, [R0] ; then reload it
SUB R0, R0, R1 ; Calculate the offset as the difference

If your code is to be assembled for a particular processor, the value of the constant is available in
armasm as {PCSTOREOFFSET}.

Architectures

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ARM® Developer Suite Assembler Guide 4.6.1. B and BL 11/1/17 10&58 ARM® Developer Suite Assembler Guide 4.6.2. BX 11/1/17 10&58

ARM® Developer Suite Assembler Guide Version 1.2 ARM® Developer Suite Assembler Guide Version 1.2

4.6.1. B and BL 4.6.2. BX

Branch, and Branch with Link. Branch, and optionally exchange instruction set.

Syntax Syntax
B{cond} label BX{cond} Rm

BL{cond} label where:

where: cond

cond is an optional condition code (see Conditional execution).

is an optional condition code (see Conditional execution). Rm

label is an ARM register containing the address to branchto.

is a program-relative expression. See Register-relative and program-relative expressions for Bit 0 of Rm is not used as part of the address.
more information. If bit 0 of Rm is set, the instruction sets the T flag in the CPSR, and the code at the destination is
interpreted as Thumb code.
Usage If bit 0 of Rm is clear, bit 1 must not be set.
The B instruction causes a branchto label.
Usage
The BL instruction copies the address of the next instruction into r14 (lr, the link register), and causes
a branch to label. The BX instruction causes a branch to the address held in Rm, and changes instruction set to Thumb if
bit 0 of Rm is set.
Machine-level B and BL instructions have a range of ±32Mb from the address of the current instruction.
However, you can use these instructions even if label is out of range. Often you do not know where Architectures
label is placed by the linker. When necessary, the ARM linker adds code to allow longer branches (see
The ARM linker chapter in ADS Linker and Utilities Guide). The added code is called a veneer. This instruction is available in all T variants of the ARM architecture, and ARM architecture v5 and
above.
Architectures
Examples
These instructions are available in all versions of the ARM architecture.
BX r7
BXVS r0
Examples
B loopA
BLE ng+8 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
BL subC
Non-Confidential
BLLT rtX

Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
Non-Confidential

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ARM® Developer Suite Assembler Guide 4.4.1. MUL and MLA 8/2/17 11'51 ARM® Developer Suite Assembler Guide 4.4.1. MUL and MLA 8/2/17 11'51

MUL r15,r0,r3 ; use of r15 not allowed

ARM® Developer Suite Assembler Guide Version 1.2 MLA r1,r1,r6 ; Rd cannot be the same as Rm

Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.4.1. MUL and MLA
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Multiply and multiply-accumulate (32-bit by 32-bit, bottom 32-bit result).

Syntax
MUL{cond}{S} Rd, Rm, Rs

MLA{cond}{S} Rd, Rm, Rs, Rn

where:
cond
is an optional condition code (see Conditional execution).
S
is an optional suffix. If S isspecified, the condition code flags are updated on the result of the
operation (see Conditional execution).
Rd
is the ARM register for the result.
Rm, Rs, Rn
are ARM registers holding the operands.

r15 cannot be used for any of Rd, Rm, Rs, or Rn.

Rd cannot be the same as Rm.

Usage
The MUL instruction multiplies the values from Rm and Rs, and places the least significant 32 bits of the
result in Rd.

The MLA instruction multiplies the values from Rm and Rs, adds the value from Rn, and places the least
significant 32 bits of the result in Rd.

Condition flags
If S is specified, these instructions:
update the N and Z flags according to the result
do not affect the V flag
corrupt the C flag in ARM architecture v4 and earlier
do not affect the C flag in ARM architecture v5 and later.

Architectures
These instructions are available in ARM architecture v2 and above.

Examples
MUL r10,r2,r5
MLA r10,r2,r1,r5
MULS r0,r2,r2
MULLT r2,r3,r2
MLAVCS r8,r6,r3,r8

Incorrect examples

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ARM® Developer Suite Assembler Guide 4.1. Conditional execution 8/2/17 11'06 ARM® Developer Suite Assembler Guide 2.5.2. Execution conditions 8/2/17 11'07

Examples
ARM® Developer Suite Assembler Guide Version 1.2 ADD r0, r1, r2 ; r0 = r1 + r2, don't update flags
ADDS r0, r1, r2 ; r0 = r1 + r2, and update flags
ADDCSS r0, r1, r2 ; If C flag set then r0 = r1 + r2, and update flags
4.1. Conditional execution CMP r0, r1 ; update flags based on r0-r1.

Almost all ARM instructions can include an optional condition code. This is shown in syntax descriptions
as {cond}. An instruction with a condition code is only executed if the condition code flags in the CPSR Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
meet the specified condition. The condition codes that you can use are shown in Table 4.2.
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Table 4.2. ARM condition codes

Suffix Flags Meaning

EQ Z set Equal

NE Z clear Not equal

CS/HS C set Higher or same (unsigned >= )

CC/LO C clear Lower (unsigned < )

MI N set Negative

PL N clear Positive or zero

VS V set Overflow

VC V clear No overflow

HI C set and Z clear Higher (unsigned <= )

LS C clear or Z set Lower or same (unsigned <= )

GE N and V the same Signed >=

LT N and V different Signed <

GT Z clear, and N and V the same Signed >

LE Z set, or N and V different Signed <=

AL Any Always (usually omitted)

Almost all ARM data processing instructions can optionally update the condition code flags according to
the result. To make an instruction update the flags, include the S suffix as shown in the syntax
description for the instruction.

Some instructions (CMP, CMN, TST and TEQ) do not require the S suffix. Their only function is to update
the flags. They always update the flags.

Flags are preserved until updated. A conditional instruction which is not executed has no effect on the
flags.

Some instructions update a subset of the flags. The other flags are unchanged by these instructions.
Details are specified in the descriptions of the instructions.

You can execute an instruction conditionally, based upon the flags set in another instruction, either:
immediately after the instruction which updated the flags
after any number of intervening instructions that have not updated the flags.

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ARM® Developer Suite Assembler Guide 4.3.1. Flexible second operand 8/2/17 11'22 ARM® Developer Suite Assembler Guide 4.3.1. Flexible second operand 8/2/17 11'22

register.
ARM® Developer Suite Assembler Guide Version 1.2
LSR and LSL
Logical shift right by n bits divides the value contained in Rm by 2n, if the contents are regarded as an
4.3.1. Flexible second operand unsigned integer. The left-hand n bits of the register are set to 0.
Most ARM general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction. Logical shift left by n bits multiplies the value contained in Rm by 2n, if the contents are regarded as an
unsigned integer. Overflow may occur without warning. The right-hand n bits of the register are set to
Syntax 0.

Operand2 has two possible forms:

ROR
#immed_8r Rotate right by n bits moves the right-hand n bits of the register into the left-hand n bits of the result.
Rm{, shift} At the same time, all other bits are moved right by n bits (see Figure 4.1).

where: Figure 4.1. ROR

immed_8r
Carry
is an expression evaluating to a numeric constant.The constant must correspond to an 8-bit Flag
pattern rotated by an even number of bits within a 32-bit word (but see Instruction
substitution). 31 1 0
Rm
is the ARM register holding the data for the second operand. The bit pattern in the register can ...
be shifted or rotated in various ways.
shift RRX
is an optional shift to be applied to Rm. It can be any one of: Rotate right with extend shifts the contents of Rm right by one bit. The carry flag is copied into bit[31]
ASR n of Rm (see Figure 4.2).
arithmetic shift right n bits. 1 = n = 32. The old value of bit[0] of Rm is shifted out to the carry flag if the S suffix is specified (see The carry
LSL n flag).
logical shift left n bits. 0 = n = 31.
Figure 4.2. RRX
LSR n
Carry
logical shift right n bits. 1 = n = 32. 31 30 1 0 Flag
ROR n
rotate right n bits. 1 = n = 31.
RRX ... ...
rotate right one bit, with extend.
type Rs
The carry flag
where:
The carry flag is updated to the last bit shifted out of Rm, if the instruction is any one of the following:
type
MOV, MVN, AND, ORR, EOR or BIC, if you use the S suffix
is one of ASR, LSL, LSR, ROR.
TEQ or TST, for which no S suffix is required.
Rs
is an ARM register supplying the shift amount. Only the least significant byte is Instruction substitution
used.
Certain pairs of instructions (ADD and SUB, ADC and SBC, AND and BIC, MOV and MVN, CMP and CMN) are
Note equivalent except for the negation or logical inversion of immed_8r.
The result of the shift operation is used as Operand2 in the instruction, but Rm itself is not If a value of immed_8r cannot be expressed as a rotated 8-bit pattern, but its logical inverse or
altered. negation could be, the assembler substitutes the other instruction of the pair and inverts or negates
immed_8r.
ASR
Be aware of this when comparing disassembly listings with source code.
Arithmetic shift right by n bits divides the value contained in Rm by 2n, if the contents are regarded as
a two’s complement signed integer. The original bit[31] is copied into the left-hand n bits of the

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ARM® Developer Suite Assembler Guide 4.3.1. Flexible second operand 8/2/17 11'22

Examples
ADD r3,r7,#1020 ; immed_8r. 1020 is 0xFF rotated right by 30 bits.
AND r0,r5,r2 ; r2 contains the data for Operand2.
SUB r11,r12,r3,ASR #5 ; Operand2 is the contents of r3 divided by 32.
MOVS r4,r4, LSR #32 ; Updates the C flag to r4 bit 31. Clears r4 to 0.

Incorrect examples
ADD r3,r7,#1023 ; 1023 (0x3FF) is not a rotated 8-bit pattern.
SUB r11,r12,r3,LSL #32 ; #32 is out of range for LSL.
MOVS r4,r4,RRX #3 ; Do not specify a shift amount for RRX. RRX is
; always a one-bit shift.

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