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Lab 3 Two Stage Amplifier: MOS Characterization

This document describes a lab experiment on characterizing a two-stage amplifier, including simulating the circuit using HSPICE, measuring the gain, bandwidth, and slew rate, and observing the effects of adding compensation elements like capacitors and resistors. The goal is to analyze the stability and frequency response of the two-stage amplifier design by simulating different configurations and component values. Procedures include simulating the basic two-stage amplifier, connecting it as a buffer, adding compensation, and measuring metrics like common mode range and output voltage swing.

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Christian Allan Lumakin
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99 views25 pages

Lab 3 Two Stage Amplifier: MOS Characterization

This document describes a lab experiment on characterizing a two-stage amplifier, including simulating the circuit using HSPICE, measuring the gain, bandwidth, and slew rate, and observing the effects of adding compensation elements like capacitors and resistors. The goal is to analyze the stability and frequency response of the two-stage amplifier design by simulating different configurations and component values. Procedures include simulating the basic two-stage amplifier, connecting it as a buffer, adding compensation, and measuring metrics like common mode range and output voltage swing.

Uploaded by

Christian Allan Lumakin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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MOS Characterization

Lab 3 Two Stage Amplifier

A Laboratory Report Presented to


Prof. Aileen Caberos-Gumera
Faculty, DEET
College of Engineering and Technology, MSU-IIT

Submitted By:
Christian Allan G. Lumakin

In Partial Fulfillment for the course


ECE 130 - Introduction to Analog Integrated Circuit Design

INTRODUCTION
Amplifiers are very necessary element in any project dealing with signal strength
and quality. The two-stage amplifier circuit comprises of two stages each of which
perform amplification on the incoming signals and output finally obtained at the end of
2nd stage, two-stage operational amplifier exhibits two poles below the unity open-loop
gain.

HSPICE codes/syntax used in this experiment

.lib – Use the following syntax for library calls

.op – Compute the DC operating points

.probe – To designate the desired value to be used

.dc – DC Sweep or Parameterized Sweep for Vdd

.alter – Used to re-run simulation with a modified netlist

.end – Last statement in the input netlist file

.tran – Transient analysis with the sampling time and total time

.tf – To calculate the following small signal characteristics

.meas – Modify information and define the results of successive simulations

.ac – To specify the frequency (AC) analysis

.option – Modifies various aspects of an HSPICE simulation

PROCEDURE AND RESULTS


Step 1: Simulate Differential amplifier and Two-Stage Amplifier respectively and
compare the gain, -3dB frequency and G.B.

Circuit simulation code:

step1_TSAmp

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vin+ n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
V1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V

.op
.option post probe
.ac dec 10 10 10g
.meas ac GB when vdb(n4)=0
.probe v(n4)
.lib 'rf018.l' TT

.alter
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u
.meas ac gb when vdb(Vout)=0
.probe v(Vout)

.end

Performance Comparison of Two-Stage and Differential Amplifier


Table 1: Performance Comparison Results

Gain -3dB G.B.

Two-Stage 81dB 100kHz 50MHz

Differential Amp 41dB 100kHz 250MHz

As shown from the results above, the Two-Stage Operational Amplifier is


better than the Differential Amplifier in terms of gain, and, gain bandwidth, however,
their -3dB is of the same value.
Step 2: Connect the Two-Stage Amplifier as a unit gain buffer. Simulate it and then
observe the stability and output waveform.

Circuit simulation code:

step2_TSAmp(a)

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vout n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
V1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V

.op
.option post probe
.ac dec 10 10 10g
.meas ac GB when vdb(Vout)=0
.probe v(Vout)
.lib 'rf018.l' TT

.end
Two-Stage Amplifier as a Unit Gain Buffer

As we can see on the graph, the gain is at 0 and the phase margin is less than
0 ° , this happens when the system is unstable. The system is stable when the phase
margin is above 45 ° . The higher the phase margin, the more stable the system.
Circuit simulation code:

step2_TSAmp(b)

mn1 n4 Vinp n5 gnd nch l=1u w=5u


mn2 n3 Vout n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
Vinp Vinp gnd pwl(10ns 0.7, 10.01ns 1, 3u 1, R=10.01ns)

.op
.option post probe
.tran 1n 3u
.probe tran v(Vout) v(Vinp)
.lib 'rf018.l' TT

.end

Slew Rate Graphical Data

The slew rate graphical data of the simulation shows that the system is
unstable since the Vin is stable, but the Vout is oscillating.
Step 3: Simulate the effect of phase margin when adding compensation capacitor.

Circuit simulation code:

step3_TSAmp(a)

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vin+ n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
V1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V

.op
.option post probe
.ac dec 10 10 10g
.meas ac Gb when vdb(Vout)=0
.probe v(Vout)
.lib 'rf018.l' TT

.alter
Cc n4 Vout 2p

.end
Two-Stage Amplifier with Compensation Capacitor

Adding a compensation Capacitor gives different results, its phase margin


improved.
Step 4: Vary the value of compensation capacitor to observe the effect to phase margin
and also to observe the effect to slew rate.

Circuit simulation code:

step4_TSAmp(a)

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vin+ n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
V1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V
Cc n4 Vout 2p

.op
.option post probe
.ac dec 10 10 10g
.meas ac Gb when vdb(Vout)=0
.probe v(Vout)
.lib 'rf018.l' TT

.alter
Cc n4 Vout 4p
.alter
Cc n4 Vout 6p

.end

Two-Stage Amplifier with varying Compensation Capacitor


Circuit simulation code:

step4_TSAmp(b)

mn1 n4 Vinp n5 gnd nch l=1u w=5u


mn2 n3 Vout n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
Vinp Vinp gnd pwl(10ns 0.7, 10.01ns 1, 3u 1, R=10.01ns)
Cc n4 Vout 2p

.op
.option post probe
.tran 1n 3u
.probe tran v(Vout) v(Vinp)
.lib 'rf018.l' TT

.alter
Cc n4 Vout 4p
.alter
Cc n4 Vout 6p

.end
Slew Rate with varying Compensation Capacitor

As we see from the results from the simulations above, the bigger the value of the
compensation capacitor, the better the phase margin and also decreases the slew rate
since larger compensation capacitor needs more time to charge or discharge.
Step 5: Observe the effect after adding a compensated resistor.

Circuit simulation code:

step5_TSAmp(a)

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vin+ n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
V1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V
Cc Cc Vout 3p
Rc n4 Cc 0

.op
.option post probe
.ac dec 10 10 10g
.meas ac Gb when vdb(Vout)=0
.probe v(Vout)
.lib 'rf018.l' TT

.alter
Rc n4 Cc 1.234k
.alter
Rc n4 Cc 6k

.end
Two-Stage Amplifier with Compensation Resistor

From the simulation above, as the Rc increases the phase margin also improved.
Circuit simulation code:

TSAmp(ICMR)

mn1 n4 Vinp n5 gnd nch l=1u w=5u


mn2 n3 Vout n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
Vinp Vinp gnd pwl(10ns 0.7, 10.01ns 1, 3u 1, R=10.01ns)
Cc n4 Vout 2p

.op
.option post probe
.dc vinp 0 1.8 0.1
.probe v(Vout) v(Vinp)
.probe i(mn2)
.lib 'rf018.l' TT

.end

Input Common Mode Range (ICMR)

Step 7: Perform the FFT analysis in the circuit of figure 4.11 while changing the
value of Rs, get the frequency spectrum.
Circuit simulation code:

TSAmp(Output Voltage Swing)

mn1 n4 Vin+ n5 gnd nch l=1u w=5u


mn2 n3 Vr n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
vin- vin- gnd dc 0.9v
vin+ vin+ gnd dc 0.9v
cc vx vout 2p
ri vr vin- 0.1Meg
rf vr vout 1Meg

.op
.option post probe
.dc vin- 0v 2v 0.001v
.probe v(vout), v(vr)
.lib 'rf018.l' TT

.end

Output Voltage Swing


Circuit simulation code:

TSAmp(CMRR)

mn1 n4 Vin- n5 gnd nch l=1u w=5u


mn2 n3 Vin+ n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
v1 Vin- gnd dc 1.5V ac 1V
V2 Vin+ gnd dc 1.5V
Cc Cc Vout 2p

.op
.option post probe
.ac dec 100 10 10g
.print vdb(Vout)
.lib 'rf018.l' TT

.alter
V2 Vin+ gnd dc 1.5V ac 1v

.end

Common Mode Rejection Ratio (CMRR)


Circuit simulation code:

TSAmp(Slew Rate & Settling Time)

mn1 n4 Vinp n5 gnd nch l=1u w=5u


mn2 n3 Vout n5 gnd nch l=1u w=5u
mp3 n3 n3 vdd vdd pch l=1u w=11u
mp4 n4 n3 vdd vdd pch l=1u w=11u
mn5 n5 n6 gnd gnd nch l=1u w=10u
mn8 n6 n6 gnd gnd nch l=1u w=10u
mp6 Vout n4 vdd vdd pch l=1u w=66u
mn7 Vout n6 gnd gnd nch l=1u w=30u

Cload Vout gnd 10p


Vdd vdd gnd dc 1.8v
Iref vdd n6 25u
vinp Vinp gnd pulse(0.8v 1.0v 0n 0n 0n 400n 800n)
Cc n4 Vout 2p

.op
.option post probe
.tran 0.1n 800n
.meas tran t when v(vout)=1.5v rise=1
.meas S param='0.9/t'
.probe v(Vinp)
.lib 'rf018.l' TT

.alter
Vinp Vinp gnd pulse(0.8v 1.5v 0n 0n 0n 400n 800n)

.end
Slew Rate 1

Slew Rate 2
Question:

Why do we use a Common Source structure as the output stage of Two-Stage


Operational Amplifier? What if we use the other structures?
- We use a common source structure as the output stage of Two-Stage Operational
Amplifier because it increases the DC gain for a given voltage supply by an order of
magnitude and increases the output signal wing due to lesser number of transistors. This
also maximizes the value of the transconductance since it has a high voltage gain, high
output, and input impedance. If we use other structures, it would not be as good as the
common source structure because other structures have low output and input impedance
which then makes the system unstable.
Hand Calculation:
CONCLUSION
In conclusion, I have observed from the simulations that having a compensation
capacitor makes a difference than having no compensation capacitor at all, also, as we
increase the compensation capacitor, the phase margin would also increase, thus,
improves the system to be more stabilized. The same result is achieved in the phase
margin if the compensation resistor is added, phase margin increases if the Rc is
increased.

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