Digital Multi-Mode PFC + LLC Combo Controller: Product Highlights
Digital Multi-Mode PFC + LLC Combo Controller: Product Highlights
Digital Multi-Mode PFC + LLC Combo Controller: Product Highlights
Description
The IDP2308 is a multi-mode PFC and LLC controller combined with a floating high side driver and a startup cell. A digital
engine provides advanced algorithms for multi-mode operation to support highest efficiency over the whole load range. A
comprehensive and configurable protection feature set is implemented. Only a minimum of external components are
required with the low pin count DSO-14 package. The integrated HV startup cell and advanced burst mode enable to achieve
low stand-by power. In addition a one-time-programming (OTP) unit is integrated to provide a wide set of configurable
parameters that help to ease the design in phase.
Features
Multi-mode PFC Configurable non-linear LLC VCO curve
Configurable PFC gate driver Configurable soft-start
Synchronous PFC and LLC burst mode control VAC input voltage sensing and X cap discharge via HV pin
Applications
LCD-TV 75W ~ 300W
Generarl SMPS
IDP2308
HSGD Vout_2
GD0 HSVCC
VAC ZCD HSGND
CS0 GD1
VS
CS1
Vout_1
VCC
HV GND
HBFB
MFIO
Configuration
GD0 STANDBY
GD1
GD0 1 16 HSGD
CS0 2 15 HSVCC
IDP2308
VCC 3 14 HSGND
GND 4
ZCD 5 12 GD1
VS 6 11 CS1
10 HBFB
HV 8 9 MFIO
PG-DSO-14 (150mil)
Figure 2 Pin Configuration
2 Representative Blockdiagram
A simplified functional block diagram is given in Figure 3. Note that this figure only represents the principle
functionality.
IDP2308 digital combo-PFC & LLC controller consists of an Infineon 66MHz (fMCLK) NanoDSP processor to actualize
both the power factor correction (PFC) and a half-bridge resonant function. The PFC and LLC controllers function
with their configured parameter to optimize the performance. The current sense, zero-crossing and voltage
sense provide the controller as well as the processor inputs for its control.
GD0 HSGD
Memory
PFC Driver
OTP
CS0 RAM HSVCC
Current ROM
Sense
VCC HSGND
Zero Crossing
input
Processor
GND
Voltage
sense LLC
ZCD Driver GD1
Timers Clock
VS Oscillators CS1
Current
Input power supply Sense
RHBFB_PU HBFB
DEPLS
Block
DEPLG Parameter
HV MFIO
MFIO Block
HV Startup cell
3 Functional Description
The functional description gives an overview about the integrated functions and features and their relationship.
The mentioned parameters and equations are based on typical values at TA = 25°C. The correlated minimum and
maximum values are shown in the electrical characteristics in Chapter 4.
This chapter contains following main descriptions:
Introduction (Chapter 3.1)
Overview Controller Features (Chapter 3.2)
General control features (Chapter 3.3)
PFC Controller (Chapter 3.4)
Half-bridge LLC Controller (Chapter 3.5)
Operation Flow (Chapter 3.6)
Overview Protection Features (Chapter 3.7)
Fixed and configurable parameters (Chapter 3.8)
3.1 Introduction
The IDP2308 is a digital Combo-LLC controller to support application topologies with a multi-mode PFC and half-
bridge LLC stage. The IC consists of a smart digital core that provides advanced algorithms for multi-mode
operation and a variety of protection features. A high degree of forward integration is realized by implementing
a floating HV gate driver and a HV startup cell in a slim PG-DSO-14 package. Multifunctional pins ensure a very
low component count in the application. General controller features are summarized in Table 2.
The IC supports highest design-in flexibility in the application by means of an advanced set of configurable
parameters. The configuration can be done via a half duplex UART interface at pin MFIO.
IC Vcc PFC
OCP
PFC current
LLC current
PFC Bus
HBFB
Vout
Burst off Burst on
LLC gate
PFC gate
POWER_on
Auto-restart: A protection mode that stops all PFC and LLC switching operations, puts the IC into a
suitable sleep mode, and initiates a new startup after a configurable break time1.
Begin
HV Startup
Block function
Procesoor flow
Parameter loading
Register inter-links
Enter/Exit
Clocks and Timer configuration
Standby
Scheduler/timers Interrupts
Watchdog
check
Protection Register/
LLC control PFC control Communication
Check status
The processor runs its program from its Read Only Memory (ROM) with random access memory (RAM) as main
data space for computation and control-flow state records during operation.
The processor monitors and processes the analog-to-digital (ADC) data. The processed data is provided to
control the power-factor-correction (PFC) and Resonant LLC converter. The processor also monitors the input
line (AC), its own monitoring lines as well as the output load feedback voltage for protection condition and
mitigates according to the conditions with the protection function. All the information are registered and
interrupts are triggered when interrupt event occurs.
1
Please refer to Chapter 4.7 for more detail about the protection mechanisms.
Processor
VCC Sel R HSGND
e
g
i Clock
GND A s Oscillators
Mux D t
Voltage C e
sense
r
ZCD s GD1
Timers
VS CS1
HV MFIO
HV Startup cell
Figure 6 shows the sensing paths that are multiplexed to the ADC. The ADC sensing is time-multiplexed to the
sensing nodes and is managed internally by the processor. Timers are used to enable and disable the sample and
hold circuit in the current sense block. Within each of the sensing block, there are sub-sensing nodes that allow
measurement for each specific function. See Chapter 4.4.3 and Chapter 4.4.4 for further details.
tRDY
VCC Voltage
Power generation via auxiliary winding status and supplies the device
VCC_ON threshold
UVLO Threshold
0
Time
I(HV)
Time
VCC supply by Dep_SW VCC supply by LLC Auxiliary
Device behaviour Depletion gate on Depletion gate off
Device off Device on
Within the device, a direct AC input monitoring is supported by a resistive sense that is switched on periodically
by an internal timer. The timer switches on the HV startup cell and the switch T2 for a very short time after a
defined period. During this short on-time, the voltage across RSH is sensed to estimate the HV voltage (See Figure
8).
Vbulk
VAC
CVCC
RHV
VCC HV
HV
Startup-cell
Closed / Open Depletion-Cell
Driver
Sampling control
for Vin
T2 measurement
+ Protection
RSH
VHVBID
Range 1 47 53 Hz
Frequency Range 2 57 63 Hz
3.3.4 IC protection
3.3.5 AC detection
This feature is used for detecting AC unplug condition during standby mode and is implemented via a
combination of built-in hardware and firmware. The figure below shows the configuration of the EMI filter and
where input voltage is sensed through the HV pin.
Bridge diode
Vin
and PFC
RHV
To HV pin
During standby mode, low power consumption is the main challenge. IDP2308 makes use of the AC detection
function to detect the AC unplug quicky and reliably. With the AC detection, it neither needs to sample the AC
voltage too often nor needs to trigger the wakeup of the IC too often and hence it can maintain low standby
power consumption. Having detected the AC unplugged, the X-cap discharge function would be triggered. In the
AC detection function, IDP2308 would take AC samples after defined time intervals and based on proprietary
algorithm it determines the decision of unplug condition.
the waiting time tw, which starts when the choke current decreased to zero and an oscillation is observed
at the drain-source voltage of the switching MOSFET and the voltage at the auxiliary winding.
COUT RVS2
Inside chip
GD0
+ CS0
VIN
+
- VS
Bus Voltage
-
RCS RVS1 CVS1
Figure 10 PFC control at GD0 pin and Voltage and current sensing at VS and CS pins
CrCM is also equivalent to quasi-resonant switching at first inductor current valley or QR1 operation. The
switching period of CrCM operation is given by
CrCM is ideal for full load operation, where the constant on-time is large. However, the constant on-time reduces
at light load, resulting in very high switching frequency particularly near the zero crossings of the input voltage.
The high switching frequency will increase the switching losses, resulting in poor efficiency at light load.
The new multimode PFC control algorithm implemented in IDP2308 can lower the switching frequency by adding
an additional delay into each switching cycle through selecting further inductor current valleys to achieve QR2,
QR3 and up to QR10 operation. In this way, the switching frequency is limited between a minimum and maximum
value. The switching period of the multimode PFC operation, consisting of QR1 to QR10 operation and DCM, is
given by
Tsw Tsw
ig/iL
1 iL,pk
iL, pk tw iL,ave
2
0
ton toff t
tcyc
iL,pk
iS
iL,sampled
0
t on t
2 Tosc
4
VPFCZCD
0
t
QR1 QR2 QR1
Introduction of the delay helps to reduce switching frequency but it also distorts the input current waveform and
thus affects the PFC THD performance. The multimode PFC control also consists of an algorithm that optimizes
the applied on-time on a cycle by cycle basis so as to ensure good input current shaping and improve PFC THD
performance.
the faulty resistance level remains unchanged, the ROVP will re-trigger again and again once the bus voltage
drops to normal level when the switching is stopped and results in auto-restart mode.
This feature is disabled by default, which is selectable in the configurable parameters. Since the MFIO pin is a
multifunction pin, not dedicated for high impedance bus voltage sensing, it is recommended to use the proposed
solution with BSS127 shown in Figure 1 to ensure almost lossless ROVP function, not effecting standby
performance.
fHB
f_MaxTCO
Slope_TCO_init
Slope_TCO_min
0 t
Figure 12 Frequency vs. Time of the TCO
VNomHB is realized, while a wide operating frequency range can be covered with fast response to the load change
in both heavy and light load is realized.
fHB
I II III
f_MaxVCO
f_LLVCO
f_NomVCO
f_HLVCO
f_MinVCO
0
THB VHBFB
TMaxVCO
THLVCO
TNomVCO
TLLVCO
TMinVCO
0 V_NomVCO V_MaxVCO
V_LLVCO V_HLVCO VHBFB
The switching period curve is defined by following key points: feedback origin (0, TMinVCO), VCO light load (V_LLVCO,
T_LLVCO), VCO nominal point (VNomVCO, TNomVCO), VCO heavy load (V_HLVCO, T_HLVCO) and feedback maximal point (V_MaxVCO,
T_MaxVCO). In this controller, all values are calculated based on the VCO nominal frequency f_NomVCO and nominal
feedback voltage V_NomVCO with certain factors, as:
the minimal and maximal HB LLC switching frequency f_MinVCO and f_MaxVCO :
𝑓_𝑀𝑖𝑛𝑉𝐶𝑂 = 𝑘𝑓𝑀𝑖𝑛𝑉𝐶𝑂 . 𝑓_𝑁𝑜𝑚𝑉𝐶𝑂 (3)
𝑓_𝑀𝑎𝑥𝑉𝐶𝑂 = 𝑘𝑓𝑀𝑎𝑥𝑉𝐶𝑂 . 𝑓_𝑁𝑜𝑚𝑉𝐶𝑂 (4)
Once these points are defined, the switching period is calculated by a linear interpolation of the switching period
to the feedback voltage, and the switching frequency curve over the whole feedback range is resulted, which is
naturally non-linear function of the feedback voltage, as shown in Figure 13.
For an optimal HB LLC operation, the frequency f_NomVCO should be set as the resonant frequency of the LLC
resonant tank, while the respected feedback voltage V_NomVCO is taken at the middle of the regulation feedback
range.
where the calculated LLC switching frequency based on the HBFB signal is higher than the switching frequency
as defined by the OCP1 protection, the LLC converter resumes control under VCO.
If above scenario occurs continuously more than N_Ocp1_max times, then there will be a serious fault condition, IC
will enter auto restart protection mode to protect the whole system. In the meantime, due to the limited power
transfer during OCP1 protection, the open loop protection or overload protection could also be triggered to enter
auto restart protection mode.
startup 2
LLC OCP1 detection during VOcp1_burst - 750 - mV 13
3.6.1 IC Initialization
As mentioned previously, once the VCC is above the turn-on threshold, the IC is active. The IC enters initialization
state immediately after the VCC is powered up. In the initialization state, the correct setup values are assigned
to the control units and then both PFC and HB are enabled. Also refer to Figure 5 for scheduler.
Scheduler Scheduler
Start
to PFC to LLC
VCC power on
VCC UVLO
from any state
No failure
restart
System Idle
Return Return
No scheduler scheduler
System Auto-restart
Check Brown In
Yes Scheduler to
Prot_Chk
Enable Prot_Chk,
PFC and LLC
yes
Check OTP
no
yes
Scheduler VCC OVP
no
no
xCap yes
Check AC Unplug
Discharge
no
Return
scheduler
Figure 14 General Operation Flow of the Controller
During PFC softstart, the PFC starts its operation according to the sensed signals at ZCD, CS0, and VS. The voltage
control loop (PI regulator) is kept fast enough and the integrator of the PI regulator growth is limited to avoid
output voltage overshoot. As soon as the bus voltage is getting close to the rated value, the PFC enters normal
operation state where it is regulated to improve the power factor.The bus voltage is regulated to its rated value.
From the PFC protections, OCP does not cause any break of the PFC converter operation but OVP1 and OVP2 will
cause a short break of the PFC operation. After the bus voltage comes back to the rated value, the PFC resumes
its operation immediately. In case of long time CCM operation, the PFC enters auto-restart state. After the auto-
restart time break, the PFC restarts with softstart.
over the supply at pin VCC. The self supply via the auxiliary winding must be therefore in place before V VCC
undershoots the VVCCoff threshold.
4 Electrical Characteristics
All signals are measured with respect to ground pin GND, except the highside signals at pins HSVCC and HSGD,
which are measured with respect to pin HSGND. The voltage levels are valid if other ratings are not violated.
1
According to JESD22-A111 Rev A.
2
Latch-up capability according to JEDEC JESD78D, TA= 85°C.
3
ESD-HBM according to ANSI/ESDA/JEDEC JS-001.
4
ESD-CDM according to JESD22-C101F.
Figure 15 PG-DSO-14
Note: Please read the Getting Started guide to learn how to use the macro’s and styles in this template.
1) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
2) Dimensions in mm.
5.2 Marking
Revision History
Major changes since the last revision
Page or Reference Description of change
13 Max RHV in Table 4 changed to 60 kΩ
14, 25, 26, 27 Update description on over temperature protection (OTP)
www.infineon.com