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Sop - Form STD - Logic STD - Logic Sop - Form Arch Sop - Form

The document describes designing a SOP (Sum of Products) boolean equation in VHDL using both behavioral and data flow modeling styles. It includes the VHDL code to implement the equation Y = A'C + B'C using an if-else process in behavioral style and using intermediate signals for the inverted terms in data flow style. It also includes a testbench component and process to simulate and test the behavioral model.

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Kshitij Gurjar
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98 views4 pages

Sop - Form STD - Logic STD - Logic Sop - Form Arch Sop - Form

The document describes designing a SOP (Sum of Products) boolean equation in VHDL using both behavioral and data flow modeling styles. It includes the VHDL code to implement the equation Y = A'C + B'C using an if-else process in behavioral style and using intermediate signals for the inverted terms in data flow style. It also includes a testbench component and process to simulate and test the behavioral model.

Uploaded by

Kshitij Gurjar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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--------------------------------------------------------

---------------------------------------------------------
-- Design a SOP based boolean equation in VHDL (BEHAVIOURAL)

-- Y = Abar C + Bbar C
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity sop_form is
port(
A, B, C: in std_logic;
Y: out std_logic
);
end sop_form;

architecture arch of sop_form is


begin
process(A, B, C)
begin
if (C ='0') then
Y <= '0';

elsif (A ='1' and B ='1') then


Y <= '0';

else
Y <= '1';
end if;
end process;
end arch;

---------------------------------------------------------
--TESTBENCH for SOP form
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench is
-- empty
end testbench;

architecture tb of testbench is
component sop_form is
Port ( A, B, C : in STD_LOGIC;
Y : out STD_LOGIC);
end component;

signal A, B, C, Y : STD_LOGIC;

begin

DUT : sop_form port map(


A => A, B => B, C => C,
Y => Y );

-- 'testbench_signal => design_signal' is the format for portmapping

process
begin

A <= '0';
B <= '0';
C <= '0';
wait for 1 ns;

A <= '0';
B <= '1';
C <= '0';
wait for 1 ns;
assert (Y = '1') report "PASSED" severity error ;

A <= '1';
B <= '0';
C <= '0';
wait for 1 ns;

A <= '1';
B <= '1';
C <= '0';
wait for 1 ns;
wait;

end process;
end tb;
---------------------------------------------------------
-- Design a SOP based boolean equation in VHDL (DATA FLOW)

-- Y = Abar C + Bbar C
---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity c_dataflow is
port(
A, B, C: in std_logic;
Y: out std_logic
);
end c_dataflow;

architecture arch of c_dataflow is


signal not_a: std_logic; --
extra signals we need as intermediate wires
signal not_b: std_logic; --
extra signals we need as intermediate wires

begin
not_a <= not A;
not_b <= not B;

-- final assignment to the output signal


Y <= (not_a and C) or (not_b and c);
end arch;

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