Ringkasan Bab 3
Ringkasan Bab 3
Ringkasan Bab 3
The logic or Boolean expression given for a logic NOR gate is that for Logical Multiplication which it
performs on the complements of the inputs. The Boolean expression for a logic NOR gate is denoted by a plus
sign, ( + ) with a line or Overline, ( ‾‾ ) over the expression to signify the NOT or logical negation of
the NOR gate giving us the Boolean expression of: A+B = Q.
Then we can define the operation of a 2-input digital logic NOR gate as being:
“If both A and B are NOT true, then Q is true”
Logic NOR Gates are available using digital circuits to produce the desired logical function and is given a
symbol whose shape is that of a standard OR gate with a circle, sometimes called an “inversion bubble” at its
output to represent the NOT gate symbol with the logical operation of the NOR gate given as.
B A Q
0 0 1
0 1 0
1 0 0
2-input NOR Gate
1 1 0
Read as A OR B
Boolean Expression Q = A+B
gives NOT Q
C B A Q
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
3-input NOR Gate
1 0 1 0
1 1 0 0
1 1 1 0
Read as
Boolean Expression Q = A+B+C A OR B OR C
gives NOT Q
As with the OR function, the NOR function can also have any number of individual inputs and commercial
available NOR Gate IC’s are available in standard 2, 3, or 4 input types. If additional inputs are required, then
the standard NOR gates can be cascaded together to provide more inputs for example.
The Boolean Expression for this 4-input NOR gate will therefore be: Q = A+B+C+D
If the number of inputs required is an odd number of inputs any “unused” inputs can be held LOW by
connecting them directly to ground using suitable “Pull-down” resistors.
The Logic NOR Gate function is sometimes known as the Pierce Function and is denoted by a downwards
arrow operator as shown, A↓B.
As well as the three common types above, Exclusive-OR, Exclusive-NOR and standard NOR gates can also be
formed using just individual NOR gates.
Commonly available digital logic NOR gate IC’s include:
TTL Logic NOR Gates
0 0 0 1 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 0 1 0
The following table gives a list of the common logic functions and their equivalent Boolean notation where a
“.” (a dot) means an AND (product) operation, a “+” (plus sign) means an OR (sum) operation, and the
complement or inverse of a variable is indicated by a bar over the variable.
AND A.B
OR A+B
NOT A
NAND A .B
NOR A+B
DeMorgan’s Theory
DeMorgan’s Theorems are basically two sets of rules or laws developed from the Boolean expressions
for AND, OR and NOT using two input variables, A and B. These two rules or theorems allow the input
variables to be negated and converted from one form of a Boolean function into an opposite form.
0 1 0 1 0 1 1
DeMorgan’s First Theorem
DeMorgan’s First theorem proves that when two (or more)
input variables are AND’ed and negated, they are
1 0 0 1 1 0 1
equivalent to the OR of the complements of the individual
1 1 1 0 0 0 0
variables. Thus the equivalent of the NAND function will be a negative-OR function, proving that A.B = A+B.
We can show this operation using the following table.
The top logic gate arrangement of: A.B can be implemented using a standard NAND gate with inputs A and B.
The lower logic gate arrangement first inverts the two inputs producing A and B. These then become the inputs
to the OR gate. Therefore the output from the OR gate becomes: A+B
Then we can see here that a standard OR gate function with inverters (NOT gates) on each of its inputs is
equivalent to a NAND gate function. So an individual NAND gate can be represented in this way as the
equivalency of a NAND gate is a negative-OR.
0 0 0 1 1 1 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 0 0 0 0
We can also show that A+B = A.B using the following logic gates example.
The top logic gate arrangement of: A+B can be implemented using a standard NOR gate function using
inputs A and B. The lower logic gate arrangement first inverts the two inputs, thus producing A and B. Thus
then become the inputs to the AND gate. Therefore the output from the AND gate becomes: A.B
Then we can see that a standard AND gate function with inverters (NOT gates) on each of its inputs produces
an equivalent output condition to a standard NOR gate function, and an individual NOR gate can be
represented in this way as the equivalency of a NOR gate is a negative-AND.
Although we have used DeMorgan’s theorems with only two input variables A and B, they are equally valid
for use with three, four or more input variable expressions, for example:
For a 3-variable input
A.B.C = A+B+C
and also
A+B+C = A.B.C
For a 4-variable input
A.B.C.D = A+B+C+D
and also
A+B+C+D = A.B.C.D
and so on.
The logic or Boolean expression given for a logic NAND gate is that for Logical Addition, which is the
opposite to the AND gate, and which it performs on the complements of the inputs. The Boolean expression for
a logic NAND gate is denoted by a single dot or full stop symbol, ( . ) with a line or Overline, ( ‾‾ ) over the
expression to signify the NOT or logical negation of the NAND gate giving us the Boolean expression
of: A.B = Q.
Then we can define the operation of a 2-input digital logic NAND gate as being:
“If both A and B are true, then Q is NOT true”
The Demorgan’s theorem mostly used in digital programming and for making digital circuit diagrams.
There are two DeMorgan’s Theorems. They are described below in detail.
As the NOR and bubbled gates are interchangeable, i.e., both gates have exactly identical outputs for the same
set of inputs.
The Boolean expression for the bubbled OR gate is given by the equation shown below:
Since NAND and bubbled OR gates are interchangeable, i.e., both gates have identical outputs for the same set
This identity or equation (2) shown above is known as DeMorgan’s Second Theorem.
A B Z
0 0 1
0 1 1
1 0 1
1 1 0
In this, both the inputs are inverted before they are applied to an OR gate. The output of a bubbled OR gate can
be derived from its logic circuit and can be expressed by the equation shown below:
Here are the results when the logic circuit of bubbled OR gate when all the possible sets of inputs are applied
such as 00, 01, 10 or 11.
For AB: 00
For AB: 01
For AB: 10
For AB: 11
The truth table for the bubbled AND gate is exactly identical to the truth table of a NAND gate. Hence, NAND
and bubbled OR gate is interchangeable.
B A Q
0 0 0
0 1 1
1 1 0
Giving the Boolean expression of: Q = AB + AB
The truth table above shows that the output of an Exclusive-OR gate ONLY goes “HIGH” when both of its
two input terminals are at “DIFFERENT” logic levels with respect to each other. If these two inputs, A and B
are both at logic level “1” or both at logic level “0” the output is a “0” making the gate an “odd but not the
even gate”. In other words, the output is “1” when there are an odd number of 1’s in the inputs.
This ability of the Exclusive-OR gate to compare two logic levels and produce an output value dependent upon
the input condition is very useful in computational logic circuits as it gives us the following Boolean
expression of:
Q = (A ⊕ B) = A.B + A.B
The logic function implemented by a 2-input Ex-OR is given as either: “A OR B but NOT both” will give an
output at Q. In general, an Ex-OR gate will give an output value of logic “1” ONLY when there are
an ODD number of 1’s on the inputs to the gate, if the two numbers are equal, the output is “0”.
Then an Ex-OR function with more than two inputs is called an “odd function” or modulo-2-sum (Mod-2-
SUM), not an Ex-OR. This description can be expanded to apply to any number of individual inputs as shown
below for a 3-input Ex-OR gate.
When the value on this pin is 1, then the component behaves just like the
respective component (a buffer or a inverter (NOT gate)).
When the value is 0 or unknown (i.e., floating), then the component's output is
also floating.
When the value is an error value (such as would occur when two conflicting
values are being fed into the input), then the output is an error value.
Controlled buffers can be useful when you have a wire (often called a bus) whose
value should match the output of one of several components. By placing a controlled
buffer between each component output and the bus, you can control whether that
component's output is fed onto the bus or not.
Pins
Facing
The direction of the component (its output relative to its input).
West edge (input, bit width matches Bit Width attribute)
The component input that will be used to compute the output if the control
input is 1.
South edge (input, bit width 1)
The component's control input.
East edge (output, bit width matches Bit Width attribute)
The component's output, which will be floating if the control input is 0 or
floating, the error value if the control input is the error value, and will be
computed based on the west-side input if the control input is 1.
Attributes
Data Bits
The bit width of the component's inputs and outputs.
The Exclusive-NOR Gate, also written as: “Ex-NOR” or “XNOR”, function is achieved by combining
standard gates together to form more complex gate functions and an example of a 2-input Exclusive-NOR gate
is given below.
B A Q
0 0 1
0 1 0
1 0 0
2-input Ex-NOR Gate
1 1 1
Read if A AND B
Boolean Expression Q = A ⊕ B the SAME
gives Q
C B A Q
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
3-input Ex-NOR Gate
1 0 1 1
1 1 0 1
1 1 1 0
Giving the Boolean expression of: Q = ABC + ABC + ABC + ABC
We said previously that the Ex-NOR function is a combination of different basic logic gates Ex-OR and
a NOT gate, and by using the 2-input truth table above, we can expand the Ex-NOR function
to: Q = A ⊕ B = (A.B) + (A.B) which means we can realise this new expression using the following individual
gates.
One of the main disadvantages of implementing the Ex-NOR function above is that it contains three different
types logic gates the AND, NOT and finally an OR gate within its basic design. One easier way of producing
the Ex-NOR function from a single gate type is to use NAND gates as shown below.
In the next tutorial about Digital Logic Gates, we will look at the digital Tri-state Buffer also called the non-
inverting buffer as used in both TTL and CMOS logic circuits as well as its Boolean Algebra definition and
truth table.