KING KHALID UNIVERSITY COLLEGE OF

COLLEGE OF COMPUTER SCIENCE

COMPUTER SCIENCE DEPARTMENT

LAB MANUAL
DIGITAL LOGIC
241 CSM-4

STUDENT NAME:
ID:
GROUP NO:

PREPARED BY:
Dr. Nermeen Talaat

2016/2017
 King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Course Syllabus
Course Title Digital Logic
Course Code 241 CSM-4
Sunday & Tuesday & Thursday : 10 am to 11 am
Lecture Times
Monday, Wednesday, Thursday : 11 am to 12 pm
A/3/31
Lecture Room
41/3/A
Dr. Nermeen Talaat , Dr.Radhakrishnan, Ms. Shabaht Khatoun and Mr. Mohammed
Instructors Name
Mohsin Ahmed
Office Hours Monday 1.00 PM to 2.00 PM; Thursday 9-11
This course is designed to familiarize the students with Digital Logic Design, with the
specific objective to make them understand how the hardware of the computer works.
Course Short Students are introduced to the concept of Boolean functions, design of logic circuits,
Description simplification of the circuits, combinational logic design, working of registers,
counters and adders. On the whole the students are expected to acquire a reasonably
good knowledge of the internal working of the Central Processing Unit.
1. Define Fundamental of Digital logic.
2. Describe various performances Define Digital logic. for different basic logic
gates.
3. Justify the Boolean Algebra.
Course Objectives
4. Explain Building of Digital logic circuit.
5. Show working of Digital Kite.
6. Appraise role of digital algebra.
7. Illustrate the role of digital circuits.
Pre-Requisite/s None
1. "Logic and Computer Design Fundamentals", M. Morris Mano & Charles
Text Book/s
R. Kime, ISBN 0-13-1405239, Prentice Hall, 2004
1. "Digital Design", Mano, M. Morris. 3rd edition, ISBN 0-13-062121-8,
Prentice-Hall, 2002.
Reference Book/s 2. "Fundamentals of logic Design". Thomson Learning. 5th edition,
Brooks/Cole, 2004.

Course Policy
Class participation and regular attendance is expected. Students are responsible for
(Include details, if it
bringing themselves up-to-date on class material and assignments. Exams will be a
is offered as a
combination of material presented in lectures, and homework problems. Home work
blended e-learning
should be completed and returned in operational form.
course)

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 King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Assignments Two assignments

Grading As per university rules
Quizzes and Assignments 10
Mid-Examination1 10
Student Evaluation
Mid-Examination 2 10
Laboratory Examination 20
Final Examination 50
To improve level of attendance of students, it was decided to award a maximum
Remarks:
of 2 marks on the basis of percentage of attendance.
Week Topic Hours
1 Introduction to digital systems 3
Number systems (binary)
Negative number representation 6
Unsigned/signed addition and subtraction
2,3 Octal/hexadecimal number representation
Number conversion
BCD,Gary, ASCII
Logic Algebra 6
Theorems of logic algebra
Digital Logic gates and Circuits
4,5 Truth tables
Synthesis using AND, OR, and NOT gates
Design examples
Logic function minimization, Karnaugh map 6
Two- and Three-Variable Map.
Four-Variable Map.
6,7
Product of Sums Simplification.
Don‟t-Care Conditions.
Minimum SOP/POS forms
Combinational Logic Circuit Building Blocks 9
Adders(half and full)/subtracters
Multiplexers
8, 9,10 Decoders, Encoders and priority encoders
Demultiplexers
Comparators
Sequential Logic Circuit Building Blocks 9
Timers- Latches
11, 12,13
Flip-flops- Registers- Counters
Synchronous Sequential Logic Circuits
14, 15 Memory cells: Gate arrays-RAM and ROMs, 6

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Designing with read only memory

Designing with programmable logic arrays (PLAs)
Designing with programmable array logic (PALs)
Seven-segment display

 Course Description

This course is designed to familiarize the students with Digital Logic Design, with the
specific objective to make them understand how the hardware of the computer works.
Students are introduced to the concept of Boolean functions, design of logic circuits,
simplification of the circuits, combinational logic design, working of registers,
counters and adders. On the whole the students are expected to acquire a reasonably
good knowledge of the internal working of the Central Processing Unit.

 Course Learning Outcomes

 Define Fundamental of Digital logic.

 Describe various performances Define Digital logic for different basic logic gates.
 Justify the Boolean Algebra.
 Explain Building of Digital logic circuit.
 Show working of Digital Kite.
 Appraise role of digital algebra.
 Illustrate the role of digital circuits.

 Lab Description
This lab depends on the KL-31001 kit that is used to simulate different logic gate with
different configuration, and they have to fill the missing table that will help them to
understand how the digital circuit works.

Hardware / Software Requirements

 KL-31001 digital kit

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Marks Distribution with assessment criteria

S. No Assessment Week Due Marks

1 Assignment 1 5 3

2 Mid I examination 8 10

3 Quiz I 9 2

4 Assignment 2 13 3

5 Mid II examination 14 10

6 Quiz II 15 2

7 Final examination 16 & 17 50

8 Lab Activities 20

Total Marks 100

Instructions for assessment methods:

1. Students have to do the connection by themself after the instructor did,
they also have to fill the output table for each lab, so they will marks
on for participation and activity in lab.

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Week-wise Practical Schedule (15 weeks)

Week Lab/Exerci Title of the Experiment / Exercise Page
se # No.
1 Introduction to Number System 6
2 Introduction to The KL-31001 11

3 Measurements of Basic Logic Gates 14

Characteristics
4 Combinational Logic Circuits NOR gate 18

5 Combinational Logic Circuits NAND gate 21

6 Combinational Logic Circuits XOR gate 24

7 Practical Midterm Exam

8 AND-OR-INVERTER (A-O-I) gate circuit 26

9 HALF and FULL ADDER 28

10 HALF and FULL SUBTRACTOR 32

11 Comparator and Decoder circuits 36

12 Counter circuit 41

13,14 Latches And Flip Flops Characteristics 44

15 Revision

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #1
Introduction to Number System
OBJECTIVE

1. To understand the principles of numbering systems

2. To convert numbers from one base to another

Definition: Number system is the way to represent a number in different forms.

Types of Number system:

1. Binary Number System: It is the number system with base value 2 means it has
only two digits to represent the data. The digits are (0, 1). E.g. 00,01,10,11,100….
2. Decimal Number System: It is the number system with base value 10 means it
has 10-digits to represent the data. The digits are(0-9). Eg. 0,1,2,3,4,5,6 ………
3. Octal Number System: It is the number system with base value 8 means it has 8
digits to represent the data. The digits are ( 0-7).
4. Hexadecimal Number System : It is the number system with base value 16
means it has 16 digits to represent the data. The digits are (0-15). Eg.
0,1,2,3…….,9,A,B,C,D,E,F

Decimal and Binary Numbers

When we write decimal (base 10) numbers, we use a positional notation system. Each
digit is multiplied by an appropriate power of 10 depending on its position in the number:

For example:

843 = 8 x 102 + 4 x 101 + 3 x 100

= 8 x 100 + 4 x 10 + 3 x 1

= 800 + 40 + 3

For whole numbers, the rightmost digit position is the one‟s position (100 = 1). The
numeral in that position indicates how many ones are present in the number. The next
position to the left is ten‟s, then hundred‟s, thousand‟s, and so on. Each digit position has
a weight that is ten times the weight of the position to its right.

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

In the decimal number system, there are ten possible values that can appear in each digit
position, and so there are ten numerals required to represent the quantity in each digit
position. The decimal numerals are the familiar zero through nine (0, 1, 2, 3, 4, 5, 6, 7, 8,
9).

In a positional notation system, the number base is called the radix. Thus, the base ten
system that we normally use has a radix of 10. The term radix and base can be used
interchangeably. When writing numbers in a radix other than ten, or where the radix isn‟t
clear from the context, it is customary to specify the radix using a subscript. Thus, in a
case where the radix isn‟t understood, decimal numbers would be written like this:

12710 1110 567310

Generally, the radix will be understood from the context and the radix specification is left
off.

The binary number system is also a positional notation numbering system, but in this
case, the base is not ten, but is instead two. Each digit position in a binary number
represents a power of two. So, when we write a binary number, each binary digit is
multiplied by an appropriate power of 2 based on the position in the number:

For example:

101101 = 1 x 25 + 0 x 24 + 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20

= 1 x 32 + 0 x 16 + 1 x 8 + 1 x 4 + 0 x 2 + 1 x 1

= 32 + 8 + 4 + 1

In the binary number system, there are only two possible values that can appear in each
digit position rather than the ten that can appear in a decimal number. Only the numerals 0
and 1 are used in binary numbers. The term „bit‟ is a contraction of the words „binary‟ and
„digit‟, and when talking about binary numbers the terms bit and digit can be used
interchangeably. When talking about binary numbers, it is often necessary to talk of the
number of bits used to store or represent the number. This merely describes the number of

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

binary digits that would be required to write the number. The number in the above
example is a 6 bit number.

The following are some additional examples of binary numbers:

1011012 112 101102

Conversion between Decimal and Binary

Converting a number from binary to decimal is quite easy. All that is required is to find
the decimal value of each binary digit position containing a 1 and add them up.

For example: convert 101102 to decimal.

10110
1 x 21 = 2

1 x 22 = 4

1 x 24 = 16

22

Another example: convert 110112 to decimal

11011

1 x 20 = 1

1 x 21 = 2

1 x 23 = 8

1 x 24 = 16

27

The method for converting a decimal number to binary is one that can be used to convert
from decimal to any number base. It involves using successive division by the radix until
the dividend reaches 0. At each division, the remainder provides a digit of the converted
number starting with the least significant digit.

An example of the process: convert 3710 to binary

37 / 2 = 18 remainder 1 (least significant digit)

18 / 2 = 9 remainder 0

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

9/2=4 remainder 1

4/2=2 remainder 0

2/2=1 remainder 0

1/2=0 remainder 1 (most significant digit)

The resulting binary number is: 100101

Another example: convert 9310 to binary

93 / 2 = 46 remainder 1 (least significant digit)

46 / 2 = 23 remainder 0

23 / 2 = 11 remainder 1

11 / 2 = 5 remainder 1
5/2=2 remainder 1

2/2=1 remainder 0

1/2=0 remainder 1 (most significant digit)

The resulting binary number is: 1011101

Hexadecimal Numbers
In addition to binary, another number base that is commonly used in digital systems is
base 16. This number system is called hexadecimal, and each digit position represents a
power of 16. For any number base greater than ten, a problem occurs because there are
more than ten symbols needed to represent the numerals for that number base. It is
customary in these cases to use the ten decimal numerals followed by the letters of the
alphabet beginning with A to provide the needed numerals. Since the hexadecimal system
is base 16, there are sixteen numerals required. The following are the hexadecimal
numerals:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

The following are some examples of hexadecimal numbers:

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

1016 4716 3FA16 A03F16

The reason for the common use of hexadecimal numbers is the relationship between the
numbers 2 and 16. Sixteen is a power of 2 (16 = 24). Because of this relationship, four
digits in a binary number can be represented with a single hexadecimal digit. This makes
conversion between binary and hexadecimal numbers very easy, and hexadecimal can be
used to write large binary numbers with much fewer digits. When working with large
digital systems, such as computers, it is common to find binary numbers with 8, 16 and
even 32 digits. Writing a 16 or 32 bit binary number would be quite tedious and error
prone. By using hexadecimal, the numbers can be written with fewer digits and much less
likelihood of error.

To convert a binary number to hexadecimal, divide it into groups of four digits starting
with the rightmost digit. If the number of digits isn‟t a multiple of 4, prefix the number
with 0‟s so that each group contains 4 digits. For each four digit group, convert the 4 bit
binary number into an equivalent hexadecimal digit.

For example: Convert the binary number 10110101 to a hexadecimal number

Divide into groups for 4 digits 1011 0101

Convert each group to hex digit B 5

B516

Another example: Convert the binary number 0110101110001100 to hexadecimal

Divide into groups of 4 digits 0110 1011 1000 1100

Convert each group to hex digit 6 B 8 C

6B8C16

To convert a hexadecimal number to a binary number, convert each hexadecimal digit

into a group of 4 binary digits.

Example: Convert the hex number 374F into binary

3 7 4 F

Convert the hex digits to binary 0011 0111 0100 1111

00110111010011112

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #2
Introduction to The KL-31001

OBJECTIVE

To be familiar with lab equipments.

Figure 2: KL-300 Trainer Kit

The Main Trainer Kit:
1. Dual VC Power Supply.
2. Adjustable DC Power Supply.
3. Standard Frequency.
4. Clock Signal Generator.
5. Data Switch.
6. Pulser Switch.
7. Line Signal Generator.
8. Thumbwheel Switch.
9. Logic Indicator.
10. Digital Display.
11. Logic Probe.

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Department of Computer Science 241 CSM-4

12. Speaker.
13. Breadboard.

1. Dual DC Power Supply

(1) Voltage Range : +5V, 1.5A; -5V, 0.3A, ±12V, 0.3A
(2) With output overload protection

2.Adjustable DC Power Supply

1. Voltage Range : +1.5V ~ +15V
2. Maximum Current Output : 0.5A
3. With output overload protection
3. Standard Frequency
1. Frequency : 1MHz, 60Hz, 1Hz
2. Accuracy : ±0.01% (1MHz)
3. Fanout : 10 TTL load
4. Clock Signal Generator
1. Frequency : 1Hz-1MHz (6 Ranges)
a) 1Hz ~ 10Hz d.
b) 1KHz ~ 10KHz
c) 10Hz ~ 100Hz
d) 10KHz ~ 100KHz
e) 100Hz ~ 1KHz
f) 100KHz ~ 1MHz
2. Fanout : 10 TTL load

3. Data Switch
1. 8-bit DIP switch×2, 16-bit TTL level output.
2. Toggle switch×4, each with DEBOUNCE circuit
3. Fanout: 10 TTL load
4. Pulser Switch
1. 2 sets of independent control output.
2. Each set with Q, Q output, pulse width > 5ms
3. Each set of switch with DEBOUNCE circuit
4. Fanout: 10 TTL load

3. Thumbwheel Switch
2-digit, BCD code output, common point input

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Display
4. Logic Indicator
1. 16 sets of independent LED indicates high and low logic state
2. Input Impedence: < 100KΩ
5. Digital Display
1. 4 sets of independent 7-segment LED display
2. With BCD, 7-segment decoder/driver and DP input
3. Input with 8-4-2-1 code

Testing Devices
6. Logic Probe
1. TTL and CMOS level
2. 5mm LED displays
3. "Lo" and "Hi" LED display low and high logic state respectively
7. Speaker
One 8Ω, 0.25W speaker with driver circuit

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #3

Measurements of Basic Logic Gates Characteristics

OBJECTIVE

Understanding the symbols and characteristics of various basic logic gates.

BACKGROUND

1. OR gate
The truth table is a table that shows a logic gate's corresponding inputs and outputs under
ideal conditions.

STATE INPUTS OUTPUTS

A B F

0 0 0 0

1 0 1 1

2 1 0 1

3 1 1 1

In Boolean expression, F = A+B

2. AND gate
STATE INPUTS OUTPUTS

A B F

0 0 0 0

1 0 1 0

2 1 0 0

3 1 1 1

In Boolean expression, F= AB

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

3. Inverter gate

STATE INPUTS OUTPUTS

A F

0 0 1

1 1 0

In Boolean expression, F= A

4. NAND gate

STATE INPUTS OUTPUTS

A B F

0 0 0 1

1 0 1 1

2 1 0 1

3 1 1 0

In Boolean expression, F= AB

5. NOR gate
STATE INPUTS OUTPUTS

A B F

0 0 0 1

1 0 1 0

2 1 0 0

3 1 1 0

In Boolean expression, F= A+B

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

6. XOR gate

STATE INPUTS OUTPUTS

A B F

0 0 0 0

1 0 1 1

2 1 0 1

3 1 1 0

When A=B, the output F=0.

When A≠B, the output F=1.

In Boolean expression, F= A  B

The output F of an XOR is equal to A  B=A'B + AB'. XOR gates can be constructed
using NOT, AND , and OR gates.

NOTE: these truth tables are based on "positive" logic where positive voltage represents
"1" and negative voltage represents "0". In case negative logic is used the output will be
reversed.

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

EQUIPMENTS REQUIRED

Module KL-33001.

LAB Connection:

For each step in part 1 of the procedures, show circuit connection in logic diagram and pin
diagram.

PROCEDURES:

Use Module KL-33001 block d , to test the NAND, NOR and XOR gates and write down
the corresponding truth table for each circuit. Show results to your instructor.

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #4
Combinational Logic Circuits NOR gate

OBJECTIVES

1. Understanding how to construct other combinational logic gates using NOR

gate.
2. Understanding how to construct any combinational logic function using NOR
gate only.

BACKGROUND

The Boolean expression for the NOR gate is F=(A+B); in deMorgan‟s theorem,
F=(A+B)=A'B'. The NOR gate can be used to construct NOT; OR; AND; NAND; and
XOR gates. We will attempt to construct various logic gates in this experiment by
connecting NOR gates in different ways.

EQUIPMENTS REQUIRED

KL-31001 trainer kit; Module KL-33002.

PROCEDURES:

PART 1: NOR gate using as NOT gate

a) Use the KL-33002 (block a) NOR gates to build an inverter as shown in figure (1).

Figure 1: NOR circuit.

b) Connected the (block a) as shown in figure(2)

Figure 2: KL-33002 Block a

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

c) Fill the truth table below

States A OUTPUTS

PART 2: NOR gate using as OR gate

a) Use the NOR gates to build an OR gate as shown in figure (3).

Figure (3): OR circuit

b) Connect the circuit (KL-33002 (block a)), on the breadboard of the trainer kit,
connect inputs A, B, and output F to SW1, SW0, and L1 respectively, and verify
the truth table.
A B OUTPUT

PART 3: NOR gate using as AND gate

a) Use the NOR gates to build an AND gate as shown in figure (4).

Figure 4: AND Circuit

b) Connected the (block a) as shown in figure(5)

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Figure 5: KL-33002 Block a

c) Connect the circuit (KL-33002 (block a)), on the breadboard of the trainer kit,
connect inputs A, B, and output F to SW1, SW0, and L1 respectively, and verify
the truth table.
A B F3

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #5
Combinational Logic Circuits with NAND gate
OBJECTIVES

1. Understanding how to construct other combinational logic gates using NAND

gate.
2. Understanding how to construct any combinational logic function using
NAND gate only.

BACKGROUND

The Boolean expression for the NAND gate is F=(AB); in deMorgan‟s theorem,
F=(AB)=A'+B'. The NAND gate like the NOR gate can be used to construct NOT; OR;
AND; NAND; and XOR gates. We will attempt to construct various logic gates in this
experiment by connecting NAND gates in different ways.

EQUIPMENTS REQUIRED

KL-31001 trainer kit; Module KL-33002.

PROCEDURES:

PART 1: NAND gate using as NOT gate.

a) Use the NAND gates to build an inverter as shown in figure 6.

Figure 6: NOT Circuit

b) Connect the circuit (KL-33002 block b), on the breadboard of the trainer kit,
connect input A to data switch SW0, and output F to LED L1 as shown in figure 7,
and verify the truth table.

Figure 7:KL-33002 block b

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

A B F2

PART 1: NAND gate using as AND gate.

a) Use the NAND gates to build an AND gate as shown in figure 8.

Figure 8: AND Circuit

b) Connect the circuit (KL-33002 block b), on the breadboard of the trainer kit,
connect inputs A, B, and output F to SW1, SW0, and L1 respectively as shown in
figure 9, and verify the truth table.

Figure 9: KL-33002 Block b

A B F4

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

PART 1: NAND gate using as OR gate.

a) Use the NAND gates to build an OR gate as shown in figure (10).

Figure 10: OR Circuit.

b) Connect the circuit (KL-33002 block b), on the breadboard of the trainer kit,
connect inputs A, B, and output F to SW1, SW0, and L1 respectively as shown in
figure 11, and verify the truth table.

Figure 11: KL-33002 block b

A B F4

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #6
Combinational Logic Circuits with XOR gate

OBJECTIVES

Understanding the characteristics of XOR gates.

EQUIPMENTS REQUIRED

KL-31001 trainer kit; Module KL-33002.

BACKGROUND

PROCEDURES:

a) Connect inputs A to SW1, D to SW2; outputs F1 to L1; F3 to L3 and F4 to L4, as

shown in figure 12.

Figure 12:KL-33002 Block b

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

b) Fill the truth table below

INPUT OUTPUT

D A F1 F2 F3 F4

0 0

0 1

1 0

1 1

 Exercises (To be solved in Classroom):

 Task 1:Construct XOR gate with basic gates using Module KL-
33002 block c, using the connection below

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #7
AND-OR-INVERTER (A-O-I) gate circuit

OBJECTIVES

Understanding the basic principle of combined logic.

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab, Module KL-33002.

BACKGROUND
As shown in the figure 13, AND –OR-INVERTER gates consist of two AND gates, one
OR gate and one INVERTER.

Figure 13: AND-OD-INVERTER Circuit

PROCEDURES:

a) Connect inputs A, A1, B, B1 to data switches SW0, SW1, SW2, and SW3
respectively. Connect outputs F3, F4 to logic indicators L1 and L2, as shown in
figure 14.

Figure 14: KL-33002 Block C

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Set B×B1 to “0”, follow the input sequences for A, A1 and record the outputs.

B×B1=0

A1 A F3 F4

0 0

0 1

1 0

1 1

A1×A=0

B1 B F3 F4

0 0

0 1

1 0

1 1

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #8
HALF and FULL Adder Circuits

OBJECTIVE

1. To understand how to construct half and full adders from basic combinational
logic.

BACKGROUND

The basic “half adder” (HA) adds two bits to produce an arithmetic result and a
possible carry. The basic diagram of the half-adder is given below:

Figure 15: HALF Adder Circuit

This circuit produces a 1 sum whenever A or B is 1, otherwise “Sum” is 0.

However, when both A and B are 1 (and thereby Sum is 0), Carry is 1. This
circuit produces a “complete” add function as long as there is no “carry-in,” i.e.,
as long as only two one-bit numbers are being added. If the numbers have more
than one bit magnitude, however, all but the least significant bit (LSB) additions
must have a carry-in, since there is the possibility of a carry being generated from
addition of less significant bits in the number. In that case, the so called “full
adder” (FA) must be used.

The full adder contains circuitry to accommodate a carry-in from addition of the two
next least significant bits. Thus, addition of the two LSBs of two numbers can be
made using half-adders, but full adders must be used to add the other bits of the two
numbers.

Figure 16: FULL Adder Circuit

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Full-Adder” (FA) can be build using two half as shown in the figure below

Figure 17: FULL Adder Block

EQUIPMENTS REQUIRED

KL-31001 trainer kit, lab module KL-33004(block a).

PROCEDURES:

PART 1: HALF adder

a) Construct the circuit of HA using module KL-33004 block a, connect inputs A and
B to data switches and outputs F1 (carry) and F2 (sum) to LEDs, and do any other
connections using clips as shown in figure 18. Record the truth table of the circuit.

Figure 18:KL-33004 Block a (Half adder)

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

A B SUM Carrier

F2 F1

PART 2: FULL Adder

a) Construct the circuit of FA using module KL-33004 block a, connect inputs A, B

and C to data switches and outputs F3 (carry) and F5 (sum) to LEDs. And do any
other connections using clips Record the truth table of the circuit.

Figure 19: KL-33004 Block a (Full adder)

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Department of Computer Science 241 CSM-4

A B C SUM Carrier

F5 F3

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #9
HALF and FULL subtraction Circuits

OBJECTIVE

1. To understand how to construct half and full subtraction from basic combinational
logic.

BACKGROUND

Subtractor is the one which used to subtract two binary number(digit) and provides
Difference and Borrow as a output. In digital electronics we have two types of subtractor.

1. Half Subtractor
2. Full Subtractor

Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit from
another single bit binary digit. Like Adders Here also we need to calculate the equation
of Difference and Borrow .

Difference = A'B+AB'=A B
Borrow=A'B
The logic Diagram of Half Subtractor is shown below.

Figure 20: Half Subtractor Circuit

Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary
digit is known as Full Subtractor. The Difference and Borrow will written as

Difference=A'B'C+A'BB'+AB'C'+ABC
Reduce it like adder

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Then We got
Difference=A B C
Borrow=A'B'C+A'BC'+A'BC+ABC
=A'B'C+A'BC'+A'BC+A'BC+A'BC+ABC ----------> A'BC=A'BC+A'BC+A'BC
=A'C(B'+B)+A'B(C'+C)+BC(A'+A)
Borrow=A'C+A'B+BC

The logic diagram of Full Subtractor is shown in figure 21

Figure 21: Full Subtractor Circuit

EQUIPMENTS REQUIRED

KL-31001 trainer kit, lab module KL-33004(block a).

PROCEDURES:

PART 1: HALF Subtractor

b) Construct the circuit of HA using module KL-33004 block a, connect inputs A and
B to data switches and outputs F1 (Borrow) and F2 (Difference) to LEDs, and do
any other connections using clips as shown in figure 22. Record the truth table of
the circuit.

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Figure 22: KL-33004 block a ( Half Subtractor )

A B Difference Borrow

F2 F1

PART 2: FULL Subtractor

b) Construct the circuit of FA using module KL-33004 block a, connect inputs A, B

and C to data switches and outputs F3 (Borrow) and F5 (Difference) to LEDs.
And do any other connections using clips Record the truth table of the circuit.

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Figure 23: KL-33004 block a ( Full Subtractor )

A B C Difference Borrow

F5 F3

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #10
Comparator and Decoder circuits
OBJECTIVES

2. Understanding the construction and operational principles of digital comparators

and decoders.

BACKGROUND

Comparator circuits:

At least two numbers are required to perform any comparison. The most simple form
of comparator has two inputs. If the two inputs are called A and B there are three
possible outputs : A>B; A=B; A<B. figure 24 shows the schematic and symbol of a
simple comparator.

Figure 24: Comparator Circuit

Decoder circuits:

A decoder is a logic circuit that will detect the presence of a specific binary number or
word. The input to the decoder is a parallel binary number and the output is a binary
signal that indicates the presence or absence of that specific number. A binary-to-octal
decoder is shown in Figure 25. There are 3 binary inputs A, B, C and 8 octal outputs
Q0Q7. If CBA=”010” output Q2=”1”. When CBA=”111” output Q7= ”1 “.

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Department of Computer Science 241 CSM-4

Figure 25: Decoder 3 to 8

EQUIPMENTS REQUIRED

KL-31001 trainer kit, lab module KL-33002 / KL-33005

PROCEDURES:

Part I: Comparator constructed with basic logic gates

c) Use model KL-33002 block C, insert connection clips in suitable places to

construct a 1-bit comparator shown in figure 26.
d) Connect inputs A and B to data switches SW1 and SW2, connect outputs F1, F2,
F5 to LEDs L1, L2, L3 respectively. Record the truth table.

Figure 26: KL-33002 block c ( Comparator)

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Department of Computer Science 241 CSM-4

INPUTS OUTPUTS

A B A>B A=B A<B

0 0

0 1

1 0

1 1

Part II: Comparator constructed with TTL IC

c) Block d of module KL-33002 will be used in this part. U6 is a 7485 4-bit

comparator IC.

Figure 27: KL-33002 Block d

d) Connect inputs A>B to SWI , A=B to SW2 , A<B to SW3 . Connect inputs
A1A4 and B1B4 of the 7485 to DIP Switches DIP1.0DIP1.3 and DIP2.0DIP
2.3 respectively.
e) Assuming inputs A1A4=A and B1B4=B and A=B, follow input sequences in
Table and record the outputs.

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Department of Computer Science 241 CSM-4

INPUTS OUTPUTS

SW3 SW2 SW3 L2 L1 L0

A>B A=B A<B A>B A=B A<B

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 1

f) Set SW3 to “0”; SW2 to “1”; SW1 to “0”. Observe and record the outputs in table

INPUTS OUTPUTS

A B A>B A=B A<B

5 3

7 13

6 6

Part III: Constructing a 2-to-4 decoder with basic logic gates

a) Use model KL-33005 block C shown in figure 28.

b) Connect inputs A and B to data switches SW0 and SW1, connect outputs F1, F2,
F3, F4 to LEDs L1, L2, L3 respectively.
c) Follow the input sequences for A and B in table and record the output states.

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College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

B A F1 F2 F3 F4

Figure 28: Decoder 2 to 4

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King Khalid University Lab Manual
College of Computer Science Digital Logic
Department of Computer Science 241 CSM-4

Experiment #11
Counter circuit
OBJECTIVES

1. Understanding the construction and operational principles of digital BCD-to-

7segment decoder.

BACKGROUND

BCD-to-7segment decoder

The idea of a seven-segment indicator for representing decimal numbers. Each segment of
a seven-segment display is a small light-emitting diode (LED) or liquid-crystal display
(LCD), and - as is shown below - a decimal number is indicated by lighting a particular
combination of the LED's or LCD's elements:

Binary-coded-decimal (BCD) is a common way of encoding decimal numbers with 4

binary bits as shown below:
Decimal digit 0 1 2 3 4

BCD code 0000 0001 0010 0011 0100

Decimal digit 5 6 7 8 9

BCD code 0101 0110 0111 1000 1001

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Department of Computer Science 241 CSM-4

Your job for this lab is to design and test a circuit to convert a 4-bit BCD signal into a 7-
bit control signal according to the following figure :

Figure 29: BCD-to-7segment decoder device

EQUIPMENTS REQUIRED

KL-31001 trainer kit, Module KL-33005 / KL-33006

PROCEDURES:

Part I: BCD-to-7segment decoder

INPUTS 7- Segments Display

D C B A a b c d e f g number

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

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e) Connect the input (LT) to DIP1.0 and se it to logic 1. Follow the input sequences
for D, C, B, A in Table 9.1
and record outputs of the 7-
segment display.

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Department of Computer Science 241 CSM-4

Experiment # 12

Latches And Flip Flops Characteristics

OBJECTIVE
1. To become familiar with flip-flops.
2. To implement and observe the operation of different flip-flops.

BACKGROUND

1. Sequential Circuits:

Digital electronics is classified into combinational logic and sequential logic.

Combinational logic output depends on the inputs levels, whereas sequential logic output
depends on stored levels and also the input levels.

The memory elements are devices capable of storing binary info. The binary info stored in
the memory elements at any given time defines the state of the sequential circuit. The
input and the present state of the memory element determine the output. Memory
elements next state is also a function of external inputs and present state. A sequential
circuit is specified by a time sequence of inputs, outputs, and internal states.
Examples of sequential circuits are Flip-Flops, latches, counters, registers, and time
state generators.
So, combinatorial circuits are ones whose outputs depend on the current input state. When
inputs change, the outputs do not depend on the previous inputs.
Sequential circuits are similar, but they do also rely on previous input states. It can be
inferred that they have memory.
There are two types of sequential circuits. Their classification depends on the timing of
their signals:
a) Synchronous sequential circuits
b) Asynchronous sequential circuits
Synchronization is achieved by a timing device called a clock pulse generator. Clock
pulses are distributed throughout the system in such a way that the flip-flops are affected
only with the arrival of the synchronization pulse. Synchronous sequential circuits that
use clock pulses in the inputs are called clocked-sequential circuits. They are stable and

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Department of Computer Science 241 CSM-4

their timing can easily be broken down into independent discrete steps, each of which is
considered separately.

a) Synchronous
The same clock signal is applied to each flip-flop, and changes in state occur when the
clock changes state from one level to another.

b) Asynchronous
The behavior of an asynchronous circuit depends on the order in which the inputs change.
Sometimes, there is an input labeled clock, that provides some level of synchronization,
but it is normally only applied to one flip-flop. In addition to this style of asynchronous
circuit, you also get gate-level asynchronous circuits, which are combinatorial circuits
with feedback.

Flip-Flops & Latches:

"Flip-flop" is the common name given to two-state devices which offer basic memory for
sequential logic operations. Flip-flops are heavily used for digital data storage and transfer
and are commonly used in banks called "registers" for the storage of binary numerical
data.
Types of Flip-Flops
There are several types of flip-flops and they are R-S, J-K, D and T flip-flops, but the two
most important kinds are the D and J-K flip-flops.
SR latch

Part1: D Flip-Flop:
- Construct D Flip-Flop using KL-33008 block d as shown then test the results.

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Department of Computer Science 241 CSM-4

Part2: JK Flip-Flop:
- Construct JK Flip-Flop using KL-33008 block d as shown then test the results.

Part3: T Flip-Flop:
- Construct T Flip-Flop using KL-33008 block d, then test the results.

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Department of Computer Science 241 CSM-4

Part4: RS Latch & RS Flip-Flop:

- Construct RS Latch using KL-33008 block d, then test the results.

Construct RS Flip-Flop using KL-33008 block d, then test the results.

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