US006952174B2

(12) United States Patent (10) Patent N0.: US 6,952,174 B2

Madsen et al. (45) Date of Patent: Oct. 4, 2005

(54) SERIAL DATA INTERFACE 5,815,102 A 9/1998 Melanson

5,838,801 A 11/1998 Ishige et a1.
(75) Inventors: Jesper Steensgaard Madsen, Carlsbad, 6,023,517 A 2/2000 Ishige
CA (US); Shouri Chatterjee, New
_
2733272; g1 * 2588(1) Beige
, , 0 a ........................ ..
341/59
goriqkNg 8252615))“ Arne Lagervan’ 6,240,193 B1 * 5/2001 Green 381/314
ar 5 a ’ 6,668,292 B2 * 12/2003 Meyer et al. ............... .. 710/61

(73) Assignee: Microsemi Corporation, Irvine, CA FOREIGN PATENT DOCUMENTS

(Us) EP 0 308 194 A2 3/1989
(*) Notice: Subject to any disclaimer, the term of this EP 0 569 989 A2 11/1993
patent is extended or adjusted under 35 OTHER PUBLICATIONS
U.S.C. 154(b) by 324 days. _ _
Magrath, A]. et al; “Design and Implementation of A FPGA
_ Sigma—Delta PoWer DAC”, IEEE Workshop on Leicester,
(21) Appl' NO" 10/237’992 UK Nov. 3—5, 1997 Signal Processing Systems, 1997 pp.
(22) Filed: Sep. 9, 2002 511—521~
_ _ _ Ramprasad, Sumant, et al; “A Coding Framework for LoW—
(65) Pnor Pubhcatlon Data PoWer Address and Data Busses” IEEE Transactions on
Us 2OO3/O2235O2 A1 Dec 4 2003 Very Large Scale Integration (VLSI) Systems, pp. 212—221,
7 no date given.
Related US. Application Data * Cited by examiner
(60) Provisional application No. 60/318,457, ?led on Sep. 10,
2001, and provisional application No. 60/318,229. Primary Examiner—Brian Young
7 (74) Attorney, Agent, or Firm—Jackson Walker L.L.P.;
........................................... Michael Cameron, Esq‘; Robert Khnger, Esq.

(58) Field Of Search ............................ .. 341/50, 51, 63, (57) ABSTRACT

341/67; 710/61’ 58’ 305’ gig/331243’ A method of encoding a ?rst stream of digital signal data
’ ’ Words is provided. A most recent value of the ?rst stream of
(56) References Cited digital signal data Words is received and memorized. A
previous value of the ?rst stream of digital data Words is
US. PATENT DOCUMENTS received and memorized. The most recent and the previous
values of the stream of digital data Words are combined to
4,553,130 A * 11/1985 Kato ......................... .. 341/67
Kick et a1.
create a second data stream. The Words are converted in the
5,495,242 A 2/1996
5,500,902 A 3/1996 Stockham, Jr. et a1. second data stream into a serial representation. The serial
5,515,443 A 5/1996 Meyer representation is transmitted on a single Wire interface.
5,710,819 A 1/1998 Topholm et a1.
5,748,684 A * 5/1998 Sanchez ................... .. 375/357 30 Claims, 6 Drawing Sheets

Electrical Shield (metal container)

Clock signal: c(t)
l l l
Trans-
76
/ w(t)
l . d'lkl
l . Clock
miner 1 eceiver 7 D5? Driver eneramr

\68 =i.\
i72 \56 \58 \78 \74
70
l
U.S. Patent Oct. 4,2005 Sheet 1 0f 6 US 6,952,174 B2

54 56 58
52

Acoustic
/ Di git a1 Acoustic
ADC DSP 7

Driver
Wave Wave
Microphone

Figure 1 (PRIOR ART)

Acoustic
Wave

Membrane
60

Figure 2 (PRIOR ART)

U.S. Patent 0a. 4,2005 Sheet 3 0f 6 US 6,952,174 B2

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U.S. Patent 0a. 4,2005 Sheet 6 6f 6 US 6,952,174 B2

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 US 6,952,174 B2
1 2
SERIAL DATA INTERFACE system in FIG. 3 further comprises receiver 72, DPS circuit
56, digital driver 58, clock generator 78, and battery 74.
PRIORITY CLAIM HoWever, such a system suffers various shortcomings
This application claims priority of US. Provisional Patent Which are associated With such data interfaces. Speci?cally,
Application No. 60/318,229 ?led on Sep. 7, 2001, entitled the small physical siZe of metal container 62 limits the
“Serial Data Interface,” and US. Provisional Patent Appli number of Wires that can be used to connect the metal
cation No. 60/318,457 ?led on Sep. 10, 2001, entitled container to other elements in the hearing aid. A typical
“Serial Data Interface”, the teachings are incorporated requirement is that the information-carrying signal be trans
herein by reference. mitted over single Wire interface 76. The physical dimen
10 sions of interface 76, hoWever, are far greater than those
TECHNICAL FIELD characteristic of interconnections betWeen circuit blocks on
The present invention relates to electrical circuit inter a monolithic integrated circuit Hence, the interface is subject
faces and, more speci?cally, to encoding signals for loW to a substantial capacitive load 70 to ground. Capacitive load
poWer serial transmission over a single-Wire interface. 70 is highly undesirable because this substantial capacitive
15 load Will cause the transmitter to drain a substantial amount
BACKGROUND OF THE INVENTION of energy from battery 74 every time interface 76 is charged
from a loW voltage to a higher voltage. Transmitter 68 Will
Digital data is transmitted via serial interfaces in a great thus consume a signi?cant amount of poWer if interface 76
number of applications, for eXample, an Ethernet, a digital is carrying a high bit rate. Therefore, it Would be advanta
telephone system, and various digital audio systems. PoWer 20 geous to have a method and system to substantially reduce
consumption is typically a very important parameter in the poWer consumption of the transmitter that Will substan
portable applications, such as, for example, hearing aids. tially reduce the poWer consumption Without any loss of
FIG. 1 shoWs the main components of a digital hearing aid data.
50. In this eXample, microphone 52 receives an acoustic
Wave and transforms the acoustic Wave into an analog 25 SUMMARY OF THE INVENTION
electrical signal. Analog-to-digital converter (ADC) 54 con
verts the analog electrical signal into digital form. Digital The present invention achieves technical advantages as an
signal processor (DSP) 56 processes the digital signal encoding/decoding system that substantially reduces the
according an audiologist’s prescription. Then digital driver poWer required to communicate digital data over a serial
58 converts the processed digital signal into an acoustic 30
interface With an appreciable capacitive load. A novel and
Wave directed toWard a patient’s ear. Microphone 52, shoWn improved Way to design and operate a transmitter and
in FIG. 2, is generally a capacitive type microphone. Small receiver is disclosed.
metal container 62 is sealed on one side (not necessarily an According to one aspect of the present invention, a serial
air-tight seal) by conductive membrane 60 Which is interface is provided With a reduced poWer consumption.
de?ected When an acoustic Wave applies force upon the 35 According to another aspect of the present invention, a
conductive membrane. Conductive membrane 60 and metal serial interface is provided for use in portable applications,
container 62 are electrically isolated from one another, and such as, for eXample, hearing aids.
the tWo-terminal system represents a capacitive structure. According to a further aspect of the present invention, a
An electrical ?eld exists betWeen the tWo capacitive plates, serial interface is provided that is optimiZed for data being
i.e., betWeen conductive membrane 60 and metal container 40 transmitted.
62, and a time varying electrical voltage signal is thus
created betWeen the tWo plates When conductive membrane According to a further aspect of the present invention, a
60 vibrates. This produced electrical signal can provide only serial interface is provided that automatically synchroniZes
a small amount of poWer, and is therefore sensitive to during normal operation.
electrical noise and other disturbances. The metal container 45 According to a further aspect of the present invention, a
is generally connected electrically to the system’s ground, serial interface is provided Which does not require a phase
for eXample, a battery’s negative terminal. A cavity inside locked loop (PLL) for clock synchroniZation.
metal container 62 is thereby, to a large eXtent, shielded from Further advantages Will become apparent from a consid
interference from unWanted electrical ?elds that may sur eration of the ensuing description, draWings and claims.
round microphone 52. Asmall integrated circuit (not shoWn) 50
located inside metal container 62 ampli?es the signal before BRIEF DESCRIPTION OF THE DRAWINGS
the signal leaves the shielded environment. In advanced For a better understanding of the invention including its
products, the signal is not only ampli?ed, but also analog features, advantages and speci?c embodiments, reference is
to-digital (A/D) converted inside metal container 62. The made to the folloWing detailed description along With
advantage of this procedure is that digital signals are virtu 55 accompanying draWings in Which:
ally immune to noise interference, and hence can be routed
FIG. 1 is an illustration of the main components of a
outside metal container 62 Without any loss of performance.
Subsequent digital signal processing implemented by DSP digital hearing aid;
circuit 56 should preferably be located outside metal con FIG. 2 is an illustration of a microphone in greater detail;
tainer 62, i.e., the digital signal processing should be sepa 60 FIG. 3 is an illustration of a system-level schematic of a
rated from noise sensitive circuits near microphone 52. digital hearing aid Where an ADC is placed inside the
FIG. 3 shoWs a system-level electrical schematic of a microphone’s metal container;
digital hearing aid Where the ADC 54 is placed inside the FIG. 4 is a an illustration of hoW codes are deciphered
microphone’s metal container 62. The microphone is elec from a voltage signal applied to the interface by the trans
trically represented by voltage source 64 With a capacitive 65 mitter in accordance With the present invention;
output impedance. Inside the shielding metal container are FIG. 5 illustrates the operation of a transmitter in accor
buffer circuit 66, A/D converter 54, and transmitter 68. The dance With the present invention,
 US 6,952,174 B2
3 4
FIG. 6 is an illustration of the operation of a state machine beloW lists hoW the four codes are represented and inter
implementing the receiver 72 in accordance With the present preted.
invention;
FIG. 7 is an illustration of a gate-level implementation of 5
a transmitter in accordance With the present invention; Value of W(t) at the rising Value of W(t) at the faing
edge of the clock signal edge of the clock signal
FIG. 8 illustrates a timing diagram for a serial data c(t) c(t) Interpreted as
interface in accordance With the present invention; and lOW or “O” lOW or “O” code-O or “00”
lOW or “0” high or “1” code-1 or “01”
FIG. 9 illustrates a gate level implementation of a receiver 10 high or “1” lOW or “O” code-2 or “10”
in accordance With the present invention. high or “1” high or “1” code-3 or “11”

References in the detailed description correspond to like

references in the ?gures unless otherWise noted. In this conventionally designed interface, the four codes
15 represent each one of the four numerical values that the
digital signal d(k) is composed of. Receiver 72 then simply
DETAILED DESCRIPTION OF PREFERRED translates the received codes to the corresponding numerical
EMBODIMENTS values and communicates that translation to DSP circuit 56.
This conventional approach, hoWever, implies that transmit
While the making and use of various embodiments of the ter’s 68 poWer consumption Will be relatively high. This
present invention are discussed in detail beloW, it should be implication is a consequence of the nature of the signal d(k)
appreciated that the present invention provides applicable produced by delta-sigma ADC 54: even for constant input
inventive concepts Which can be embodied in a Wide variety signals, d(k) Will constantly ?uctuate betWeen tWo or more
of speci?c contexts. numerical values. The corresponding frequent ?uctuation
betWeen codes implies that interface 76, With the interface’s
One embodiment of the present invention is a serial 25 76 capacitive load 70, Will be charged and discharged
interface that encodes data according to a speci?c frequently. This frequent charging and discharging of the
application, such as the application shoWn in FIG. 3. A/D interface’s capacitive load 70 is associated With a relatively
converter 54 is based on a delta-sigma principle. The A/D high poWer consumption.
converter produces a stream of loW resolution Words, i.e., a To reduce the poWer consumption, the present invention
sequence of codes each representing a numerical value, at a advantageously encodes d(k) in a different manner, such as
rate Which is substantially higher than the Nyquist rate, ie., to reduce the frequency at Which the interface 76 is charged
tWice the signal’s bandWidth. In this embodiment, the digital and discharged.
Word rate (sampling frequency) is 2 MHZ although the ADC 54 produces a data stream d(k) Which may be
signal bandWidth is only 10 kHZ. In other Words, the over composed exclusively of the folloWing numerical values:
sampling ratio (OSR) may be expressed as: (+8), (+1), (—1), and (—8). It is particularly important to note
at this point that the poWer consumption is small When the
input signal is small, i.e., When the hearing aid, for example,
OSR — *2
MHZ — 100
_ 2X10 kHz _
is used in a relatively quiet environment. This type of use for
the hearing aid is generally the case for more than 90% of
40 the time the hearing aid is in operation. For such small
Delta-Sigma A/D converters generally produce digital signals, conventional delta-sigma ADCs tend to produce
Words of very loW resolution. Sometimes the resolution of signals d(k) Which quantitatively maybe of the type:
the Words is only one bit i.e., each Word has one of only tWo d(k)= ' ' ' >(+1)>(_1)>(+1)>(_1)>(+1)’(_1)>(_1)>(+1)>(_1)>

possible numerical values, in Which case transmitter 68 in (+1), (—1), (+1)(—1), . . .

FIG. 3 could be a simple digital buffer circuit. Transmitter 68
45 In other Words, the signal d(k) primarily alternates
betWeen the numerical values of (+1) and (—1) in betWeen
may consume signi?cant poWer in charging and discharging short sequences of constant (+1) or (—1). The sequences of
capacitive load 70 if such a single-bit data stream Were to be identical values are rarely more than 2 or 3 samples long.
transmitted directly on the interface 76. In this embodiment, Based on this observation, to reduce the poWer consumption,
hoWever, delta-sigma ADC 54 advantageously produces the present invention advantageously includes transmitter 68
digital Words each With a resolution of tWo bits. In other designed to generate a code “00” every time the signal
Words, ADC 54 produces a stream of data Words in Which transitions either from (+1) to (—1) or from (—1) to (+1). If
each data Word may have one of four prede?ned numerical a (+1) folloWs a (+1), or a (—1) folloWs a (—1), transmitter 68
values. Hence, in each clock cycle, one of four codes produces the code “11”. Hence, for the above data sequence,
(code-0, code-1, code-2, or code-3) may be transmitted over 55 the transmitter produces the folloWing sequence of codes:
interface 76 While the signal has only tWo valid voltage . , ‘2?, 00, 00, 00, 00, 00, 11, 00, 00, 00, 00, 00, 00, 11,
levels. 00, . . .

Interface 76 is charged and discharged much less fre

FIG. 4 shoWs hoW the codes are deciphered from a
quently than if conventional encoding (Where each code
voltage signal W(t) applied to interface 76 by the transmitter represents a speci?c numerical value) Was used. As a result,
68 in accordance With the present invention. Receiver 72 the poWer consumption is reduced substantially.
detects a logical value (high/loW voltage levels are respec Receiver 72 is able to reconstruct the signal d*(k)=d(k).
tively interpreted as logical values 1/0) of W(t) at both a Observe that tWo different signals:
rising and falling edge of a clock signal c(t). For example, d1(k)= ' ' ' >(+1)>(_1)> (+1)>(_1)>(+1)> (_1)>(_1)>(+1)> (_1)>
if W(t) is loW at the rising edge of c(t) and W(t) is high at the (+1), (—1), (+1), (—1), (—1), . . . and
falling edge of c(t), the receiver interprets the data as a d2(k)= ' ' ' >(_1)>(+1)> (_1)>(+1)>(_1)> (+1)>(+1)>(_1)> (+1)>
message corresponding to code-1 (code “01”). The table (—1), (+1), (—1), (+1), (+1), . . .
 US 6,952,174 B2
5 6
Will produce the same sequence of codes mentioned above. described in Table 2, Which effectively de?nes receiver’s 72
In other Words, receiver 72 Will not inherently be able to operation.
detect the polarity of the signal, the receiver 72 Would only
be able to guarantee d*(k)=:d(k). In some applications, the TABLE 2
absolute phase is arbitrary (in Which case this encoding Code Received Previous State New State Output Value
scheme Would be splendid), Whereas it is of crucial impor W(t) d*(k — 1) d*(k) d*(k)
tance in other applications, such as in directional hearing “01” (-8) (-8) (-8)
aids, for eXample. “01” (-1) (-8) (-8)
10
“01” (+1) (—8) (—8)
Correct phase can be guaranteed if transmitter 68 and “01” (+8) (—8) (—8)
“00” <-8> <-1> <-1>
receiver 72 are synchroniZed by some sort of reset event. “0O” (—1) (+1) (+1)
According to the present invention, such a reset event “00” (+1) <-1> <-1>
advantageously occurs relatively frequently to assure satis “00” (+8) (—1) (—1)
“11” (—8) (+1) (+1)
factory performance in the very rare event that a bit error 15 “11” <-1> <-1> <-1>
should occur. In this embodiment, synchroniZation is guar “11” (+1) (+1) (+1)
anteed every time d(k) attains a numerical value of either “11” (+8) (+1) (+1)
“10” (—8) (+8) (+8)
(+8) or (-8). “10” (—1) (+8) (+8)
“10” (+1) (+8) (+8)
In practice, transmitter 68 may be implemented as a “10” (+8) (+8) (+8)
digital state machine With four possible states: (-8), (-1),
(+1), and (+8). The state machine is clocked once every FIG. 6 is an illustration of the operation of a state machine
clock cycle. The state machine alWays transitions to the state implementing the receiver 72 in accordance With the present
that corresponds to the value of d(k) (for simplicity the four invention. In this eXample, each of the four states are
states are named according to the value of d(k)). The state 25 represented by an oval. Each arc represents a transition from
machine’s operation is described in Table 1, Which effec one state to the neXt, i.e., starting from d*(k-1) and leading
tively de?nes the operation of transmitter 68. to d*(k). The annotation of each arc identi?es the received
code. Note that When receiving code “01”, the state machine
TABLE 1 Will alWays transition to state (-8), i.e., regardless of What
the previous state Was. Likewise, note that When receiving
Input value Previous state NoW state Code Generated code “10”, the state machine Will alWays transition to state
D(k) d(k - 1) d(k) W0) (+8).
(-8) (-8) (-8) “01” Advantageously, according to Table 1 above, transmitter
(-8) (-1) (-8) “01” 68 Will only generate code “01” When it transitions to state
(-8) (+8) (-8) “01” 35 (+8), and likewise, transmitter 68 Will only generate code
(-1) (+8) (-1) “01” “10” When it transitions to state (-8). Hence, the tWo state
(-1) (-8) (-1) “00” machines implementing respectively transmitter 68 and
(-1) (-1) (-1) “11”
(-1) (+1) (-1) “00” receiver 72, Will synchroniZe every time d(k) attains a
(-1) (+8) (-1) “00” numerical value of either (-8) or (+8). Synchronization Will
(+1) (—8) (+1) “11” 40 thus take place relatively frequently (Which makes the
(+1) (—1) (+1) “00” system tolerant to bit errors) Without disrupting the normal
(+1) (+1) (+1) “11”
(+1) (+8) (+1) “11” operation. To obtain immediate synchroniZation in a poWer
(+8) (—8) (+8) “10” up situation, it is preferable that the ?rst numerical value of
(+8) (—1) (+8) “10” d(k) is forced to be either (+8) or (-8). Once the tWo state
(+8) (+1) (+8) “10” 45 machines are synchroniZed, they Will remain synchroniZed
(+8) (+8) (+8) “10”
(+8) (+8) (+8) “10” (Which can be seen from Tables 1 and 2).
Gate Level Implementation (Transmitter)
FIG. 7 is an illustration of a gate-level implementation of
The operation of transmitter 68 is illustrated in FIG. 5. In a transmitter 68 in accordance With the present invention. In
this example, each of the four states are represented by an this eXample, the digital input signal d(k) provided by ADC
54 is encoded in a “one-of” fashion, Where only one line in
oval. Each arc represents a transition from one state to the
the 4-bit bus is logically high at any time. A digital code
next, i.e., starting from d(k-1) and leading to d(k). The representing d(k) is clocked into a ?rst set of ?ip-?op
annotation of each arc identi?es the code that is transmitted. circuits 80 slightly after (eg., 6 gate delays) the clock
Note that for each state, the transitions to each of the four 55 signal’s c(t) rising edge. The digital codes “11”, “10, “01”,
possible states, neW states are associated With each a unique and “00” are used to represent the folloWing numerical
code. Note also that all transitions to the state (-8) Will values for d(k): (+8), (+1), (-1), and (-8). The outputs from
produce the unique code “01”, and similarly that all trans the ?rst set of ?ip-?op circuits 80 are connected directly to
actions to the state (+8) Will produce the unique code “10”. the inputs of a second set of ?ip-?op circuits 82A and 82B
The combination of these tWo properties facilitates robust Which are clocked simultaneously With the ?rst set of
reconstruction of d(k) on the basis of the transmitted codes. ?ip-?op circuits 80.
The tWo sets of ?ip-?op circuits 80, 82A and 82B store
Receiver 72 is implemented as a state machine. This state 2><2 bit codes representing respectively d(k) and d(k-1).
machine also has four possible states: (-8), (-1), (+1), and According to Table 1, these four bits of information are
(+8). These states are named according to the corresponding 65 suf?cient to determine Which digital code that should be
numerical values of the output signal d*(k), Which is the transmitted on interface 76. The actual encoding is per
anticipated value of d(k). The state machine’s operation is formed by a small netWork of logic gates 84. TWo logical
 US 6,952,174 B2
7 8
signals WR and WF attain the logical values that the receiver the possible values of d(k) are assigned a speci?c code
should detect at respectively rising and falling edges of the transmitted on the interface. The results are summariZed in
clock signal c(t). Asingle bit ?ip-?op circuit 86 produces the Table 4.
actual output signal Waveform W(t). The ?ip-?op circuit 86
is clocked at every rising and falling edge of c(t). A small TABLE 4
edge detecting circuit 88 produces a short duration pulse at
each edge of c(t), Which is used to clock the ?ip-?op circuit Signal Level Relative to Transitions Standard Transitions New
86. The output ?ip-?op circuit 86 Will, at the rising edge of Full Scale Interface Interface
c(t), clock in and apply to interface 76 the value generated —1OO Db 1448/ms 608/ms
When c(t) is loW, i.e., WF. Similarly, at the falling edge of —8O Db 1429/ms 574/ms
c(t), the ?ip-?op circuit 86 Will clock in the value generated —6O Db 1401/ms 569/ms
When c(t) is high, i.e., WR. —4O Db 1451/ms 598/ms
FIG. 8 illustrates a timing diagram for a serial data —2O Db 1456/ms 599/m
O Db 701/ms 1350/ms
interface in accordance With the present invention. To assure
a suf?ciently long hold time for the output ?ip-?op circuit
86, the preceding netWork of ?ip-?op circuits 80, 82A, and 15 As expected, the poWer consumption depends on the input
82B and logic gates 84 are driven by the delayed clock signal level. Table 4 lists the number of transitions that
signals, clk and m. Receiver 72 evaluates the voltage W(t) occurred on interface 76 in a millisecond using a 2 MHZ
on interface 76 at the rising and falling edges of c(t). Notice clock signal. The standard interface is characteriZed by, on
that receiver 72 at any rising edge of c(t) detects the ?rst bit average, approximately 0.7 transitions per clock cycle. This
WR(k) in the code representing the sample d(k) that Was is representative for conventional delta-sigma modulators
clocked into the ?rst set of ?ip-?op circuits 80 one clock since these modulators constantly alternate betWeen the
cycle earlier. Similarly, receiver 72 Will at any falling edge available codes. Using the neW interface, the average num
of c(t), detect the second bit WF(k) in the code representing ber of transitions per clock cycle on interface 76 are reduced
the sample that Was clocked into the ?rst set of ?ip-?op to approximately 0.3, in other Words, for typical signal levels
circuits 80 one and one-half clock cycles earlier. AfeW clock 25 (the signal level Will only occasionally exceed —20 Db of full
cycles of latency is quite acceptable in an interface for this scale), the number of transitions are advantageously reduced
type of application. by a factor of approximately 2.5.
Gate Level Implementation (Receiver) For the used technology, the present invention requires
FIG. 9 illustrates a gate level implementation of a receiver approximately 20 uA/MHZ to drive interface Wire 76 With a
in accordance With the present invention. In this example, a 5 pF capacitive load 70. Hence, Without the encoding,
third set of ?ip-?op circuits 90A and 90B detect and store the transmitter’s 68 current consumption Would be in the order
logical values of W(t) at respectively the rising and falling of 28 uA. When the encoding scheme is used, transmitter’s
edges of c(t). It is important that the third set of ?ip-?op 68 current consumption is reduced to approximately 14 uA,
circuits 90A and 90B are clocked directly by c(t) or by including the poWer needed to operate the described cir
induced clock signals that have a minimum of delay With 35 cuitry. The saved 14 uA constitutes more than 10% of the
respect thereto. The inputs of a fourth set of ?ip-?op circuits total current consumed by buffer 66, ADC 54, and transmit
92A and 92B are connected directly to the outputs of the ter 68. The neW serial interface, therefore, represents a
third set of ?ip-?op circuits 90A and 90B. Accordingly, the substantial overall improvement of the system.
tWo logical signals DR and DF represent the detected logical Therefore, from the foregoing description of the present
values of W(t) at respectively the rising and falling edges of 40 invention, this invention substantially reduces the poWer
c(t). The timing of these signals is shoWn in FIG. 8. A ?fth consumption of a serial interface. The transmitter’s 68
set of ?ip-?op circuits 94 stores the output signal, i.e. the poWer consumption may be reduced by as much as a factor
expected value d*(k) of d(k). The encoding scheme used for of tWo. The savings are a substantial fraction of the system’s
d*(k) is shoWn in Table 3. overall poWer consumption. The reduced poWer consump
tion translates into longer battery life, Which is a substantial
advantage for hearing aids and other portable applications.
The interface is self-synchronizing, Which makes it robust to
bit errors and easy to use.
While the above description contains many speci?cities,
these should not be construed as limitations of the scope of
the present invention, but rather as an exempli?cation of
preferred embodiments thereof. Many other variations are
possible. For example, a different set of codes may be used
According to Table 2, the state machine’s next state and to represent transitions in the state machines, the delta-sigma
output value d*(k) is a function of the received code and the 55 modulator may have more or less than 4 quantization levels,
previous state d*(k—1). These four bits of information are the delta-sigma modulator’s quantiZation levels may have a
stored in the ?ip-?op circuits 92A, 92B and 94. A small different set of values, for example, :1 and :3, :1 and :32,
netWork of logic gates 96 perform the necessary decoding, and the like, the interface may be used in other medical
as described by Table 2, and the neW state and output value applications With other types of transducers, in cellular
d*(k) is clocked into the ?ip-?op circuits 94 at the rising phones, for audio and non-audio equipment, With or Without
edges of c(t). FIG. 8 shoWs the overall timing diagram. a shielding environment, and in many other applications
Performance Evaluation such as, for example, electronic tape measures. Those Who
The described embodiment of the present invention has are skilled in the art Will understand that the state machines
been designed and simulated extensively. This embodi used to illustrate a preferred embodiment of this invention is
ment’s operation is very robust and no errors Were detected. 65 merely and example of such systems, they can be designed
To evaluate the encoding scheme’s ef?ciency, a compari in a great number of Ways. The underlying technology can
son Was made to a traditional serial interface Where each of be, for example, CMOS, BJT, BiCMOS or any other current
 US 6,952,174 B2
10
or future technology suitable for the implementation of Wherein said conversion circuit provides said output data
integrated circuits. In fact, this invention should not be stream such that the polarity of said output data stream
construed as limited to electric circuit, future signal pro is ascertainable by a receiver.
cessing platforms, possibly biochemical, may take advan 6. An encoder, comprising:
tage of such encoding schemes for data communications. 5 an input adapted to receive digital input data stream;
Accordingly, the scope of the invention should be deter
mined not by the described embodiments, but by the a conversion circuit adapted to convert said digital input
appended claims and their legal equivalents. data stream into an output data stream composed of at
What is claimed is: least 2-bit codes, Wherein said conversion circuit gen
1. An encoder, comprising: erates said codes as a function of transitions of said
10 input data stream, Wherein each bit of said code have
an input adapted to receive a digital input data stream;
a conversion circuit adapted to convert said digital input the same voltage level When said digital input data
data stream into an output data stream composed of at stream alternates betWeen tWo prede?ned numeric val
least 2-bit codes, Wherein said conversion circuit gen ues; and
erate said codes as a function of transitions of said input Wherein a predetermined code is generated every time the
15
data stream, Wherein each bit of said code have the input data stream comprises a predetermined numeric
same voltage level When said digital input data stream value.
alternates betWeen tWo prede?ned numeric values; and 7. The encoder as speci?ed in claim 6 Wherein said
said output data stream being composed of codes having predetermined numeric value is a representative of the
each 2 bits of resolution. largest absolute value that can be represented by said input
2. An encoder, comprising: data stream.
an input adapted to receive a digital input data stream; 8. An encoder, comprising:
a conversion circuit adapted to convert said digital input an input adapted to receive a digital input data stream;
data stream into an output data stream composed of at a conversion circuit adapted to convert said digital input
least 2-bit codes, Wherein said conversion circuit gen data stream into an output data stream composed of at
erates said codes as a function of transitions of said 25
input data stream, Wherein each bit of said codes have least 2-bit codes, Wherein said conversion circuit gen
erates said codes as a function of transitions of said
the same voltage level When said digital input stream
alternates betWeen tWo prede?ned numeric values; and input data stream, Wherein each bit of said code have
Wherein said digital input data stream is composed of the same voltage level When said digital input data
stream alternates betWeen tWo prede?ned numeric val
values proportional to values chosen from the set of
minus eight, minus one, plus one, and plus eight. ues; and
3. An encoder, comprising: Wherein said conversion circuit is a state machine;
an input adapted to receive a digital input data stream; Wherein said state machine starts at a predetermined state
a conversion circuit adapted to convert said digital input at initialiZation of said digital input serial data stream;
data stream input an output data stream composed of at 35 and
least 2-bit codes, Wherein said conversion circuit gen Wherein said conversion circuit synchroniZes everytime
erates said codes as a function of transitions of said said output data stream as a predetermined state.
input data stream, Wherein each bit of said codes have 9. An encoder, comprising:
the same voltage level When said digital input data an input adapted to receive a input digital data stream;
40
stream alternates betWeen tWo prede?ned numeric val a conversion circuit adapted to convert said input digital
ues; and data stream into an output data stream composed of at
Wherein said codes are represented by 00, 01, 10 and 11. least 2-bit codes, Wherein said conversion circuit gen
4. An encoder, comprising: erates said codes as a function of transitions of said
an input adapted to receive a digital input data stream; input digital data stream, Wherein each bit of said codes
45
a conversion circuit adapted to convert said digital input have the same voltage level When said input digital data
data stream input an output data stream composed of at stream alternates betWeen tWo prede?ned numeric val
least 2-bit codes, Wherein said conversion circuit gen ues;
erates said codes as a function of transitions of said an ADC generating said input digital data stream; and
input data stream, Wherein each bit of said codes have Wherein said output data stream is provided at a rate
the same voltage level When said digital input data substantially higher than tWice the signal bandWidth of
stream alternates betWeen tWo prede?ned numeric val said ADC.
ues; and 10. The encoder as speci?ed in claim 9 Wherein said ADC
Wherein said conversion circuit compares a previous converter comprises a delta-sigma modulator.
value of said digital input data stream With a most 11. The encoder as speci?ed in claim 9 Wherein said ADC
recent value of said digital input data stream to generate is disposed With a hearing aid.
said input data stream. 12. A method of encoding a ?rst stream of digital signal
5. An encoder, comprising: data Words, comprising the steps of:
an input adapted to receive a digital input data stream; receiving and storing a most recent value of said ?rst
a conversion circuit adapted to convert said digital input stream of digital date Words;
data stream input an output data stream composed of at receiving and storing a previous value of said ?rst stream
least 2-bit codes, Wherein said conversion circuit gen of digital data Words;
erates said codes as a function of transitions of said comparing said most recent value and said previous value
input data stream, Wherein each bit of said codes have of said stream of digital data Words to create a second
the same voltage level When said digital input data data stream having at least 2-bit Words;
stream alternates betWeen tWo prede?ned numeric val providing the Words in said second data stream in a serial
ues; and representation;
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11 12
transmitting said serial representation on a single Wire predetermined code to establish synchroniZation at initial
interface; iZation of said digital input serial data stream.
synchronizing a transmission of said serial representation 21. The method as speci?ed in claim 20 Wherein a phase
With edges of a received clock signal; of said output data stream is ascertainable upon a reset event.
composing said second s am of digital data Words in 22. A method of operating an encoder, comprising the
tWo-bit digital data Words; and steps of:
generating said ?rst stream of digital data by analog-to receiving a digital input serial data stream;
digital conversion of an audio signal. converting by a conversion circuit of a state machine said
13. The method of claim 12 Wherein the analog-to-digital digital input serial data stream to at least a 2-bit code,
conversion of an audio signal comprises the step of using a Wherein said code is generated as a function of a
delta-sigma modulator. transition of said digital input serial data stream, and
14. The method of claim 12 Wherein said delta-sigma also a function of a lack of a transition of said digital
modulator is disposed inside a microphone. input serial data stream, Wherein each bit of said code
15. The method of claim 14 Wherein said microphone is has the same voltage level When said digital input serial
15
disposed in a hearing aid. data stream transitions;
16. A method of operating an encoder, comprising the Wherein said state machine starts at a predetermined state
steps of: at initialiZation of said digital input serial data stream;
receiving a digital input serial data stream; and
converting said digital input serial data stream to at least Wherein said conversion circuit synchroniZes everytime
a 2-bit code, Wherein said code is generated as a said output data stream has a predetermined state.
function of a transistion of said digital input serial data 23. A method of operating an encoder, comprising the
stream, and also as a function of a lack of a transition steps of:
of said digital input serial data stream, Wherein each bit receiving a digital input serial data stream;
of said code has the same voltage level When said 25 converting said digital input serial data stream to at least
digital input signal data stream transitions; and a 2-bit code comprising an output data stream, Wherein
Wherein said predetermined code is digital 11. said code is generated as a function of a transition of
17. A method of operating an encoder, comprising the said digital input serial data stream, and also a function
steps of: of a lack of a transition of said digital input serial data
receiving a digital input serial data stream; stream, Wherein each bit of said code has the same
converting said digital input serial data stream to at least voltage level When said digital input serial data stream
a 2-bit code, Wherein said code is generated as a transitions;
function of a transition of said digital input serial data Wherein said output data stream comprises a sequence of
stream, and also as a function of a lack of a transition codes at a rate substantially higher than the Nyquist
of said digital input serial data stream, Wherein each bit rate.
of said code has the same voltage level When said 24. A method of operating an encoder, comprising the
digital input serial data stream transitions; and steps of:
Wherein said predetermined code is digital 00. receiving a input digital serial data stream;
18. A method of operating an encoder, comprising the converting said input digital serial data stream to at least
40
steps of: a 2-bit code, Wherein said code is generated as a
receiving a digital input serial data stream; function of a transition of said input digital serial data
converting said digital input serial data stream to at least stream, and also as a function of a lack of a transition
a 2-bit code, Wherein said code is generated as a of said input digital serial data stream, Wherein each bit
function of a transition of said digital input serial data 45 of said code has the same voltage level When said input
stream, and also as a function of a lack of a transition digital serial data stream transitions;
of said digital input serial data stream, Wherein each bit using an ADC to generate said input digital serial data
of said code has the same voltage level When said stream and
digital input serial data stream transitions; and
Wherein said ADC converter comprises a delta-sigma
Wherein said code is representative of a digital code 00, modulator.
01, 10 and 11.
25. A method of operating an encoder, comprising the
19. A method of operating an encoder, comprising the
steps of:
steps of:
receiving a digital input serial data stream; receiving a digital input serial data stream;
converting by a conversion circuit said digital input serial 55
converting said digital input serial data stream to at least
data stream to at least a 2-bit code, Wherein said code a 2-bit code comprising an output data stream, Wherein
is generated as a function of a transition of said digital said de is generated as a function of a transition of said
input serial data stream, and also as a function of a lack digital input serial data stream, and also as a function
of a transition of said digital input serial data stream, of a lack of a transition of said digital input serial data
Wherein each bit of said code has the same voltage level stream, Wherein each bit of said code has the same
When said digital input serial data stream transitions; voltage level When said digital input serial data stream
and transitions;
Wherein said conversion circuit provides said output data a receiving circuit converting said output data stream to a
stream such that a phase of said output data stream is serial data stream.
ascertainable by a receiver. 26. A method of operating an encoder, comprising the
20. The method as speci?ed in claim 19 Wherein said steps of:
output data stream is set by the conversion circuit at a ?rst receiving a digital input serial data stream;
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13 14
converting said digital input serial data stream to at least 28. The encoder of claim 1, Wherein said conversion
a 2-bit code comprising an output data stream, wherein circuit adapted to provide said output data stream serially on
said code is generated as a function of a transition of a slngle Conductor
said digital input serial data stream, and also as a 29. The method as speci?ed in claim 19 Wherein said
function of a lack of a transition of said digital input 5 conversion circuit provides said output data stream a single
conductor.
serial data stream, Wherein each bit of said code has the 30. The method as speci?ed in claim 19 Wherein said
same voltage level When said digital input serial data conversion circuit compares a previous value of said digital
stream transitions; input serial data stream With a most recent value of said
Wherein Said digital input Serial data Stream 15 digitized digital input serial data stream to generate said output data
signals from a microphone. 1O stream.
27. The method as speci?ed in claim 26 Wherein said
microphone is disposed With a hearing aid. * * * * *