Gopi Krishna Saramekala

Assistant Professor

National institute of Technology Calicut

Course Outcomes:

CO1: Illustrate challenges faced by present CMOS

VLSI device design and fundamental limits of
operation.
CO2: Explain novel MOS based silicon devices and
various multi gate devices.
CO3: Develop knowledge about SOI devices.
CO4: Examine different nanoelectronic systems and
2D materials and Devices

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Module 1:
Challenges going to sub-100 nm MOSFETs – Oxide
layer thickness, tunneling, power density, non-uniform
dopant concentration, threshold voltage scaling,
lithography, hot electron effects, sub-threshold current,
velocity saturation, interconnect issues, fundamental
limits for MOS operation.

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Module 2:
Novel MOS-based devices – Multiple gate MOSFETs,
Silicon-on-insulator, FDSOI, vertical MOSFETs,
strained Si devices, FinFET, optoelectronic, and
spintronics devices, Heterostructure based devices –
Type I, II and III heterojunctions, Si-Ge heterostructure,
heterostructures of III-V and II-VI compounds -
Resonant tunneling devices (diodes & transistors)

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Module 3:
C a r b o n n a n o t u b e s b a s e d d e v i c e s – C N F E T,
characteristics, Hysteresis and device passivation,
Single Electron Memory, 2D materials and devices,
S p i n t r o n i c s - S p i n - b a s e d d e v i c e s – S p i n F E T,
characteristics

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References:
1. Waser Ranier, Nanoelectronics and Information
Technology (Advanced Electronic Materials and
Novel Devices). Wiley-VCH,3rd Edition 2012.

2. R. Saito and M. S. Dresselhus, Physical properties

of Carbon Nanotubes. Imperial College Press 1998

3. Francois Leonard, The Physics of Carbon Nanotube

Devices. William Andrew, 200

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 SCALING
SHORT CHANNEL EFFECTS

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 Downscaling of MOSFET

Why Scaling?

Challenges as feature size decreases

Dennard observes that transistor dimensions could be scaled by -30% (0.7x) every technology
generation, thus reducing their area by 50%. This would reduce circuit delays by 30% (0.7x)
and therefore increase operating frequency by about 40% (1.4x). Finally, to keep the electric
field constant, voltage is reduced by 30%, reducing energy by 65% and power (at 1.4x
frequency) by 50%. Therefore, in every technology generation, if the transistor density
doubles, the circuit becomes 40% faster, and power consumption (with twice the number of
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transistors) stays the same
 What is Short Channel?
• A MOSFET is considered to be short when the channel length
‘L’ is in the same order of magnitude as the depletion-layer
widths (xdD, xdS).
• The potential distribution in the channel depends on
– Transverse field (perpendicular to channel)
• controlled by the gate voltage and back-surface bias
– Longitudinal field (along the channel)
• controlled by the drain bias.

Long Channel Device Short Channel Device

xdS xdD

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Long Channel
• In conventional (Long channel) devices, electric field in the
longitudinal direction is low, so that the velocity of the carriers
is proportional to it. Hence, the current is not affected as the
drain voltage is increased above its saturation value.
• A one-dimensional analysis could be used.
• The gate oxide is a perfect insulator; and that the gate and
substrate currents are zero.

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Short Channel
• Now, we will allow the channel to become short. We will
study; what happens when the longitudinal field is so high that
the carrier velocity saturates.
• We will consider the effect of the drain voltage on the
saturation current.
• We will discuss what happens when the magnitude of the
electric field is so large that it imparts a large energy on the
carriers, which are then said to be “hot” and can result in
substrate current and oxide damage.
• We will also consider what happens when the gate oxide is
very thin.

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 Short Channel Effects

Ø Velocity saturation
Ø Drain-induced barrier lowering
Ø Punchthrough
Ø Hot carrier effects
Ø Direct gate oxide tunnelling

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 Carrier Velocity Saturation
• The phenomenon of velocity saturation is associated with drift
currents, and as such it will be discussed in the context of strong
inversion, where such currents are dominant.
• In weak inversion, current conduction is due to diffusion; the
lateral electric field in the channel is zero (in the ideal case) and
thus no drift current and velocity saturation are expected to occur.
• Let Ex be the value of the longitudinal component of the electric
field in the semiconductor, i.e., the component parallel to the
semiconductor-insulator interface.
• We have assumed that at all points in the inversion layer |E x | is
small enough so that the magnitude of the carrier velocity |vd| is
proportional to |Ex|.
• Although this assumption was useful in deriving our basic models,
it is not accurate for devices with short channels, or even for long-
channel devices at or near saturation. 13
 Carrier Velocity Saturation

• Ec = critical electric field,

the point at which the
velocity tends to saturate.
For silicon, is ~104 V/cm at
300 K.

• The velocity saturates when E≫Ec and it becomes vd=μEc=vd,max

(when E≪Ec, vd=μE as expected). In silicon, for electrons it is ~107
cm/s and for holes around 0.6*107 cm/s.
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 Carrier Velocity Saturation
• The velocity of charge carriers, such as electrons or holes, is
proportional to the electric field that drives them, but that is
only valid for small fields. As the field gets stronger, their
velocity tends to saturate before pinchoff

Where μ is the surface mobility i.e. the

mobility of carriers next to the
semiconductor-insulator interface; this
quantity is significantly lower than the
bulk mobility (e.g., by a factor of 2),
depends on the tranversal electric field
(normal field).
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 Carrier Velocity Saturation

tox = 1.5 nm, NA = 3 × l0l7cm-3,

W = 10 μm, L = 90 nm.

Characteristics, (a) in the absence and (b) in the presence of velocity saturation effect

For the same V GS , saturation is achieved at smaller values of V DS

when velocity saturation is included. Equally important, the spacing
of the curves in saturation no longer follows the “square law”
behavior. 16
 Drain-induced barrier lowering

• In short channel MOSFETs, the potential barrier is controlled by both the

gate-to-source voltage VGS and the drain-to-source voltage VDS.

• We assume a uniform substrate for simplicity, and Vsb = 0. Curve 1 shows

the situation when the gate voltage is equal to the flatband voltage and
Vd = Vs. The p-type substrate away from the source and drain is neutral,
and the total potential barrier encountered by electrons attempting to cross
into the channel is φbi, where φbi is the built-in potential of the source-body
and drain-body junctions.
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 Drain-induced barrier lowering
• This barrier is high, and practically no electrons in the n+ regions
have sufficient energy to cross it.
• When the gate voltage is increased (still maintaining Vd = Vs), the
surface potential becomes positive and the corresponding energy in
the channel is lowered, as shown by curve 2.
• This lowers the energy barrier, and many electrons enter the channel.
• Finally, if we keep the gate voltage at the same value as for curve 2,
but increase the drain voltage, the potential rises toward the right by
Vds.
• This corresponds to a lowering of Ec by an amount qVds as shown by
curve 3. Source electrons with enough energy to enter the channel
are now accelerated by the field toward the drain, and a drain current
is observed.
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 Drain-induced barrier lowering

• In short-channel, because the source and drain are both close

to the entire channel, their depletion regions approach each
other, and the field situation becomes two-dimensional.
• If the drain voltage is increased, the potential barrier in the
channel decreases, eventually allows electron flow between
the source and the drain, even if VGS<VT.

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 Drain-induced barrier lowering

DIBL is a main cause for the

large slope of saturation I d vs
Vds in weak inversion.

DIBL can be controlled by controlling threshold voltage (VT) with

substrate (back gate/body) voltage (VSUB).
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Drain-induced barrier lowering – Threshold voltage roll-off

• The DIBL results in threshold voltage roll-off. Under short-channel,

lower threshold voltage causes higher IOFF (subthreshold current).
• This higher IOFF makes it difficult to turn-off the device which results
in high static power dissipation. Lower ION/IOFF causes poor digital
circuit switching performance.

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 Punchthrough
• The expressions for the drain and source junction depletion
widths are:

• where V SB and V DB are source-to-body and drain-to-body

voltages.
• When xdS + xdD = L, punchtrough occurs. 22
Punchthrough-high subthreshold leakage

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 Punchthrough-high subthreshold leakage

• Punchthrough can be minimized with thinner gate oxide, high

substrate doping, shallower junctions. But, higher substrate
doping decreases the mobility of the device.

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 Punchthrough

(a) Surface punchthrough (b) bulk punchthrough.

Surface punchthrough is said to occur when the depletion regions of

the source and drain, in the absence of any depletion from the gate,
reach each other.

Bulk punchthrough occurs in a channel with higher doping

concentration at the surface, which limits the spread of the depletion
regions there.
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 Hot Carrier Effects- Impact Ionization, surface scattering, and
gate oxide breakdown

• Consider a transistor in strong-inversion saturation. The

longitudinal electric field in the channel increases from source to
drain. This field is maximum at the abrupt body-drain junction
and is higher for shorter-channel devices and at higher drain-
source voltages.
• To compensate the stronger lateral electric field created by VDS.,
the vertical electric field (created by the VGS) needs to increase
proportionally (under short-channel). This can be achieved by
reducing the oxide thickness.
• Under the strong lateral and vertical electric fields, carriers move
faster as they approach the drain in such a way that the product
of drift velocity and inversion layer charge density is kept
constant. Eventually, velocity saturation occurs.
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 Hot Carrier Effects- Impact Ionization, surface scattering, and
gate oxide breakdown
• When carriers move at the saturation velocity, they continue to
acquire kinetic energy from the field but their velocity is randomized
by excessive collisions which results in surface scattering.
• Such that their average velocity along the field direction no longer
increases but their random kinetic energy does.
• The carriers with high kinetic energy causes following effects,
– Some of them acquire enough energy to create impact ionization
of silicon lattice atoms, whereby new electrons and holes are
created; this effect is also referred to as weak avalanche.
– The new electrons join the stream of channel electrons and move
on toward the drain; the new holes are swept by the normal field
into the substrate, where they give rise to drain-to-substrate
current.
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Hot Carrier Effects- Impact Ionization, surface scattering, and
gate oxide breakdown
– A much smaller fraction of electrons acquire even higher energy,
which allows them to overcome the silicon-oxide barrier, get
injected into the oxide, and be collected by the gate as gate
current.
– Such energetic carriers also create damage at the silicon-oxide
interface that manifests itself as an increase in interface states
density.
– Another small fraction become trapped in the oxide giving rise to
a localized change of Q0. The ensuing corruption of the oxide
results in device degradation with operating time, or “ageing.”

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Hot Carrier Effects- Impact Ionization, surface scattering, and
gate oxide breakdown

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 Direct gate oxide tunnelling

• In order to achieve a desired current drive at a substantially low

power supply voltages in sub 50 nm MOSFETs, aggressively
scaled gate-dielectrics with equivalent oxide thickness (EOT) in the
range of tox =1.5 - 0.5nm are required according to the latest edition
of the ITRS.
• For such ultra-thin oxides the channel carriers can tunnel into the
gate through the gate-dielectric material. This process of electron
or hole transmission through the dielectric barrier increases the
gate leakage current exponentially with decreasing tox.
• As a consequence of the increase in gate current, the overall
current is raised to an intolerable level for real circuit applications.

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Direct gate oxide tunnelling

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 High-k dielectric - Reducing gate leakage current
and threshold voltage roll-off

Trade-off between ION/IOFF and Vt – choice of tox

• IOFF would not be a problem if Vt is set at a very high value.

• That is not acceptable because a high V t would reduce I ON and
therefore reduce circuit speed.
• Using a larger V dd can raise I ON , but that is not an acceptable
solution because a larger Vdd would raise the power consumption,
which is already too large for comfort. Most other changes that
could reduce the leakage would also hurt ION.
• The salient exception is to use a smaller tox. That improves both
ION and Vt roll-off.
• Unfortunately, large dielectric tunneling leakage--has made SiO2
thickness reduction beyond 1nm more harmful than helpful.
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 High-k dielectric - Reducing gate leakage current
and threshold voltage roll-off

• The oxide thickness at which direct tunneling starts is 3nm.

• With reduction of gate oxide thickness, direct quantum-mechanical
tunneling of electrons from the gate across the gate oxide to the
underlying silicon causes an increase in the gate leakage current.
• After reaching the 70 nm node, a desperate need was felt to use a
high dielectric constant insulating material above the silicon
dioxide layer to subdue the gate leakage current to ignorable
proportions.
• Zirconium oxide (ZrO2) with k = 25, Hafnium oxide (HfO2) with
k = 30, etc.

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 High-k dielectric - Reducing gate leakage current
and threshold voltage roll-off

(a) (b)
Fig. (a) MOSFET with SiO2 as dielectric material (b) MOSFET with High-k as dielectric material

  
o Physical Oxide Thickness t ox  EOT  k  where,  Sio2 is relative
  SiO 2 
dielectric constant of SiO2 and k is relative dielectric constant
of high-k material.
o High-k dielectric materials with large physical thickness and small
electrical thickness can control both short-channel effects and gate
leakage current
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High-k dielectric - Reducing gate leakage current
and threshold voltage roll-off

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 Junction Leakage; Band-to-Band Tunneling

• Large doping concentration in the channel lead to narrow

depletion regions around the source and drain junctions, which
essentially means that the reverse-bias voltage must be
dropped over a small distance, resulting in high electric fields.
• These can cause impact ionization in the junction depletion
regions and the leakage can be higher than that expected.
• The large potential gradient also means that the bands must
bend considerably over a small distance.
• This leads to a form of tunneling through the narrow depletion
region.

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 Junction Leakage; Band-to-Band Tunneling

• In terms of energy bands, an electron can tunnel from the

valence band on the p-side to the conduction band on the n-
side, leaving behind a hole. This is called band-to-band
tunneling.
• The electrons and holes generated in this manner are separated
by the field and contribute to the leakage current. Currents due
to band-to-band tunneling become considerable at fields of 106
V/cm or more.
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Non-uniform dopant concentration –Junctionless transistor
• Because of the laws of diffusion and the statistical nature of the
distribution of the doping atoms in the semiconductor, the
formation of ultrashallow junctions with high doping
concentration gradients has become an increasingly difficult
challenge for short-channel MOS FETs.
• Junctionless transistors (also called gated resistor) have no
junctions and no doping concentration gradients.
• These devices have full CMOS functionality and are made using
silicon nanowires.
• The key to fabricating a junctionless gated resistor is the
formation of a semiconductor layer that is thin and narrow enough
to allow for full depletion of carriers when the device is turned off.
• The semiconductor also needs to be heavily doped to allow for a
decent amount of current flow when the device is turned on.
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Non-uniform dopant concentration –Junctionless transistor

Junctionless vs Normal Transistor

• The JLT can properly turn on and Off by bringing sufficient Gate
voltage at the gate terminal. For proper operation sufficient metal
work function at the gate terminal is required.
• A properly designed gate with sufficient work function can deplete
the channel below it. For n channel mosfet a higher work function
(5.1 ev) and for p channel mosfet a lower work function (4.2 ev) is
essential to deplete the channel. 39
Scaling Laws

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 Constant field scaling
• The basic principle which they employ is that in order to increase
the performance of a MOSFET we must reduce linearly the size of
the transistor, together with the supply voltage, and increase the
doping concentration in a way which keeps the electric field shape
and its magnitude in the device constant -hence the name “constant
field scaling”.
• The scaling process is performed by a linear transformation of
three design parameters (voltage, doping concentration, and
physical dimensions) of a particular generation of transistor by the
same scaling factor, k.
• Under this scaling the shape and maximum magnitude of the
electric field in the structure will remain the same. Thus
undesirable high field effects will not occur.

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Constant field scaling

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Constant field scaling

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 Constant field scaling - challenges
• Consider now the metal and polysilicon lines used to form the
gates and interconnections. Since we now have a fabrication
process capable of small dimensions, let us attempt to scale the
width of these lines by 1/K.
• The new process may also require reducing the height of these
lines, since trying to make very thin, but tall, lines can run into
fabrication problems.
• Let us attempt to scale that height by 1/K also. Then the cross-
sectional area of the lines is scaled by 1/K2.
• Since the current that these lines carry has been seen to scale by
1/K2, the current density in these lines will scale by K.
• This is very undesirable, since the increased current density can
cause what is known as electromigration, a phenomenon in which
atoms are carried by the flow of current and can result in line
failure.
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 Constant field scaling - challenges
• Another problem with scaling interconnection lines is that the
resistance of the lines is proportional to length and inversely
proportional to the cross-sectional area and thus scales by K.
• The parasitic capacitances of these lines to the substrate scale by
1/K, and thus the corresponding time constant does not scale.
• If the lines are long, this can cause a problem, since it prevents us
from taking advantage of the fact that the speed of transistors has
scaled by K.
• Also, since the resistance of these lines scales by K and the current
through them by 1/K, the voltage drop across them does not scale.
Thus, a larger fraction of the total voltages available, which have
been scaled by 1/K, is now wasted across interconnect lines.
• Because of the preceding problems, the height of interconnect
lines is reduced less significantly.
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 Constant field scaling - challenges

• Carrier mobility degradation as a result of high doping (scaling of

NA by K) in the channel and the short channel effect (decreasing
of Vt) are the other drawbacks to consider.
• Additional problems are caused by the “contact windows,”
etched through the thick oxide in order to make contacts between
various layers. If the area of these windows is scaled by 1/K 2.
their resistances will scale by K2. For currents scaled by 1/K, this
means that the voltage drop across the contacts will scale by K,
i.e., in the opposite direction from the bias voltages, which were
scaled by 1/K.
• Another undesirable effect of scaling is an increase in the
resistance of the source and drain n+ regions due to the decreased
junction depth.

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 Constant voltage scaling – reasons and challenges
• Reasons: The voltage swings required for turning the device from
off to on may be an unacceptably large fraction of the total voltage
available.
• In addition, established chip interface requirements must often be
obeyed for which voltage levels are fixed, and, hence, the voltage
cannot be scaled.
• The rules followed in such cases, for decreasing device
dimensions while keeping the voltages unchanged, have
classically been referred to as constant voltage scaling.
• Challenges: In these, W, L, and Na are scaled as before. However,
if the oxide thickness is scaled by the same factor, the resulting
field can be exceedingly high since voltages are not scaled; this
can cause oxide leakage and mobility degradation.
• To alleviate this problem somewhat, oxide thickness is usually
scaled less drastically. 47
 Quasi constant voltage scaling
• To avoid the extreme cases of constant-field and constant-voltage
scaling, compromise scaling rules have been proposed. For
example, geometric dimensions and substrate doping are scaled as
in the case of constant-field scaling, but voltages are scaled less
drastically. This has been termed quasi-constant-voltage scaling.

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