Microelectronic Fabrication

1. Introduction

In this introduction chapter, I will be mainly discussing the following

a. Overview(materials involved, basic processes involved without

discussing much details)
b. what will be covered and NOT covered in this course
c. Grading scheme for this course

If you take any electronic gadget say computer, phone and so on, the heart of the
electronic gadget is chip. The speed of the device is mainly decided by the chip
performance. So, the electrical design and physically making the chips based on the
given electrical design are two important steps that decide the performance of the
chip and eventually, the device performance.

The electrical design of chip for any given device is created by electrical engineers.
Once, the electrical design is available, we have to physically make the chips in fab.
How the chip is fabricated in the industries? The course is focused on various
processes involved in fabrication of chips in semiconductor industries.

In general, during your B. Tech Chemical engineering program, various processes

involved in industries such as petroleum , petrochemical, paper and pulp industries
are covered. However, the processes involved in semiconductor manufacturing
industries (also called as microelectronic fabrication industries) are not covered. So,
in this course, we will be focusing on this.

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 Overview
 The price of electronic goods is
decreasing while others such as petrol is
increasing. Why??
 History of IC’s
◦ William Shockley, John Bardeen and Walter
Brattain invented transistor in 1947.
◦ Before 1947, resistors, capacitors and triodes
were in use for making radio and television.
◦ Bulky, expensive, consumes lot of electricity

The price of electronic goods is decreasing compared to that of other commodities such as
petrol , gold etc…?

The reason is that the heart of the electronic goods is integrated chips ( But why the name
integrated? I will discuss it in next slide) whose price is decreasing with years due to the
miniaturization of devices and the advanced cost effective manufacturing process.
As you observed, the computers, cell phones, television are really bulky when it first
introduced. However, now we are getting slim version of all these items.
Also, as the size keeps decreasing, people are continuously working towards improving the
process involved in chip fabrication. We cannot say the processes are fully developed like
other chemical industries. The paradigm often shifts in chip fabrication industries. Also,
people have to come up with cost effective process to survive the competition from others.

Let discuss history of integrated chips.

William Shockley, John Bardeen and Walter Brattain invented transistor in 1947. (We will
discuss more about transistors in FEOL chapter)
Before 1947, resistors, capacitors and triodes (electrical components present in chip) were in
use for making radio and television.
Bulky, expensive, consumes lot of electricity.

The invention of transistor marked as a new beginning for semiconductor industry. The rapid
development of electronic industry is mainly due to the transistor invention.

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 Overview
 Why the name Integrated Circuits?
◦ Separate transistors were made and
connected by using wires.
◦ Making many circuits is not possible
◦ In 1957, Jack Kilby created five transistors
simultaneously and formed a circuit
◦ After him, Rober Noyce improved the
process
◦ Currently, millions of transistors are made in a
single chip
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Why the name Integrated Circuits?

Previously, transistors were made separately and then they are connected by wires.
However, this is time consuming process as well as troublesome when the circuit is
complicated as we are having billions of transistors in a chip (example: computer
memory devices. Billions of transistors are required to store huge quantity of data). R,
Making many circuits are not possible by this way. However, if we are making many
transistors and their connections simultaneously, we can reduce the time and
thereby the cost (as throughput is higher) though the initial effort in developing the
process is huge. Throughput means how many chips one could make in a given time.

This could also be understand by the following analogy. Suppose if we you want to
multiply two numbers, we could do that by mind if the numbers are simple say 2*2
=4. However, if the numbers are not simple say 12531256987546*256487975689
and if the number of problems are more (around 2000), then it is better to write a
code to calculate the multiplications of two numbers. Though, we need to put some
initial effort in writing the code, it is easy later to solve “n” number of problems.

In 1957, Jack Kilby created five transistors simultaneously and formed a circuit. After
him, Rober Noyce improved the process. Currently, millions of transistors are made in
a single chip

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 Overview
 Transistors: First one (Germanium)

Silicon Based GaAs and others

CMOS BiPolar

 Si is commonly used.
 Easy availability of Si (Sand –Impure form)
 SiO2 forms easily on Si – Good Protection
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Transistors are based on semiconductor materials. Why semiconductor? Why not conductor
or insulator. In insulators, current cannot be carried. Though conductors can carry current,
we could not control it. The current passing through the conductor is proportional to the
voltage applied at the two ends of the wire and the resistivity of that material. But in
semiconductors, we can control the current the way we wants.
Transistors can act as an amplifier (amplify the incoming current signal) as well as switches
(ON and OFF state). ON state represents 1 and OFF state represents 0. As we use binary
number system in the computer, millions and billions of transistors are used to store huge
quantity of data. Using many transistors ,we could construct logic gate. The logic gate (AND
gate, OR gate and so on which you might have studied already) will work based on Boolean
algebra technique. The output of logic gate will help the computer to take decisions. They are
many types of transistors like CMOS and Bipolar. This will be covered in FEOL chapter later.
Initially Germanium was used to make the transistor. But later shifted to Si as it is easily
available (present in sand in impure form) and the cheaper one. Also it forms SiO2 on the Si
surface which provides protection to the underlying Si substrate. Si has a large band gap (1.1
eV) compared to Ge (0.66 eV) which offers better properties to Si. For example, the reverse
breakdown voltage (the maximum voltage beyond which the current rises rapidly) is higher
for Si compared to Ge. Besides, Si has better thermal stability (~140 οC) compared to Ge
(~80οC). Although Ge has few advantages over Si, because of aformentioned advantages, we
are currently using Si as a substrate for making chips in semiconductor industry.
GaAs and other materials are used for some specific applications and not are commonly
used.

*CMOS- complementary metal oxide semiconductor

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 Overview
 Dia/thickness : 200 mm/0.45 mm

 Dia/Thickness : 300 mm/1 mm

 Fragile

 Only 0.1 % entire thickness is used. The

remaining provides mechanical strength.

 Si – Single crystalline silicon

 Impurities such as Boron /phosphorous

added to alter the conducting properties
Ref: www.intel.com of Si
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All the chips are made on Si wafers. How the Si wafer looks like? Please see the picture. It
looks more like CD disk. The dimensions of the Si wafer used in the semiconductor industries
is given in the slide. Typically we are using 200 mm/300 mm diameter Si wafer. If the dia
increases, the thickness of the wafer should also be increased as it provides mechanical
strength. We will make all the transistors and the connections only on top of the Si wafer. i.e.
Only 0.1 % entire thickness is used. The remaining provides mechanical strength.

The Si material can be

1. Single crystalline ( the basic crystal structure is repeated for a long range – i.e. same
throughout the material). So the surface is homogeneous. This is really preferred in
semiconductor industries. But it also expensive.
2. Polycrystalline ( here it is repeated only for a short range and disturbed at the grain
boundaries. i.e. within grains, the structure as well as the orientation is same but
orientation is different among different grains. The grains are separated by the grain
boundaries. The properties along the grain boundaries will be different from grains. This
is the starting material for making single crystalline Si. Few techniques such as Czochralski
technique, float zone technique available for converting polys Si into single Si. However,
these will be not discussed in this course.
3. Amorphous: more randomly distributed.

One could control the semiconductor prooperties of Si by adding dopants such as Boran and
phosporus. These processess will be discussed in detail later.

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 BEOL/FEOL

Ref:
www.magwel.com

 Transistors are connected by a material called

interconnect(Al / Cu)
 Making transistors – Front End of Line
(FEOL)
 Connecting wires – Back End of Line (BEOL)
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The chip fabrication basically involves two major processing stages

(1) FEOL – Front end of the line
(2) BEOL – Back end of the line

FEOL involves making transistors and other important electrical components on the
top of the Si substrate.
BEOL involves connecting all these transistors and other components by some metal
wire.

See the picture. Grey region represents Si. Green and yellow region is for transistor
and other electrical components. Red and Blue blocks represent metal wiring

We will be discussing BEOL in detail in Chapter 2 and FEOL in chapter 6

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 BEOL /FEOL
Steps FEOL BEOL
Shape Photo Lithography Photo Lithography
Definition
Modification Ion Implantation Anneal
Diffusion
Rapid Thermal Anneal (RTA)
Oxidation

Deposition Chemical Vapor Deposition Chemical Vapor Deposition

(CVD) (CVD)
Physical Vapor Deposition Physical Vapor Deposition
(PVD) (PVD)
Electrochemical Deposition

Removal Chemical Mechanical Chemical Mechanical Polishing

Polishing (CMP) (CMP)
Etching Etching

The various processes involved in FEOL and BEOL are summarized here. Each process
will be discussed in detail in subsequent chapters. Some basic information is given
below:

If I want to create one particular device with particular dimensions at a given location
in the Si substrate, then I have to define the size and shape on the Substrate. This is
done by photolithography. This is more like creating patterns on the substrate. More
details will be discussed in chapter 3.

If I want to modify the properties of given materials, then it can be achieved by

various processes as listed in the slide. For example, if I want to dope boron to silicon,
then it could be done by either by ion implantation or diffusion.

Once you define the shape in the substrate, we have to deposit some material
(conductor/insulator depending on the situation), then it could be done by various
processes as shown in the slide.

After deposition, the excess material should be removed. The processes employed for
this step is also shown in the silde.

What are the various processes available for a given step, what are the advantages
and disadvantages of each of these processes, all will be discussed in this course.

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 Major steps in IC Manufacturing
Electrical Design

Physical Layout

Creating Chip Our Focus

Testing

Before seeing all the processes, let me discuss, what are the four major steps
involved in the integrated chip manusfacturing?
1. Electrical design (Here once the device is fixed say cell phone, the electrical circuit
will be drawn by the electrical engineers. Will not be covered in this course)
2. Physical layout. Once the circuit is drawn, the physical layout will be created.
Basically the soft file. It gives you the 2D (X and Y dimensions) view of the chip.
The third dimension (Z) will be included in the process flow sheet and control in
the manufacturing process. Especially, the location of all the components in the
chip is decided. Once this is done, using the soft file, the mask (with defined
patterns) will be created. It is like a photonegative. (covered minimally in this
course in chapter 2)
3. Creating chip (main focus of this course – actual chips are created using the mask
(similar to taking many photographs from the negative) and by the various
processes (mentioned in the previous slide)
4. Once, the chip is fabricated, it will be sent to quality control section to test the
performance of the chips. If a particular chip does not pass the test, then it will be
discarded while others will go through. (basics will be covered in this course)

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 Course Overview and Grading
Scheme
1. Introduction
2. BEOL
Assessment 1
3. Photolithography
Mid Sem
4. Deposition
5. Removal
6. FEOL

7. Ion implantation
8. Diffusion Assessment 2
9. Oxidation
End Sem
10. Testing and
11. Yield
12. Tools and Techniques

The overall course is divided into 12 chapters. At the end of every of three chapters,
there will be an assessment test as shown in the slide i.e. for assessment 1, the
questions will be asked from chapters 1-3 and for assessment 2, the questions will be
asked from chapters 4-6 and so on. Each assessment carries 15 marks. Assessment
tests are written based and for this question paper will be send to you through mail
and you need to submit your responses through mail in a given time. There will be a
viva-voce exam which carries 40 marks. The syllabus for viva-voce exam includes
chapters 3,4,5,6,7 and 9 (6 chapters in total).

Grading scheme:

Assessment Tests: 4x 15 = 60 Marks

Viva-Voce exam = 40 Marks

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 References
1.Class notes
2. S.A. Campbell, The Science and Engineering of Microelectronic
Fabrication,,2nd Edition, Oxford University Press, 2001
3. Richard C. Jaeger, Introduction to Microelectronic Fabrication, Vol. 5 of
Modular Series on Solid State Devices, 2nd Edition, Prentice Hall, 2001
4. Peter Van Zant, Carol Rose (Editor), Daniel Gonneau (Editor), Microchip
Fabrication: A Practical Guide to Semiconductor Processing, 2nd Edition,
Semiconductor devices, 1990

INTERNET
❑ www. semiconductor.net
❑ www.intel.com/research/silicon/

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The reference books are given for additional reading. Reading the PPT slides are
sufficient for assessment tests and viva-voce exam.

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 Boolean Algebra logical gate
A C
B E

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 2. BEOL

Before moving to chapter 2, I will quickly summarize what we have seen in the first chapter.
1. We discussed about what will be covered in this course
Major focus on various processes involved in fabrication along with testing and yield of chip and, various tools used in semiconductor
industries
2. Why we use Si as a substrate in semiconductor industries
It is cheap, easily available, forms SiO2 on surface which act as a protecting layer, relatively high thermal stability, higher reverse breakdown
voltage. We have also discussed why semiconductor is being used over conductor and insulator.
3. We use Si in the form of wafers. All the components and connections are made on the top of Si wafer
4. What are the two major processing steps: Back end of the line (BEOL) and Front end of the line(FEOL). Making of active devices such as
transistors come under FEOL while connecting the active devices i.e. wiring come under BEOL
5. We have also seen the functions of transistors i.e it can act as an amplifier and switch (ON and OFF state). We will see the transistors making
and their working principle more in chapter 6
6. Also, I discussed what are the major processes being employed in FEOL and BEOL. We haven’t discuss the details of these processes yet which I
will do in the subsequent chapters.
There are few points which I missed to explain in first chapter which I will discuss now.
Firstly, I mentioned about Fab. Fab refers the industries which fabricate the chips. Sometimes it is also called foundry. On the other hand, Fabless
refers the industries which only design the chip (electrical design of the circuit) and sell the hardware part. They wont involve in fabrication
process.
Some of the major foundries ( make and sell chips on a commercial scale) in the world:
1.Intel, USA
2.Hynix, S. Korea
3.Samsung, S. Korea
4.Global foundries, Germany
5.TSMC, Taiwan
6.USJC, Japan
7.ST microelectronics, Singapore and So on
Chemical engineers are being placed in these companies with a good package.
If you see above, you may observed that India don’t have any fab. The major reason is that huge capital investment is required along with
uninterrupted power and water supply for setting up a new plant. However India has fabless industries such as semiconductor India Pvt Ltd, IBM
Global service India Pvt LTd etc. Though ISRO has small scale fab, they fabricate chips for some applications. They don’t fabricate on a larger scale
for electronic gadgets.
It is also to be noted, that the processes which we are discussing here not only used in semiconductor industries, but also in making MEMS
devices (micro-electromechanical system), fabrication of biosensor etc. MEMS devices basically consist of both mechanical and electrical
components. It has wide spread applications in automotive, electronics, medical, communications industries and in defence.

1
 Electrical Design

BEOL – connecting devices

using wires (metal)
Physical Layout

Device 1 Device 2Device 3Device

Creating Chip
Silicon Wafer

FEOL
Testing

Now, move onto chapter – 2 BEOL.

In the last chapter , we discussed ,there are four major steps in chip fabrication. The
same is also shown here. Among these, we will be focusing on creating chips.
Again in creating chips, there are two major processing steps (1) FEOL – making active
devices and then BEOL (connecting the devices by metal wire).
Although, the first step is FEOL, we will discuss BEOL first as it is relatively easy to
understand.
Regarding Picture: Blue – Si substrate ; Green – Devices such as transistors, Brown –
connecting wires, Grey- insulator such as SiO2. Insulators needs to be placed between
devices and between wires, to prevent short circuiting.

Connecting wires is referred as metal interconnects/ interconnects. So hereafter, I use

the word “interconnects”

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  Why BEOL is important?
 Al vs Cu technology
▪ Properties of interest
▪ Why Al was used ?
▪ From Al to Cu technology
▪ Issues in Cu technology
▪ How we overcame these issues
 Process flow
▪ Al
▪ Cu
 Integration issues
3

The topics that will be discussed in this chapter.

3
  For older generation, FEOL decides the speed
of the chip and BEOL influences the yield of
chip.
▪ Transistors has to switch fast
▪ Many layers in BEOL – more likely to fail

 In new generation, BEOL also affects speed

of the chip
▪ Signal has to go through interconnect metal
4

One may think, why BEOL is important as we are having active devices such a
transistors are made during FEOL and BEOL is just about connecting the devices? In
previous generation also, people are striving towards increasing the speed of the
device. If we want to increase the device speed, the transistor has to switch ON and
switch OFF quickly i.e. the transition b/w these two states must be quick. However,
these are coming under FEOL. BEOL is important only from yield point of view. Yield
means, out of total chips made, how many chips going to perform well. For example,
if only 7 chips perform well out of 10 chips, then yield will be 70%. As many
steps/processes (most of them are very sensitive to lot of factors) are involved in
making a chip and also, the device size is continuously shrinking, the chances of
failure is more in semiconductor industries. We will be discussing Yield in detail in
chapter 11.

So, as I told , in previous generation BEOL is important only from the yield point of
view. Because, the chance of failure is more in BEOL than in FEOL. Because, active
devices are present in a single layer while connecting wires are made in many layers
(4-15 layers). So chance of failure is more in BEOL.

But why multilevel metal layers are used instead of single layer which we will see
later in this chapter.

But in new generation, as the device size shrinking continuously, transistor size also

4
becomes small and thus the speed of the device is enhanced. For example, the device
speed is increased from 100 MHz (during 90’s) to 3 GHz (currently). Speed of the
transistor is mainly depend on Gate length (we will see this in chapter 6). As
transistor size decreases, the Gate length also decreases and eventually the chip
speed increases. As manufacturing process is available for making a small transistor,
this is not an issue.

But in newer generation, BEOL is also important from speed point of view. Even
though, the transistors are working fast, the signal has to go from one transistor to
the other through interconnect metals. This is trivial when transistor speed is low.
But, now a days, as we could make high speed transistors, we have to focus on BEOL
as well to increase the device speed.

So, BEOL is also important from speed point of view in the current generation.

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 ❑The metal layers are names as M1, M2, M3 and so on…
❑M1 thickness is smaller (200 nm)- Local interconnects –
between cells
❑M2, M3 interconnects are slightly larger (250 nm) – Global
interconnects – between blocks
❑Last one must be large (450 nm) – for power distribution
❑ Has to carry large current. To reduce the resistance, the
width has to be higher.

In this slide, we will see more about metal interconnects.

In semiconductor industry, the metal layers are named as M1, M2 and so on by

convention. Usually in integrated chips, the metal layer varies from 4 to 15. If the
circuit design is complex, then we need more metal layers so that the chip could be
fabricated in minimal area. It is must that the chip area should be smaller because it
affects the cost of chip.

Based on dimension, metal layers are classified as Local interconnects and Global
interconnects. If metal layers are more, then we may have intermediate
interconnects.

Local interconnects are connecting the nearby active devices. It runs for shorter
distance. So its thickness is also lower. On the other hand, global interconnects are
run for longer distance and its thickness are slightly higher as shown in the slide.
Because resistance increases as you increase the length. To compensate that, we
have to increase the thickness of the interconnect. Global interconnects are for
connecting the devices b/w different blocks. The last metal layer is for power
distribution so the width and thickness should be larger.

5
 Ref: http://www2.isu.edu.tw/upload/341/7/files/dept_7_lv_2_31755.pdf
6

This slide shows the local and global interconnects. As you see, the length of global
interconnects (yellow) are long compared to that of local interconnects(pink).

6
 7

The horizontal structure (named as metal 1 and metal 2 are interconnects). The
vertical structure (black color) are called as contact or via.

Contact : connection b/w FEOL and first metal layer

Via: connection b/w first layer and second layer, second layer and third layer and so
on.

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  Resistivity – should be low
 Melting point – should be high
 Thermal expansion coefficient – mismatch
with other materials in use should be low
 Diffusivity in SiO2 – Should be low
 Adhesion to the insulator – should be better

Metal Resistivity, µ ohm - cm Melting point, °C

Cu 1.7 -2.0 660
Al 2.7-3.0 1084
W 8-15 3410
8

So far, we discussed about interconnects. what is the material used for making
interconnects? We will discuss this now.

As BEOL also affects device performance, we have to chose a right material

(conductor) for making interconnects. As the signal has to go from one end to the
other, the material should be obviously a conductor. As you know, metals are good
conductors of electricity. Thus, metals are used for making interconnects. As many
metals are available, we have to chose the suitable one. So, the resistivity value of the
metal should be lower. But, what are the other properties we are looking for in the
metal?

When we are making many metal interconnects, insulator should be deposited b/w
them to prevent short circuiting i.e. one metal line should not touch the other one.
Thus, diffusion of metal to the insulator (normally SiO2 is used) should be low. As the
concentration of metal atoms is higher in metal side while the concentration is zero in
the insulator side. Thus, the metal atoms will diffuse from metals to insulator. This
diffusion rate should be lower. Also, when we are depositing SiO2 b/w two metal
layers, metal should adhered well to the insulator. If it is peeled off, then it won’t
serve the purpose.

As we are using chips at different locations, temperature fluctuations will be there. So

materials will expand /contract depending on the temperature. As we are using many
materials in the chip (Si – semiconductor, SiO2 – insulator, Metal- conductor), the

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mismatch of thermal expansion coefficient of metal layer with other materials should
be lower.

The values of resistivity and m.p is given for some of the metals which are explored
by semiconductor industries for interconnects is given in the slide.

8
  Cu is widely used now [in 1997, IBM
introduced chips with copper interconnects*]
 Al – Previously

Metal Metal

via via via

*Ref: http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/

In the last slide, we have seen the properties of interest for metal interconnects.
Based on it, Al was chosen initially and then we moved to Cu.

Why Al was used initially and why we moved from Al to Cu which we will see in the
next couple of slides.

Regarding Picture: grey – SiO2 .

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  Al – W process to make interconnect is more
easier than Cu.
 Mechanical properties of Al is compatible
with Si
 Al has high melting point
 Mismatch of CTE b/w Al and Si is lower
 Does not contaminate Si

10

Why Al is used initially?

Although Al resistivity value is higher compared to Cu, when considering other

properties(read this slide for understanding), Al is a better choice for interconnects.

10
  Cu is widely used now [ Al – Previously]

11

But later we moved from Al to Cu.

Currently, we are using Cu only although continuous research on exploration of
possibility of using other metals as interconnects is going on.

Why we moved from Al to Cu? Before addressing this question, first we will see how
device size is continuously shrinking with years?

This plot is given for various units such as DRAM- dynamic random access memory,
MPU (memory protection unit) gate length, print gate length. The trend for all the
units are almost same (slope is ~ 12-13%) . During 60’s, the device length is 25000
nm, in 90’s the device size is shrink to 800-900 nm and currently, it is in the range of
10 nm. However, in this plot, you could see only till 2014.

So, from this plot, it is clearly observed that the device size is continuously shrinking.

But , how does it affect BEOL performance? We will see in next slide.

11
 12

The signal from one device to other has to go through metal interconnects. How fast
it will go? We can quantitatively measure this and call it as RC delay. If the RC delay is
low, the signal will go fast. How to calculate RC delay. The equation is given in the
next slide. Before this, see this plot. Just focus on Pink line (Al is used as interconnect,
SiO2 is used as insulator) and blue line (Cu as an interconnect and low dielectric
material in the place of insulator). This plot is given for how RC delay is changing with
device size. Below 0.18 micrometer (left to green line), the difference in delay b/w
Cu-low K interconnect and Al –SiO2 is not significant. However, the difference is
significant for lower device sizes (right to green line). Especially below 0.18 micron
size, we have to shift to Cu technology to improve the speed of the chip.

In summary, we have seen the device size is shrinking with years and when the device
size decreases, the RC delay for Cu is lower compared to that of Al. This is mainly
because of lower resistivity value for Cu. So, we have to move from Al to Cu.

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 ρ L2
RC Delay = ε
M S
ρ = resistivity
M = metal thickness
ε = permittivity of ILD
L = length of metal layer
S = ILD thickness

13

The RC(Resistive-capacitive) delay associated with metal layer is influenced by various

parameters.
To decrease the delay, the resistivity has to be lower i.e. conductivity value has to be
high. Note Cu has higher conductivity than Al
Decrease in metal thickness (decrease in device size) increase the RC delay. So, to
compensate that, we have to chose a high conductivity material. That’s why, we
moved from Al to Cu.
Similarly if we choose a material with low epsilon (low dielectric constant), RC delay
could be decreased. People are exploring various low K materials in the place of SiO2.

13
  Cu has lower resistivity
 Lower joule heating
 Allowing higher current densities and
therefore smaller sizes
 Lower electro migration resistance – less
failures

14

In addition to higher conductivity, Cu has few more advantages which is mentioned in

this slide.

As you know, joule heating (or ohmic heating) is directly proportional to resistance of
the given material, the joule heating is lower for Cu.

Besides, current density is inversely proportional to resistivity of the material, thus Cu

allows higher current densities and only smaller size is required compared to that of
Al to allow the same current.

Electro migration Resistance:

When current is passing through a conductor, the electrons move from one end to
the other end. They transfer some of their momentum to the metal atoms and
gradually the metal atoms also move. This is called electromigration. This
phenomenon is not of much importance when the current densities are low. In IC
chip the current densities are very high and electromigration can cause failure of a
circuit.

In the beginning, the metal would fill the space between the insulators and the
current density would be at a certain level. If sufficient atoms move due to
electromigration, then a small void will form. Now the all current has to go through

14
the metal and hence near the void region, the current density will increase. The
electrical resistance of the metal line is also higher now, because the electrical
resistance is inversely proportional to the cross sectional area. This results in larger
heat release and hence higher local temperature. At higher temperatures, the metal
atom diffusivity is higher, which makes it easier to ‘push’ the atoms. The increased
current density and higher temperature accelerates the formation of voids and finally
results in the circuit failure.
The extent of electromigration movement depends on the nature of the material. For
example, materials such as copper, tungsten and gold have good electro migration
resistance. We must note the difference between electrical resistance and electro
migration resistance clearly. Electrical resistance indicates the resistance to
movements of electrons. We want good electrical conductors (i.e. low electrical
resistance). At the same time, we want materials which have high electro migration
resistance.
If the electro migration resistance is poor, then after many hours of operation, the
resistance of one or few wires will increase dramatically. It can lead to the failure of
the chip. These types of failures, where the chip originally functions well and after
few months of operation fails, are called “reliability issues”. This means that the chip
appears to be good during testing in the fab, but it is not reliable and after sometime
it can fail.

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  Difficult to pattern using conventional
etching technique
▪ Generate etching products such as CuCl2 which is
not easy to evaporate.
 Quickly diffuses into oxides and Si
▪ Altering the property of Si and oxides –more
failures
 Oxidizes in air
▪ Poor oxidation resistance
15

But there are new issues coming up in the process side when Cu technology replaced
Al technology. What are those issues? It is mentioned in this slide.

If you want to create patterns on a given metal, you have to remove some part of the
metal. The metal is removed conventionally by etching technique (we will discuss this
process later). For example, if you have metal A, it will react with other chemicals B
and it will form a etching product C. The “ C” has to be volatile /dissolvable so that
the metal will be removed.

For Al, the removal is done by etching. However for Cu, the etching products are non-
volatile in nature. So , we can’t use etching for Cu removal.

Also Cu quickly diffuses in to Si and SiO2 unlike Al. If Cu (conductor) diffuses into SiO2
(insulator), it will alter the property of SiO2 and causes of failure of chips. These are
the two major issues.

How to overcome them. We will discuss this in this chapter when we are discussing
process flow diagram of Cu technology.

15
  Etching products –non volatile
 Instead of etching , chemical mechanical polishing is
introduced

 Diffusion of Cu in to SiO2
▪ Introducing barrier layers between Cu and SiO2
such as Ta, TaN, TiN

16

As we discussed, we have few issues in introducing Cu technology in in fabrication.

How we overcame them?

Instead of etching, chemical mechanical polishing – a removal technique was

introduced. We will see this process in detail in removal chapter. A brief introduction
to this process is given at the end of this chapter.

Diffusion of Cu in to SiO2 is overcome by introducing a barrier layer (ex: Ta, TaN, TiN)
b/w Cu and SiO2.

Using these techniques, we moved from Al to Cu. In the next couple of slides, we will
see Al and Cu technology in detail.

16
 Metal layers

Cu Cu Al Al

Cu Cu Cu W W W

Vias

17

The difference b/w Cu and Al technology

Metal layer Contact Vias

Al W W

Cu W Cu

But why we are using W. It is easy to deposit W in high aspect ratio structures than
Al. But note W has higher resistivity. But the overall length of vias are small compared
to that of metal layers. Hence contribution to overall resistivity will be low. So, we can
use W in vias

But for contact, W is used for both Cu and Al.

Aspect ratio - ratio of length to width

High aspect ratio - the ratio of length to width is small.

17
 a

18

This slide shows the conventional aluminum process.

Here Yellow color region represents SiO2. Blue color region represents Al. Brown
color region represents positive pattern/positive photoresist.

I have structure as shown in (a). I want to pattern this so that I could get a structure
as shown in (d). How to achieve this ? The major steps involved in it are shown in
here.

Basically I have a rectangular block of Al as shown in (a) and I want to get a vertical
structures as shown in (b). To do this patterning, put a positive pattern (I will be
discussing more about positive pattern & negative pattern, how to put that on top of
any layer as shown in (a) in next chapter) on top of Al layer. Now if you expose this
structure to etching solution, the region beneath the positive pattern will not be
exposed to the solution and hence it cannot be removed(ideally). However, the
region which is exposed to the etching solution will be removed. After that we have
to remove the positive pattern. Then we will get the structure (b). Then, we have to
deposit SiO2 layer as shown in (c) by using suitable deposition technique. Afterwards,
the excess SiO2 layer will be removed by suitable removal techniques(subtractive
etching) by as shown in (d).

The main point I want to share here is, the Al patterning could be done by etching
process. But you cannot employed this step for Cu patterning as explained
previously.

18
 Ref: https://www.philamuseum.org/booklets/7_43_80_1.html
19

For making Cu patterns, people used damascene technique. The name damascene
originates from Damascus, the capital of modern Syria.
This is the old technique by which people inlay one metal in to other metal. The
techniques was used for making decorative patterns for jewellery, bowls etc.
See the figure in LHS. First we have to create pattern on the substrate. Then, cut the
metal which is to be inlaid into required shape. Then hammering the metal in to the
substrate, we will get the required structure as shown in 3.

The above technique was inspired for making Cu patterns in the Chip. Hence, it got
the name Cu damascene technique.
Now see the RHS figure. The first step is the same. In the second step, copper is
applied to the entire substrate and then polish the copper so that the copper is
stayed only on the channel made.

19
 20

How the same Al pattern created by both using conventional process and damascene
process is shown in this slide.

In RHS figure, read the negative pattern as positive pattern.

If you look conventional process, first deposit Al, then create patterns on Al by
etching. Then deposit SiO2. But in damascene technique, deposit SiO2, create
patterns on SiO2, then deposit Al and finally remove extra Al by polishing. So there is
no etching process involved in the damascene technique.

Hope you got the difference b./w these two techniques.

It is to be noted that dark blue represents etch stop layer. It is to make sure that
etching will proceed until this layer exposes to the solution. As soon as, this layer
exposed to the etching solution, the etching stops. It is to make sure that etching will
be proceeded upto a certain height. We will discuss this in detail in removal chapter.

20
 Example of Single Damascence Process

Single, because one layer is created in one

damascene step
Polishing of Copper makes this possible

Polish
Etch
Dep

21

Again in damascene process, we have single damascene and dual damascene

process. In this slide, single damascene process is described.

Here the vertical structure is created first followed by horizontal structure. i.e. only
one layer is created in a single step.

21
 Example of Dual Damascence Process

Dual, because two layer are created in one

damascene step

Polish
Dep
Etch

22

Here, both the horizontal and vertical structures are created at the same time (in a
single step). It reduces the number of steps involved and increases the throughput.

22
 Fig .1 Fig .2

23

Let see what are the steps involved to make the structure given in Fig. 2 from Fig. 1

Cu metallization – Process integration: Copper has lower electrical resistance and

higher electromigration resistance then aluminum. Hence it was introduced as
interconnect material in the 1990s. Dry etching of copper was difficult and hence the
aluminum process integration scheme could not be used for copper. A new set of
processes and sequence was needed. The following describes the process integration
scheme of copper metallization.

Fig 1. Schematic of chip in BEOL , with Cu line (a) after M1 layer Fig 2. after
fabrication of via12 and M2 layer.
Here via12 refers via connecting M1 and M2 layer.

23
 Fig. 3 Fig. 4

Fig. 5 Fig. 6

24

At first, a thin layer of silicon nitride is deposited on top of copper, by LPCVD (Low pressure chemical vapour deposition) as shown in Fig 3. Next, a thick layer of silicon
dioxide is deposited on top (Fig. 4). Both the silicon nitride and silicon dioxide are insulators. Silicon nitride acts as an etch stop layer. In the next step, using lithography
and dry etching, holes for the vias are created (Fig. 5). In this process, the etching ‘stops on nitride’. i.e. only the oxide layer is removed but the nitride layer is not
removed. The etching chemicals and process conditions are chosen such that only the oxide will etch.
Then, again using lithography and dry etching, trenches (horizontal structure) for metal lines are made (Fig. 6). This is called as ‘blind etch’ because the etch does not stop
at another material. The etching time is controlled so that the expected depth (with some variation) will be created.

24
 Fig. 7 Fig. 10

Fig. 8
Fig. 11

Fig. 9
Fig. 12

25

Then a thin layer of the silicon nitride, inside the via hole, is removed using dry etching using suitable combination of chemicals and plasma (Fig.
7). During this etch, a slight damage to Cu lying below may occur. However, since the nitride layer is thin, the etch time will be very short and the
damage is also limited. If the nitride layer were not present and only oxide were used as insulator, the potential damage to Cu line would be
severe.
Subsequently, a thin layer of barrier (Ta/TaN, and in some cases, an additional layer of Ru) is deposited (Fig. 8). This is needed to prevent the
diffusion of Cu through the silicon dioxide insulator. Then, another thin layer of Cu is deposited using CVD method (Fig. 9). This is needed to obtain
a layer of at least moderate electrical conductivity for the next step.
After the seed layer is deposited, a thick Cu layer is deposited using electrochemical deposition (Fig. 10). The Cu formed has larger crystals, lower
electrical resistance and higher electromigration resistance compared to Cu deposited by other methods such as PVD or CVD. The Cu can not be
deposited only inside the vias and trenches. Hence it is deposited throughout the wafer surface. Then in the next step, the excess Cu is removed
using CMP (Fig. 11)
The removal is done in two steps. In the first step, only the Cu is removed. The barrier and the insulator are not removed (Fig. 11). In the second
step or 2nd stage of the CMP, a different slurry is used and the barrier metal is also removed in the unwanted places (Fig. 12). Subsequently, the
Cu is annealed so that the crystal size increases.
This scheme of intergration is called “via first” integration because via holes are made before trenches here. In another process sequence, the
trenches can be made first and the vias can be made afterwards (i.e. the processes in Fig. 5 and Fig. 6 can be done in reverse order) and that
scheme is called “trench first” integration. Most fabs use the via first scheme for copper metallization.
Summary: Process integration denotes combining various processes to obtain the desired structure, to obtain a functioning chip, in a robust
fashion. In the modern chips, the BEOL part plays a significant role in determining the yield as well as the speed of the chip. Electromigration is
the movement of metal atoms due to the movement of electrons. It can cause failures at the later stage of chip operation and hence is a
reliability issue. If the metal lines are long, and/ or if large current densities are used, then the chances of failure by electromigration is high. It is
desirable to have high electromigration resistance and low electrical resistance. Aluminum has more electrical resistance than Cu and less
electromigration resistance than Cu. However, it can be etching using plasma and a process sequence using tungsten vias and aluminum metal
lines was used to make interconnects. With the introduction of CMP, it is possible to make Cu vias and Cu metal lines on chips, and the different
process sequence needed to obtain Cu interconnects was discussed.

25
 26

We will see trench first and via first Cu process in detail. I am concentrating only on
making vias and trenches. So do not worry about other processes such as copper
deposition and Cu polishing.

In this slide, trench first (via next) process is given: PR represents photoresist (in the
previous slide, it mentioned as positive pattern).

First they make trench (Fig. 3) and then deposit photoresist (Fig. 4). Here they have to
deposit thick layer of photoresist (referred as photoresist pooling) and then make
small hole (via –high aspect ratio) as shown in Fig. 5. This is difficult to do. Hence, it is
usually not preferred.

Finally, photoresist is removed. You will be end up with trench and via structure as
shown in Fig. 6

26
 27

Here via first (trench next process is given): As you see in the figure, via is created first
(Fig. 9) followed by trench (Fig. 10- fig. 12). The main advantage is , we need not to
make via in the thicker photoresist as in the previous case. Thus, this process is really
preferred. But it also has few disadvantages For example, as you see in figure Fig. 10,
residual photoresist is present at the bottom. This may be absorbed by the SiO2 layer
and alter its characteristics.

27
 Fig .1 Fig .2

28

Let see what are the steps involved to make the structure given in Fig. 2 from Fig. 1

Aluminum process: When aluminum is used as interconnect material, a layer of

titanium and titanium nitride is used as a barrier and adhesion promoter. This
prevents the diffusion of aluminum atoms through the insulator. The insulator
material used is SiO2. The sequence of process steps needed to fabricate a via and a
metal line are given below.
Let us assume that the fabrication of M1 is completed and that via12 and M2 have to
be fabricated.

28
 Fig. 3 Fig. 5

Fig. 4 Fig. 6

W deposition
29

First, a layer of silicon dioxide is deposited on top of M1 (Fig.3). Then using lithography and plasma etching, via12 hole is made (Fig.4). Next, a thin
layer of TiN/Ti is deposited on top. This film is formed on the top of the surface as well as on the sides and bottom of the via hole (Fig. 5). Then, W
is deposited using CVD-chemical vapor deposition (Fig. 6)

29
 Fig. 9
Fig. 7

Fig. 8
Fig. 10

30

Then, excess W is removed using CMP (Fig.7)

In the next step, aluminum and titanium are deposited on the top (Fig.8). After that, using lithography and plasma etching,
aluminum is removed from unwanted locations. The titanium barrier layer is also removed along with aluminum in those
locations (Fig.9).
Oxide layer is deposited on top of the aluminum (Fig. 10) and the non-planar surface is subjected to CMP, to make it planar. This
is necessary so that subsequently lithography can be done on the surface with minimal distortions.

30
 31

In this slide, I am explaining about CMP process which was introduced to remove
excess copper in the place of etching.

Chemical mechanical polishing is a process in which both chemical and mechanical

actions are used to remove the excess material. The schematic of CMP machine is
given in this slide. The wafer needs to be polished to be kept upside down (shown as
blue color) and rotate against the pad under pressure. The CMP slurry consists of
abrasive particles (Silica powder, alumina powder etc), oxidizers, corrosion inhibitors,
pH tuners and surfactants are continuously supplied to be the pad. The slurry
chemicals react with wafer surface and will remove the excess material.

We will discuss about CMP process in detail in removal chapter.

31
 ❑ Al vs Cu processes
❑ Al -etch / Cu Damascene (CMP)
❑ Al -via is W / Cu- via is Cu
❑ Al & Cu: Contact is W

❑Overall, the processes involved are

❑ Lithography, PVD, CVD, Electrochem
Dep, Etch, Anneal

32

32
33

33
34

34
 MICROELECTRONIC
FABRICATION
1 3. Photolithography

In the last chapter, we discussed about BEOL process.

We have seen BEOL process involves fabrication of metal interconnects

(Metallization). The interconnects are needed to connect the active devices and for
power distribution. The interconnects are classified as local, intermediate and global
interconnects based on the dimension.

We discussed what are the materials being considered for interconnects. Previously,
we used Al and then we moved to Cu. What are the issues we faced and how we
overcame them when we moved to Cu? These were also discussed in the previous
chapter. Mainly, we have seen, Cu cannot be removed by etching process and hence
CMP process was introduced. The Cu patterning was done by damascene technique.
This is classified in to single and dual type. Again, in dual type, we have trench first
and via first process.

What are the various process steps in Cu and Al patterning? We have discussed the
process flow sheet for both the materials. Here onwards, we will discuss the
processes involved in BEOL in detail one by one.

The first process technique , we are going to discuss is photolithography.

1
 OVERVIEW
 Layout
 Mask

 Photolithography
 Its figure of merit
 Types of Lithography
 Basic
 Advanced
 Limitations and Applications

The overview of this chapter is given in this slide. First we will discuss layout followed
by mask and then photolithography.

2
 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
3
❑ the transferring of patterns from the mask to the wafer

The sequence for making chips is creating physical layout followed by mask making
and then eventually making chips from mask using photolithography technique. So
before discussing photolithography, we will discuss about layout first.

3
 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)

4
Picture: Physical design for system on a chip by Y. Chang at al , 2006
DOI:10.1007/1-4020-5352-5_9

As I said before, Once the device is fixed, the electrical design should be made for the
same. From this electrical design, physical layout should be created i.e. the circuit
representation (electrical design) is converted into geometric representation (physical
layout) as shown in the above picture. For example, if you look at the electrical
design, you know how many transistors are required and how to connect them. The
physical layout shows how everything will look (top view) on an actual chip. It also
provides quantitative information i.e. what is the length and width of a, b, c, d and e,
what is the distance between c and a, a and b and so on., what is the length and
width of yellow and green rectangular block. In short, it gives you 2D picture of the
final chip.

4
 LAYOUT
 Soft copy file
 MS file – doc file; Acrobat portable file –pdf
 Layout file -GDS
 IC chips- many layers (transistors, Gate , metal
layers)
 GDS file have info about all the layers
 But each layer must be specified separately
 If the circuit in the chip is repetitive, then storing the
one circuit in file is sufficient.
 Group level information vs. individual level
information
 Hierarchical file (to reduce the size of file) vs. flat file
(have complete info) 5

All the information about physical layout is stored in a soft copy file where the
information for all the layers (FEOL, BEOL) are available. Basically, this is stored in a
magnetic tape. Then this will be feed to pattern generator (mask masking machine)
to create masks. Using these masks, we will create actual chips. Before moving onto
masks and making chips, we will discuss little more about layout.

The physical layout file format is GDS. (just similar to referring word file as .doc and
acrobat reader file as .pdf)

IC chips have many layers (transistors, Gate , metal layers) GDS file have info
about all the layers
But each layer must be specified separately
If the circuit in the chip is repetitive, then storing the one circuit in file is
sufficient.

In some cases, we need detailed info about all the layers (i.e. individual level
information). For example, if we want to perform optical proximity correction (OPC)
for the given layout, then we must know the details of this layout. I will discuss about
OPC later. Right now you assume, it is one of the correction techniques performed to
get the patterns right on the chip.

However in some cases, group level info is sufficient. It can be understand by the

5
following analogy. In a company, we have one CEO, two GM, 4 mangers and 8
workers. 2 workers are working under one manger (first level) that is referred as Team
1. Every two managers are controlled by one GM (Second level) and both GMS are
controlled by CEO (third level). There are different levels (this is called hierarchy). If
we want to compute the salary of the company it is sufficient if we know the salary of
team 1 in level 1(assume the salary is same for the given post). No need to worry
about individual salary. But if someone is absent for a particular day, then if other
person works for extra time, then we must know the individual salary details to
compute the salary.

Same thing here. Hierarchical file contains overall info (to reduce the size of file) and
flat file has complete information about all the layers.

5
 LAYOUT (CONTD…)

Example
A sample part of a
chip

6
M1
Via 12

M2

The file has different layers (numbered from 1 to...)

A table which correlates the layers to numbers is also
provided Layer Number
M1 11
V12 12
M2 21
V23 22
M3 31
V33 32
M4 41

As mentioned, layout contains information about all the individual layers. Here in this
slide, you can see the information about M1 layer, via 12 and M2 layer. Please note
here via12 (black squares) has to be align properly w.r.t to M1 and, similalrly M2
(green squares) should be aligned with via12 (how to align – we will see in
photolithography section under “ alignment”). Do remember, all these information
are quantitative.

A table which correlates the layers to numbers is also provided in the file as shown in
the slide.

6
 LAYOUT (CONTD…)
❑ Via and contacts are shown as squares/ rectangles
(rare cases) in the layout. Others are in rectangular
geometry
❑However, the mask will have circular (or in rare
cases elliptical) holes
❑ Completely filling rectangular features (with metal) in high
aspect ratio is difficult
❑ Aspect ratio: Depth/width (or diameter)

Dia width
Dia width

height height
7

Low aspect ratio High aspect ratio

Read the slide. It is self explanatory.

I am trying to explain aspect ratio using the figures.

7
 LAYOUT (CONTD…)

This depth size (Z) will not be

in layout file. It is provided in
the process flow sheet.
Layout have info on X and Y

Picture courtesy: http://www.eetimes.com/document.asp?doc_id=1262098

As mentioned earlier, the layout gives 2D (X and Y information) view of the chip. The
third dimension (depth, marked as “Z” ) information will not be there in the layout
file. This info will be available in process flow sheet and could be controlled during
manufacturing process.

8
 LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
9
❑ the transferring of patterns from the mask to the wafer

Now , moving to how to make masks using the information available in layout file.

9
 MASK
 Layout for mask is designed using CAD tools
(Magic, cadence). This is stored in magnetic tape.
 This will be feed to the pattern generator.
 Emulsion coated glass plate
 Chrome plate glass plate
 Composite mask (one layer needs to be defined
with other layer
 Separate level of mask for each layer

 Magnification higher

10

Once the physical layout is ready , we have to create mask. Now let discuss about Mask:

Physical Layout for mask, which we discussed so far, is designed using CAD tools (Magic,
cadence). This is stored in a magnetic tape.
This will be feed to the pattern generator (Mask Making machine). Mask is something like
hardcopy of the physical layout.

What is the material used for making masks?

1. Emulsion coated glass plate

2. Chrome plate glass plate

So either emulsion or chromium is coated on the glass substrate and the patterns are written
on this emulsion/chromium. Substrate is glass as the substrate being used in
photolithography must allow the light of given wavelength to pass through and should have
zero defects ideally. Otherwise, it may alter the light travelling path. Cost also counts here.

We have two types of mask:

1. Emulsion coated – cheaper, resolution is lower, coating quality will be poor. Usually we
use this when the dimension size is bigger. Ex: if actual feature size is 5 micron, we will
be getting 5.5 micron. This is allowable as it won’t affect the chip performance
significantly. But if the actual size itself is 1 micron, then getting 1.5 micron may affect
chip function. So we have to move chrome plated glass plate.
2. Chrome coating – expensive, good resolution, can obtain good coating quality. In IC
fabrication, we are using this currently.

10
Here resolution means what is the minimum size that we could print on the wafer.
We will discuss in detail later.

As we already discussed in slide no. 5, the one layer needs to be aligned w.r.t other,
initially a composite mask is prepared with all the structures
aligned w.r.t one another. Then, this composite mask is broken into separate mask for
each layer.

10
 MASK (CONTD..)
❑ The layout file is given as ‘input’ the mask making
machine
❑ Mask may be a plate of glass, coated with chromium.
On top of chromium, a photosensitive coating is
applied
❑ A mask is often referred to as ‘chrome’
❑ E-Beam, ‘sensitizes’ the areas
❑ E-beam writer (electron beam)
❑ Scans the “blank” mask
❑ Develop the resist
❑ Remove chromium on the ‘exposed’ areas 11

How the mask is created physically? It is explained in this slide.

The layout file is given as ‘input’ to the mask making machine. We have to take the
blank mask. Mask may be a plate of glass, coated with chromium as discussed in the
previous slide. On top of chromium, a photosensitive coating (e-beam resist) is

applied. A mask is often referred to as ‘chrome’.

Then, We have to use E-beam writer (electron beam). E-beam is act like a pen. We
can write patterns directly on the given mask. For this, we scan the blank mask using
e-beam. E-beam moves pixel to pixel. At some pixels, e-beam is in ON state and
sensitize the e-beam resist (meaning e-beam resist is softened and hence could be
removed easily in developer solution). At some pixels, e-beam is in OFF state and
won’t sensitize the e-beam resist.

So, E-Beam, ‘sensitizes’ the areas and develop the

11
resist. It means e-beam resist is removed in certain
region (exposes the underneath Cr layer) and not
removed in remaining region (does not expose the
underneath Cr layer). Then the chromium will be
removed on the ‘exposed’ areas. I will post a video
on this for better understanding.

11
 MASK (CONTD..)
❑ Relatively slow process
❑ beam goes to each ‘pixel’ which has to be written ‘on’
❑ switches “on” and then “off”
❑ moves to the next pixel which has to be written on

❑ Mask has to be very clean.

❑ Any particle on the mask will cause incorrect ‘feature’
in all the chips
❑ ==> chips will to fail

❑ A mask is then coated with a clear film, to

protect it.
❑ Eg. If a particle falls on the mask, then you can remove
the clear film and put a new film. (Easy to ‘repair) 12

During scanning(writing), it goes pixel by pixel. So very slow process. Sometimes, it

may take even one day to write a mask. So the cost of the mask will also be high. The
cost varies from lakhs to crores depending upon complexity involved in the chip
design. However, we need one mask for making many chips. So this method is
preferable in semiconductor industry for making masks.

Once the mask is made, it has to be very clean. Any particle on the
mask will cause incorrect ‘feature’ in all the chips.
So, the chips will fail.
So, the mask is then coated with a clear film, to protect it. Eg. If a particle

falls on the mask, then you can remove the clear

film and put a new film. (Easy to ‘repair).

12
 MASK (CONTD..)
❑ If a mask gets dirty in a particular location,
❑ with in a ‘field’, a die will always fail

13

White region- chips; violet region – space b/w chips. If some particle fall on violet
region, it won’t affect the chip function. But if particle falls on white region, it will
affect the chip performance.

13
 MASK (CONTD..)
❑ A mask may be 100 mm x 100 mm (for example)
❑ The size is decided by the size of the lens in the lithographic tool
❑ A mask is usually 4 to 5 times larger than the actual feature. The
features are ‘reduced/ zoomed out’ during the lithographic process
❑ Correspondingly, a mask is referred to as ‘4x mask’ or ‘5x mask’
❑ Example: If you want a 100 nm wide line on the wafer
❑ layout file will show 100 nm wide line on the screen
❑ mask making machine will enlarge everything by 4
❑ Actually, layout file will be converted to another file which will enlarge
it by 4 and then the mask making machine will use it.
❑ The process is sometimes called MDP (Mask Data Preparation)
❑ Mask will have 400 nm wide opening and
❑ Lens in the litho process will ‘shrink’ the image to 100 nm. 14

Read this slide. It is self explanatory.

Why we are zoomed out? Because,in this case, the resolution of lithography is not
limited by the resolution of the mask. For example, if there is a slight variation in the
mask pattern dimension, it will get zoomed out (i.e. variation will decrease) when it is
printed on the wafer.

We will discuss about resolution in detail in the upcoming slides.

14
 MASK (CONTD..)
❑ A mask may be 100 mm x 100 mm (for example)
❑ So, one ‘print’ will be about 25 mm by 25 mm, on
the wafer.
❑ A chip may be only 5 mm by 4 mm

❑ So, one mask will have perhaps 20 chips, if the

chip is small

❑ The gaps between the ‘real chips’ are

used for
❑ alignment marks (TBD)
❑ test structures (TBD)
15

TBD- to be discussed later

15
 MASK (CONTD…)

Mask

Patterns in mask to be transferred

to wafer

Wafer
with PR
coating
16

This slide just show how the mask is used in lithography process. Green color – glass
substrate black color –chromium patterns

Yellow-color –photoresist
Grey – wafer

The patterns in mask have to be transferred to wafer. How? Using photolithography

technique. So, we will see next the same.

16
LAYOUT, MASK AND LITHO
❑ Layout
❑ Convert electrical design to physical design
❑ 2D ‘picture’ of the final chip (quantitative)
❑ Mask
❑ hard copy of the physical layout (similar to photo
negative)
❑ Can be used to generate many chips (similar to
obtaining many copies from a negative)
❑ Photo (Lithography)
❑ Process of obtaining a ‘picture’ from a ‘negative’
17
❑ the transferring of patterns from the mask to the wafer

17
 LITHOGRAPHY

18

Litho means stone. In the olden days , the patterns are engraved on the stone and
then some ink will be applied on to these patterns. Finally, patterns are transferred
to the paper as shown in the slide. In semiconductor industries also, the patterns are
transferred from mask to wafer using light. That’s why it got the name
photolithography.

18
 LITHOGRAPHY
Coat the wafer with light
sensitive material (photo-
resist)

Place mask over the wafer,

align the mask w.r.t wafer,
focus the light through the
mask
Exposure for a precise
amount of time

Developing and Etching

Move (Step) to the next ‘Field’

Stepper
Actually, the wafer moves, not the litho system 19

Repeat the above procedure

Read the slide. I will post a short video on this for better understanding. This is the
overall process sequence. The details of each step will be discussed later in this
chapter.

Developer: Once the photoresist is exposed to radiation, it is either

hardened/softened. Then we have to dip the wafer in the developer solution. The
relatively softened region will be removed in the developer solution. This stage is
called developing.

Stepper: wafer size is larger than mask. So, when we transfer patterns from mask to
wafer, it is one “print” as highlighted by green color square. Then we have to move to
other grey square and repeat the same procedure.

19
 LITHOGRAPHY: BASIC STEPS
After the whole wafer is exposed....
Repeat for other wafers in the lot
Crude schematic below

Develop the lot

Etch the open areas

Remove the remaining

photo resist and the etch
products

20

Note: Etch product forms a thin film or ‘veil’. Removal of the veil is
called ‘de-veil’

Read the slide. Self explanatory.

20
 FIGURES OF MERITS OF LITHOGRAPHY

 Resolution
 Minimum feature size
 Precision with which minimum feature size can be
incorporated in the wafer
 Minimum size and accuracy are interrelated
 Throughput
 How many wafers can be processed in a given time
 Cost
 E-beam lithography –slower process
 Depth of focus
 Many layers of mask
21
 Mask 1 has to be aligned with Mask 2

Before seeing the types of lithography process in detail, let first discuss figures of
merit associated with lithography.

Resolution means, what is the minimum feature size that can be incorporated in the
wafer. For example, if we have a line of width 0.1 micrometer in mask, then, whether
that can be transferred to wafer as same or as 0.12/0.8 micrometer (20% variation) or
0.14/0.6 micrometer (40% variation). We want this variation to be small i.e.
resolution to be better. So, the resolution refers the precision with which minimum
feature size can be incorporated in the wafer. How accurately we are transferring the
patterns from the mask to the wafer. So the minimum size and accuracy are
interrelated.

Throughput – Read the slide.

Depth of focus – As we have many layers of mask, we have to align the mask of
particular layer with mask of other layer. Then we have to focus the light. Focusing on
particular layer? or focusing on other layer? Read the next slide for better
understanding.

21
 DEPTH OF FOCUS

22

In LHS photo, you could clearly see the batsman (first layer), wicket keeper (second layer) but
not audience (third layer). In RHS photo, you could clearly see bowler (First layer), but not
wicket keeper (second layer) and audience (third layer). Here the cameraman focusing on
first layer , that’s why third layer is blurred. If the depth of focus is better for camera, then
you could see first and second layer clearly. If it is not good, then second layer might also get
blurred.

Here in photolithography process, as we are dealing with many layers and focusing, the
depth of focus needs to be good.

22
 LITHOGRAPHY: RESOLUTION
Resolution and other parameters


 = k1
NA
 = Minimum Feature Size  = Wavelength of light used
D
k1 = Raleigh Constant NA = Numerical Aperture=
2f
f – focal length of lens
D- diameter of the lens
Depth of Focus or Depth of Field (DOF)

DOF = k2
NA2
We need small  and large DOF 23

Better resolution = smaller sigma value.

So decrease the wavelength to reduce the sigma value. But it also affect depth of
focus(DOF). DOF has to be higher.

So we cannot reduce the wavelength to a much smaller value.

23
 PHOTORESIST
 Positive
 Throughput is lower
 Resolution is higher
 Resin + photosensitive material+ solvent
 Negative
 Resolution is lower
 Polymer + photosensitive material + solvent
 Swelling up decreases resolution
 Cross-linking not possible if oxygen is present

24

We have seen photoresist has to be coated on top of the wafer during

photolithography process. There are two types of photoresist (1) positive and (2)
negative photoresist.

In positive resist, we have a mix of resin and photosensitive material as a photoresist.

Upon exposure to radiation, the photosensitive material absorbs light and transfers to
resin molecules. Thus, the chemical bonds of the molecules get broken in exposed
regions, hence property changes. Here, the exposed regions are softened. We have
to make sure that the photoresist material is fully developed during exposure. So we
need relatively more time for exposure. Hence throughput is lower in positive
photoresist.

In negative photoresist, we use a mix of monomer chains and photosensitive

material. Upon absorption of radiation, monomer chains likely to crosslink and hence
molecular weight goes up. So it gets hardened upon receiving radiation. In this case,
as polymers usually swelling up when we put wafer in the developer solution, the
resolution might not be better as in the case of positive photoresist. Also, cross
linking will not occur if oxygen is present. So we need oxygen-free environment
(preferably nitrogen environment) to perform this operation.

24
 PHOTORESIST (CONTD..)

❑ Mostly positive resists used now

❑ More resistance to pinhole formation

❑ Easier removal (stripping)

❑ More expensive

-ve resist; most area open +ve resist; most area blocked

25

As the resolution is better in positive resist, we are mostly using positive resists now.

Few more advantages of using positive photoresist.

Look at the figure: In the positive resist, most of the areas on the mask are blocked
compared to –ve resist. So chips are not more likely to fail in the presence of dirt
particles if we use +ve resist. Hence positive resist has more resistance to pinhole
formation.

In positive resist, in the developed areas, the resist becomes softened unlike in
negative photoresist where it is hardened. So stripping is easier here.

On the other hand, the disadvantage of positive photoresist is

Very expensive compared to negative photoresist.

25
 PHOTORESIST (CONTD..)

Photo Resist properties

❑Response to a given wavelength (spectral response)

❑ Solubility differential between unexposed vs exposed regions
❑ Etch/ Implant resistance
❑ Resolution

26

These are some of the properties of photoresist that one has to consider while
choosing for photolithography process.

Solubility differential: The difference in dissolution rate of softened and hardened

part of resist in the developer solution. This should be high like 100:1

After lithography, we will be performing many operations such as etching,

implantation and harsh conditions will be employed during these steps. The
photoresist has to withstand those harsh environment.

Read the slide for other properties and those are easy to understand.

26
 LITHOGRAPHY : DETAILS

27

To get the same pattern on the wafer, we have different masks for +ve and –ve
photoresist.

27
 TYPES OF LITHOGRAPHY
 Optical
 Photoresist
 UV light
 E-Beam
 E-Beam Resist
 No need of Mask
 E- Beam is acting like a pen
 X-ray
 Same as Optical
 Instead of UV light, X-rays will be used
28

So far we discussed, the principle of photolithography technique and how the

patterns are written on the wafer.

Now, we will discuss the various types of lithography.

There are mainly three types as shown in the slide.

The principle of optical and x-ray lithography is the same. The only difference is that,
as the name suggests, in X-ray lithography, we will use X-rays instead of UV light. In
both the cases, the resist what we are using is called photoresist.

The E-beam lithography technique, we have already discussed it during mask making
process.

Here in this technique, we don’t use any mask. The resist what we are used is called
as E-beam resist. Here patterns are directly written on the wafer.

The pros, cons and applications of these processes are discussed in the upcoming
slides.

28
 OPTICAL
 Oldest and still in use (popular)
 Steps are already defined
 Sub- Classification
 Contact Printing
 Wafer – Mask in Contact with each other
 Resolution will be good
 Mask life will be shorter
 Wafer contamination is possible
 Proximity Printing
 Close to each other (10- 25 micron)
 Resolution is sacrificed minimally
 But life of wafer will be improved

 Projection Printing
 Image if focused on the wafer using suitable optic technique
 Penalty-cost
 Resolution could be limited by diffraction limit which in
turn depends on wavelength of light. (as discussed before) 29

The optical lithography are further classified based on the distance b/w mask and
wafer.

Please see the next slide for figure.

29
 OPTICAL LITHOGRAPHY

30

The images for contact, proximity and projection coating are given in this slide.

30
 MICROELECTRONIC
FABRICATION
1 3. Photolithography

In the part 1, we have discussed how mask is produced using E-beam lithography for
making chips. We have also discussed various types of lithography (1. Optical 2. E-
beam and 3. X-ray ) in which, the optical lithography was discussed in detail. What are
the major steps involved and what are the sub types of optical lithography. We have
seen the difference between positive and negative photoresist.
We discussed about figures of merit as well (Resolution, DOF and throughput).

In this part 2, we will see more details about lithography steps and other types of
lithography (E-beam and X-ray).

1
 LITHOGRAPHY: DETAILS
Exposure

Litho Tool (current): Projection aligners

Stepper vs Scanner
Stepper: What we saw before
Scanner: Actually Step & Scan
Need smaller lens for the same sized mask
Or with same sized lens, can handle larger mask

Stepper
Step & Scan

MASK
Lens Lens
2

The lithographic equipment which we have discussed so far is also called a stepper
because it exposes one part of the wafer to the light, and then moves or steps to the
next location and repeats the exposure. Recently, a more sophisticated technique
called scanning is used. In this, the exposure is not done in one shot. Instead, once
the mask is positioned above the wafer, light is shone on only a part of the mask and
the wafer. Then the wafer and the mask are moved, as shown in figure. This step is
called scanning. When the entire mask is covered, the scanning is completed. Then
the wafer is moved to the next step and the scanning continues. Thus, even though
the equipment is called as scanner, it is actually a step-and-scan technique.

What is the need for scanning? Large lenses, free from aberrations, are extremely
expensive. If only a stepper is used, then for a given mask size, a very large lens is
needed. The diameter of the lens must be at least 1.4 times the size of the mask.

However, if scanning is available, then the task can be accomplished using a smaller
lens. Consider the following example. During scanning, only a part of the mask is
exposed. In this example, the entire ‘width’ of the mask is not exposed at all the
times, but only a small part of the ‘width’ is exposed. By moving the mask (and also
the wafer), the entire mask can be covered while using a smaller lens. Even within
this small lens, only a small part should be absolutely free from aberrations. Thus for
a given mask a smaller lens can be used in step-and-scan systems. Alternatively, for
a given lens, a larger mask can be used in a scanner while only a smaller mask can
be used in a stepper.

2
 LITHOGRAPHY: DETAILS
Photo Resist Coating

Dynamic coating

Low rpm (500) dispense

High rpm (5000) thinning (form uniform film)
Final resist thickness depends on rpm and time
and viscosity, surface tension, drying characteristic of
solvent...

Moving arm to enhance uniformity

We have seen the overall steps involved in the photolithography process which
involves coating, etching etc.. Now we will discuss these steps in detail.

We have seen, we could go for either positive or negative photoresist. However, we

mostly prefer positive resist as it gives better resolution. Now, we will discuss how to
coat this photoresist (positive or negative) on the given substrate.

Spray coating and spin coating are available. However, spin coating is widely used
because of high throughput. We have to apply the photoresist in the liquid form and
the solvent could be varied to alter its viscosity. In the spin coater, we have Spinner
chunk by vacuum , in which we have to keep the wafer. Then it has to be rotated at
500 rpm and then dispense the PR at the centre of the wafer. This is referred as
dynamic coating. In case, if the wafer is kept at rest while dispensing PR, it is referred
as static coating. Dynamic coating is preferred especially when the wafer diameter is
large so that the PR spread to a large diameter. Once, PR covers the whole wafer, we
have to increase the spinning speed to 5000 rpm. So that the PR coating thickness
could be controlled. Please note that the speed and time are the variables to control
the PR thickness on the given wafer. The properties of photoresist solution (viscosity,
surface tension, drying characteristic of solvent) also plays an important role.

The uniform thickness across the whole wafer is our main focus. Sometimes, to
achieve this, we will use moving arm in the spin coater. The arm will move from
centre to edge of the wafer to maintain the thickness uniform.

3
 LITHOGRAPHY: DETAILS
Pre Expose Bake

Soft Bake:
To drive out the solvent
Resist is still ‘soft’, but not liquid like
Temperature:
Baking options:
Hot Plate (manual, moving)
Convection Oven (may form crusts)
Infra-red (wafer surface heated)
Microwave (volume heating)
Vacuum baking (radiation)

After photoresist coating, we have to expose the light. Before exposing the light on
the photoresist, it has to be baked (heating). This is referred as pre exposure
bake/soft bake. This is done to remove the solvent from photoresist and thereby
increasing stability. i.e. if the solvent is there b/w PR and the substrate, PR may
peeled off during subsequent steps. Film thickness is also reduced due to the removal
of solvent. But still, the resist is soft.

There are many options for baking as shown in the slide. But, Usually baking is
performed in convection oven at 90°C for 30 minutes. It is a time consuming process.
Hence, currently we are using hot plate method. Here, the wafer is brought either
into intimate vacuum contact with or close proximity to a hot, high-mass metal plate.
Due to the high thermal conductivity of silicon, the photoresist is heated to near the
hot plate temperature quickly (in about 5 seconds for hard contact, or about 20
seconds for proximity baking). The main advantage is that it requires less time. In
general, proximity baking is preferred to reduce the possibility of particle generation
caused by contact with the backside of the wafer.
When the wafer is removed from the hotplate, baking continues as long as the wafer
is hot. Hence we could not control the baking process So, hotplate baking is always
followed immediately by a chill plate operation, where the wafer is brought in
contact or close proximity to a cool plate (kept at a temperature slightly below room
temperature). After cooling, the wafer is ready for its lithographic exposure.

4
 LITHOGRAPHY: DETAILS
Post Exposure Bake
Similar to pre-exposure bake
Help minimize standing wave effects
Developing
Immersion
Spray develop
Plasma (dry) develop

Rinse

Hard bake: 200 C, 30 mins (for example)

To protect from etch/implantation
Resist flow
Ridges are
formed on the
photoresist
pattern sidewalls 5
due to standing
wave effect

Once the wafer is exposed for radiation, again it needs be baked (post exposure bake). The
baking process is as same as pre –exposure bake. But the purpose is different. This is to
reduce the standing wave effect. When the light pass through the photoresist and reach the
substrate, it may get reflected. The reflected light may interfere with the incoming light and
result a standing wave. This is undesirable as it form ridges on photoresist pattern as shown
in the slide (if you look at the sidewalls, it is not smooth).
To eliminate this effect, we have to go for post exposure bake.
The mechanism is still unclear. However, one of the hypothesis is diffusion of photoactive
molecules occurs during baking that help in minimizing standing wave effect.
After Post exposure bake. We have to develop the photoresist coating. This is done by (1)
immerse the wafers in the developing solution or (2) spraying the developing solution on the
wafer or (3), expose the wafer to the plasma (gaseous state and hence dry). We will discuss
about plasma more in the subsequent chapters. Commercial developing solutions are
available. One of the main chemicals is tetra methyl ammonium hydroxide (TMAH)

After developing, rinse the wafer with suitable solvent (water) to remove any residual
developing solutions.
Again, it needs to be baked at higher temperature (200 degree) – Hard baking . So it
becomes hardened (i.e. densified) so that it would withstand harsh etch conditions. Because,
after photolithography, etching will be followed as discussed previously.
In summary. Although we discussed major steps involved in photolithography process
previously, now we came to know that baking is necessary at different stages as discussed
here.

5
 LITHOGRAPHY: DETAILS
Light Sources
Hg Lamp: Filter
G,H, or I-line (365 nm)
Excimer Lasers (DUV)
ArF193 nm
EUV, X-Ray, E Beam (in R&D)

I
G
H

Intensity
6
400 nm 600 nm

What are the light sources, we normally used for photolithography? Please see the slide
Optical lithography – UV light (wavelength in the range of 350- 400 nm)
DUV-Deep ultraviolet radiation (100-280 nm)
EUV- extreme ultraviolet radiation (10-100 nm).

For example, Hg lamp emits radiation of various wavelengths. By using suitable filter, we
choose particular wavelength in the UV- range (either G or H or I line ). Please wavelength is
an important factor as it affects resolution and depth of focus as discussed previously.

An excimer laser uses a combination of a noble gas (Ar, Kr, or Xe) and a reactive gas (F or Cl).
Under the appropriate conditions of electrical stimulation and high pressure, a pseudo-
molecule called an excimer is created, which can only exist in an energized state and can give
rise to laser light in the DUV range. For EUV, we use laser produced plasma. As I said in the
previous slide, we will discuss about plasma in the next chapter. Since almost all materials
absorb EUV, the EUV lithography must be done in vacuum. The mask and other optics would
be using reflective method and not refractive (normal lens system) method which is
commonly employed in optical lithography.

Remember for optical lithography, we use UV radiation. Similarly, electron beam for E-beam
litho and X-rays for X-ray lithography. E-beam and X- ray lithography are in developing stages.
They are mainly employed in specific applications and not for making commercial chips. The
major reason is higher cost associated with it. We will see this in detail in the upcoming
slides.

6
 E-BEAM LITHOGRAPHY
❑Geometries
❑Direct writing
❑Automation
❑Greater depth of focus

❑Beam dia : 0.01 micron -0.5 micron

❑Scan field (so small)

❑Good resolution
❑Lower throughput

❑E –Beam resist: Positive (lower sensitivity) and Negative ( lower

resolution) [ similar to optical lithography]

❑Proximity effect [ one of the disadvantges]

7
❑E-beam sources

We discussed about optical lithography so far. The resolution of optical lithography is limited by the wavelength of light (UV) used. So,
researchers are exploring other types as well especially when we make chips of smaller size. Now we will discuss about E-beam lithography.
Although we discussed e-beam lithography during mask making process, we will discuss further here. Comparing to optical lithography, it offers
various advantages as listed below:
1. The feature size of less than 1 micron can be patterned using this technique as we are using electron beam of small diameter.
2. Here we are writing the pattern on the wafer directly using electron beam (similar to pen). It is a mask less technology. (3) So direct automation
is possible. Remember if we use mask, then alignment of mask w.r.t wafer comes in to picture that needs personnel. So automation is quite
difficult to implement there.
4. Compared to optical lithography, it offers greater depth of focus. Hence level to level (many layers/levels in the chip) registration is much
better here
The rule of thumb says, minimum feature size is 4 times the beam diameter. The electron beam diameter varies from 0.01 micron to 0.5 micron.
The (focused) electron beam is scanning the wafer using computer control. Let divide the wafer in to number of pixels (m* n array). The wafer is
coated with photo resist. The electron beam goes to (1*1) pixel. If the pattern doesn’t lie in this pixel, the electron beam goes to OFF state. The
photoresist will not be irradiated. Then the electron beam goes to (1*2) pixel. If the pattern lies here, then electron beam is ON and irradiate the
photoresist. This way electron beam goes to every pixel point (scanning the wafer).
The electron beam could move only in the small region. This is called scan field. If you want to scan the whole wafer, then wafer needs to be
moved. Thus, wafer is kept on the moving XY table. The table cold be moved in X as well as in Y direction.
Since it is a direct writing, great resolution could be achieved. However throughput is lower as it is a very slow process ( moving pixel by pixel). If
you reduce the electron beam (more focused), the resolution will be better. However it will also affects the scan field (more slow and less
throughput). The scan field is 2000 times the beam diameter.
Hence this type is not implemented in the IC industries yet for making chips. But it is used for making mask. Because on mask is sufficient for
making many chips. So we are not bother about throughput for mask making.
Similar to optical lithography, here too we have positive as well as negative photoresist. The only difference here is the resist has be sensitive to
e-beam radiation unlike in optical litho where resist is sensitive to UV light. So the chemicals what we used here is different.
One of the disadvantages of e-beam lithography is Proximity effect- Will post a video on this.
Regarding e- beam source:
Generally, we have to use materials having low work function (the energy required to remove an electron from the solid surface to the outside
environment i.e. a point in vacuum , immediate point above the solid surface). So if materials having low work function, it could emit electrons
easily. The energy provided to emit electrons is either thermal energy (thermionic emission) or electric field (Field emission/ cold field emission).
Combination of thermal energy and electric field (Thermal field emission) is also and it offers better resolution.

7
 X- RAY LITHOGRAPHY
❑ Faster throughput (vs e beam)
❑Good resolution (vs optical)
❑No proximity effect (secondary electrons has lower energy)

❑Proximity type (40-50 micron)

❑X ray mask (thin membrane with gold caoting)

❑Resist :PMMA
❑Geometric effect.

❑Next generation Lithography: Immersion lithography

The third type of lithography technique is X-ray lithography. This is much similar to optical
lithography, The major difference is , we use x-ray instead of UV light to irradiate the
photoresist.

We have seen three sub types of litho based on the distance b/w mask and wafer previously.
Here we have to go proximity type. The distance b/w wafer and mask is 40-50 micron.

It has following advantages

1. Compared to e-beam litho, it has high throughput as it is not moving pixel by pixel
2. Compared to UV, x-ray have small wavelength (0.01 to 10 nm). The diffraction
limitations of normal lithography would not be present. So X-ray litho has better
resolution than optical litho.
3. In e-beam, secondary electrons cause proximity effect. But here, secondary electrons
does not have much energy. So no proximity effect.
4. X –ray will not be absorbed by dirt. It is an advantage as presence of dirt on the mask will
not affect the patterns.

The diadvantages are

1. It is difficult to bend and focus the X-rays and hence only 1X mask can be used.
2. However, x-rays can penetrate through most of the materials. This is an disadvantage.
Hence, we cannot use the same mask (chromium coated glass plate here). We have to
use special materials as shown in the slide.

8
3. A problem common to all next generation techniques is that they are very
expensive.
4. Geometric effect –other disadvantage. Will post a video on this

Although X- ray litho is not employed in semiconductor industries as it is expensive, it

is applied in micro electro mechanical system (MEMS) fabrication.

Immersion Lithography: In this technique, a fluid such as water (or preferably with
high refractive index) is introduced between the wafer and the lens. If the refractive
index of the fluid matches that of the lens, (and assuming that the refractive index of
the photoresist is similar to that of the lens) then the images formed at the bottom of
the photo resist will be with high resolution. Comparatively, if the fluid were not
present, the light path will be different and the resolution will be poorer. Even if the
refractive index of the fluid is not the same as that of the lens, if it is higher than that
of air, it will enhance the resolution. The resolution enhancement obtainable through
immersion lithography is about 30 to 40% and an increased depth of focus (40 to
70%) can also be achieved.

The requirements of the fluid are that it must be compatible with the photo resist
and the lens and that it should not absorb the light used (< 5% absorption). High
purity water satisfies these requirements. Its refractive index is 1.47 and it can be
doped with sulfates or phosphates to increase the refractive index slightly.
Commercially, water is continuously circulated between the wafer and the lens, and is
maintained at a constant temperature since the refractive index can change with
temperature. Care must be taken to ensure that it is particle free and bubble free,
that it is removed after exposure, and that leaching from the photo resist is minimal

8
 PRODUCTION ISSUES
Key parameters:
resolution
alignment (or misalignment)
depth of focus
Partial and full field
Resolution:
indicates the smallest feature (or space) that can be produced
One of the limiting factors is wavelength of the light used

So far we have seen three different types of lithography. Now we will see, production
issues (Reference for this note : Prof. S. Ramanathan from IIT Madras)

One of the major production issues is resolution which I have already discussed it.
Anyways, I am repeating some key points regarding resolution in the next slide.

9
 LITHOGRAPHY: RESOLUTION
Resolution and other parameters


 = k1
NA
 = Minimum Feature Size  = Wavelength of light used
D
k1 = Raleigh Constant NA = Numerical Aperture=
2f
Depth of Focus or Depth of Field (DOF)
Details Later


DOF = k2
NA2
We need small  and large DOF
10

Better resolution = smaller sigma value.

So decrease wavelength to reduce the sigma value. But it also affect depth of
focus(DOF). DOF has to be higher.

So we cannot reduce the wavelength to a much smaller value. SO how to improve the
resolution for the given wavelength of light. See next slide.

10
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Presence or absence of other features nearby (proximity) will affect
the optical behavior
Corrections are made in the layout to account for it (Hence, Optical
Proximity Correction or OPC)
Anti Reflective Coating (ARC)
Phase Shift Masks

11

We have seen resolution is limited by wavelength of the light. We will improve the
resolution without decreasing the wavelength of light by using various techniques
(also called as RET) . Three important techniques will be discussed in this chapter. The
first one is OPC i.e optical proximity correction. See the next slide for better
understanding.

11
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Ideal Real

Mask

Resist

Presence or absence of neighboring features will alter the width /

space of the feature

12

Ideally, we want the light to pass through the mask layer as shown in LHS figure.
However, as light is an electromagnetic wave, it gets diffracted when it passes
through an opening. So, as shown in RHS figure, the diffraction of light will occur. This
leads to the inaccurate printing of mask patterns on the wafer. For example, the
space b/w the two features will get widened as shown in RHS figure. So, the
resolution will go down. So how to improve it?

12
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Biasing
OPC
Rule based (simple rules, reasonably effective)
Model based (more complicated, computationally intensive,
better)

Original After Bias

M1 layout M1 layout

13

It is clear from the previous slide that the presence or absence of neighbouring lines makes a
difference on printing a given line. Even if there is no other line nearby, the image will not be exactly
the same as the one in the mask.
In the case of line without any neighbour (isolated line or iso line), the diffraction effects may make
the image bit smaller than planned. For example, if the mask contains 100 nm line, the image on the
wafer may be only 90 nm. So, in order to print 100 nm line on the wafer, the mask can be made with
110 nm wide line. Please note that in this example, we are assuming that the mask is 1X mask and not
the usual 4X mask. In case of a 4X mask, the explanation will be as follows. If we use 400 nm wide line
in the mask, the ideal lithographic process will produce 100 nm wide image on the wafer. But the
actual image may be 90 nm due to diffraction. Hence, to produce 100 nm image on the wafer, the
mask may be made with 440 nm wide line. This method is called biasing and is one part of OPC. This is
shown in this above figures. LHS figure 2.10 is the layout before OPC while RHS figure is the layout
after OPC. Notice the increase in size of some of the lines. Also notice that the left most line, which is
already large, is not altered. Thus, not all the lines are altered by OPC. (For example, if the feature
dimension on the chip is 1000 nm, but we are getting 1010 nm on the wafer, it will not affect the chip
performance significantly. However, if the feature dimension is 100 nm, but if it is printing as 110 nm,
then the chip function may get affected.
But we cannot just make all the lines larger and expect that everything will print correctly. A few more
modifications are necessary. Depending on the method used to make the corrections, OPC can be
classified as “rule based” or “model based”. Rule based OPC is somewhat empirical. For example, one
rule may say that “If there are two lines separated by 200 nm, then increase the width by 10 nm. If
they are separated by 300 nm, increase the width by 5 nm” etc. This is relatively simple and is
reasonably effective. However, when one tries to make very complicated chips, this method is not very
effective.
“Model based OPC” actually models how the light will travel and how diffraction will alter the image,
over the entire mask .It is very computationally intensive. It can run on very powerful computers for
many days for a single layer of mask. But if the modeling is done correctly, then the results are better
than what one would obtain from rule based OPC.

13
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Biasing (zoomed picture)

Width is changed (usually increased)

1 Line End is changed (usually extended)

The idea is, after photolithography using

mask with structure 2, the resulting structure
will be close to what we planned originally
(structure 1)
i.e. We try to account for non-idealities in
2 the lithography process

14

A few examples of the changes made by OPC are shown in the above figures. Note
that the width is increased a little and the line-end is extended a bit more.

14
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Other corrections A “Tee” may not “print” correctly

3
1

What we want is structure 1

If we make a mask like structure 1, we will

end up getting structure 3

2 Hence, we make a plan like structure 2 to

obtain on the wafer what we want
Add “dog ears” to the lines
15

The figure 1 and 2 show a T shaped structure before and after OPC respectively. If
one actually makes a mask with the T shaped structure without OPC, then the
structure on the wafer will appear somewhat like the figure 3. i.e. it will cause
“necking” or reduction in the neck of the T junction

In order to ensure that a real T structure is obtained on the wafer, one needs to add
little bit of squares near the T junction, as shown in fig 2. Sometimes these are
referred to as “dog ears”. Thus we add dog-ears to the T junction so that it will
actually print correctly on the wafer. Generally one needs to increase or decrease the
width and add the dog ears. Thus, fig 1 shows the ideal pattern that we want on the
wafer and the figure 2 shows the layout after biasing and adding dog-ears, so that we
will finally get the correct pattern on the wafer.

15
 LITHOGRAPHY: OPC

Taken from Intel website

16

One point that we need to remember is that increase in the width is not the same as
enlarging the layout. Here when the width is increased, the space gets reduced.
The above illustrations are simplified version of the OPC process so that one can
understand OPC. If one looks at the real mask before and after OPC, there will be a
lot more changes. However, the basics are what we have seen here. In order to gain
some idea of what a mask looks like before and after OPC., the picture taken from
Intel website is given here.

In the lithography process, the presence of one line will affect the printing of another
line, if the distance between the lines is within one micron. If the distance is more
than one micron, the presence or absence of a line will not make any difference. That
is the effect is felt only up to one micron in lithography process, whereas if one looks
at few other processes, the effect can be felt even further. For example, in a process
called chemical mechanical planarization, the length scale where one feature affects
the process of another, can be as high as mm. In these cases, the layout is again
altered to account for these non-idealities. Techniques such as slotting and
introducing dummy features are used to account for non-idealities in CMP. We will
see those details in the “removal techniques” chapter.

16
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Presence or absence of other features nearby (proximity) will affect
the optical behavior
Corrections are made in the layout to account for it (Hence, Optical
Proximity Correction or OPC)
Anti Reflective Coating (ARC)
Phase Shift Masks

17

The second one is ARC which is discussed in the next slide.

17
 ANTI REFLECTIVE COATING

If light reflected from the substrate surface – standing effect –

resolution decreased

Coat ARC before photoresist coating

18

The second resolution enhancing techniques or RET is the application of anti

reflective coating. This also called ARC or arc. During the lithographic process, we saw
that a thin layer of photo resist is applied on the top of the wafer and light is shone
from the top, through the mask. Some of the light will be reflected from the top of
the film and some of the light will pass through the film. After passing through the
film, a part of the light will again be reflected on the wafer surface .The incoming light
and the reflected light within the film can form what is known as a standing wave.
Essentially, the light reflected from the wafer will interfere with the light coming from
the top. This will distort the image, and hence we will not get the exact image on the
wafer.

In order to overcome this problem, the following procedure is used.

❑ First, on the top of the wafer, a film made of a material called ARC or anti reflective
coating is applied (LHS top figure). And then bake the ARC to increase its stability
as we do for photoresist layer (RHS top figure)
❑ On top of ARC, the normal photo resist is applied (LHS bottom figure) and then
bake it (not shown here).
❑ Then, keep the mask above the wafer and expose the light (RHS bottom figure)
❑ Now, when the light comes from the top, it will pass through the photo resist and
then through the ARC. Then it will fall on the wafer (See LHS figure in the next
slide). Most of the light will be absorbed by the photo resist, but some will not be
absorbed. When it passes through this ARC, ARC will ensure that the light will not
get reflected from the bottom of the wafer. This way there will not be any
interference and there will not be any standing waves.

18
❑ Then finally remove ARC and photoresist layer using suitable developing solution
(RHS figure in the next slide).

18
 ANTI REFLECTIVE COATING

19

What happens during expose and developing step is given here.

19
 LITHOGRAPHY: OPC
Resolution Enhancement Techniques
(RET)
Optical Proximity Correction
To ‘accommodate’ for diffraction effects
Presence or absence of other features nearby (proximity) will affect
the optical behavior
Corrections are made in the layout to account for it (Hence, Optical
Proximity Correction or OPC)
Anti Reflective Coating (ARC)
Phase Shift Masks

20

The third one is PSM which is discussed in the next slide.

20
 PHASE SHIFT MASK

2-Mar-22
Normal Masks OPC can correct only to
some extent
When the space and the

21
width are very small (and
similar to wavelength of
light used)....
Use Phase Shift Mask
(PSM)
Amplitude
Intensity

The third RET is called phase shift mask or PSM.

Earlier we saw that OPC can be used to account for diffraction to some extent. However, this
trick can work only up to some extent. When the space between two features or two lines
becomes very small, OPC will not work effectively. What is meant by very small? When these
spaces and the widths are similar to the wavelength of the light used, then we can say that it
is very small. For example, visible light is in the wavelength of 400 nm to 700 nm. Ultraviolet
(UV) light is of wavelength less than 400 nm. In the microelectronic industry, one currently
makes chips of less than hundred nanometer size. So, naturally, one cannot use visible light
for photolithographic process. Even when UV is used, the usual wavelength is about 193 nm
(actually deep UV). The electromagnetic waves in the range of 30 or 40 nm are called
extreme UV or EUV. In the beginning of 2010), companies are creating chips with features of
65 nanometer size using light of 193 nanometer wavelength. This is possible only because
they use phase shift mask (PSM).

What is a phase shift mask? How does it work?

First, we will look into the operation of a normal mask. Then we will see how the phase shift
mask is constructed and how it works. Consider a normal mask and two openings, as shown
in the animation in figure Here we are assuming that the mask and the wafer are of the
same size. i.e. the mask is one-to-one mask or 1x mask. Even in the case of 4x or 5x masks,
the arguments we make here will apply. However, it is easy to illustrate the issue in the 1x
mask.

The amplitude and intensity of light that the photoresist layer received is shown here. The

21
intensity is square of the amplitude. Look at the intensity and amplitude values at
point X (it is not Zero). The significance of the same will be explained in the next slide.

21
 PHASE SHIFT MASK

Amplitude-
Intensity- close
close to wafer
to wafer
Amplitude-
close to mask Normal Mask

Amplitude- Intensity- close

22
close to wafer to wafer
Amplitude- PSM
close to mask

Remember that lights are electromagnetic waves. The electromagnetic field very close to the mask will be very
close to ideal (blue rectangles). Ideally, if there were no diffraction, the light will come from the top and the mask
feature and the wafer feature will be identical. But light will bend near the edges and this is called diffraction.
What happens is the “opening” on the wafer will be larger. This is shown by the curve which looks like ‘hills and
valleys’. The peaks correspond to the openings and the valleys correspond to the blocked regions.
When the space between the openings is small, the valleys will be shallow . Thus, the pattern printed on the
wafer will be very different from the pattern on the mask. When the gap between the two openings is very small
in the mask, the corresponding openings on the wafer will begin to merge. We will not get two different lines but
we will get one large line on the wafer. Here, even if OPC is used, we will not be able to get two different lines.
In the top figure, we see that when the light comes through the mask, the phases of the light on the left side and
on the right side opening are the same (two blue rectangles on the positive side). Electromagnetic waves
(including light) are transverse waves and hence they have these two properties. One is the amplitude and the
other is the phase. The intensity of the light is proportional to the square of amplitude. Whenever the amplitude
is maximum, intensity will be maximum, and when it is zero it will be zero. When the amplitude goes to the
negative, the intensity will be positive because we are taking the square of the amplitude. The key point to note
here is that in both openings, the electromagnetic wave (i.e. light) will have the same phase.
Now, we want to use the same light (i.e. same wavelength) and still get this small gap printed on the wafer
correctly. In order to do that, we can use phase shift mask. Look at the bottom figure. We see there are still two
openings separated by the same gap, but in one of the openings, there is an additional material. This additional
material is there to change the phase of the light. In this case, the phase of the light passing out of the first
opening and the phase of the light passing out of the second opening at the same point they will have 180 degree
or pi radians phase difference . Thus, the phase of the light in one of this is shifted or changed. (one orange
rectangle at the negative side and the other one is at the positive side)
Compare amplitude closer to wafer in both the cases. In top figure (normal mask), the amplitude is not reaching
to zero even in the blocked regions. Ideally, we want maximum amplitude at the opening and zero in the blocked
regions. The intensity is also not reaching to zero. However, in the bottom figure (PSM), as the phase of the one of
the openings is opposite to other, the amplitude has to move from negative to positive and hence it has to cross
zero as shown in the figure. As intensity is square of the amplitude, the intensity is also zero at the corresponding
point (blocked region). Thus resolution will be better in this case.

22
 PRODUCTION ISSUES
Key parameters:
resolution
alignment (or misalignment)
depth of focus
Partial and full field

23

Now we will discuss about alignment issues.

23
 ALIGNMENT

RHS Image Ref: 24

Aligning one layer mems-exchange.org
w.r.t other layer

For most of the layers in lithography, alignment to another layer is necessary. For
example, in order to make a metal line correctly, it has to be aligned to the previous
layer (via layer) which connect the bottom layer to the top layer. The metal line
which is printed on the top should align exactly with the bottom layer. Otherwise the
connection will not function.

In ideal situation, everything will align perfectly. However, in practice the alignment
will not be perfect and there will be some misalignment. If the line widths and spaces
are of the size of say 65 nm, then the alignment tolerance is probably in the range
of 10 nm. i.e. We would like it to align perfectly with the previous layer, but a 10 nm
misalignment is tolerable. Thus even if the lines are off by 10 nm, they will conduct
and the chip will function. Beyond 10 nm, this will lead to problems and ultimately to
the failure of the chip.

The alignment is made using standard marks called alignment marks. A few
examples are given in figures. The top Figure is called “box in box” (i.e. one box
would be at the bottom layer and there will be a box on the mask of the top layer).
These marks are sometimes called “Fiducials”. The machine will align the box in the
mask such that it will exactly fall at the center of the other box. Another example,
shown in bottom fig is called cross. In this case, a cross will be there on the mask and
it must be aligned to fall exactly within the four square marks present in the previous
layer. These marks are usually present at the corners and edges of the masks and, the
space between the chips on the wafer.

24
RHS figure is given just to visualize how we perform alignment in lithographic
equipment. It has to be aligned perfectly both in X and Y direction.

24
 PRODUCTION ISSUES
Key parameters:
resolution
alignment (or misalignment)
depth of focus
Partial and full field

25

Now will discuss the DOF issues.

25
 DEPTH OF FOCUS

FOCUS EXPOSURE MATRIX

26

Incoming wafers always have topographic variations i.e. it is not very smooth. How can we
measure the tolerance level to the variation in topography?
One way to do that is as follows: Take a very planer wafer (standard wafer). Take a mask
with a well known pattern and then place it above the wafer and project the image on
to the wafer. Usually this is done with an auto set up, where the machine itself can find out
the exact distance where the focus will be best. Print the image and this should come
correctly. Next move the lens to the next shot and pull it away from the best focus
deliberately by a small distance (0.1 micron or 0.2 micron) and then take the image. In this
case, we are deliberately taking it out of focus and continue with the process. Similarly, in the
next shot, move the lens towards the wafer (push it towards the wafer) by 0.1 micron and
take the image. In the next row of chips, increase (or decrease) the exposure, while following
the same set of focus adjustments. Thus we are adjusting the focus and exposure in a matrix
like fashion. This is called focus-exposure-matrix.
Thus the neighboring chips will be made with slightly different focuses and exposures. The
remaining processes (such as deposition or etching) to make the lines will be identical. At the
end of this sequence, the wafer will be tested to see whether all the features are created
correctly. For example, if the best focus itself is not giving the features properly then this
process is really poor. But we may find that the best focus as well as 0.1 micron and 0.2
micron out of focus chips can yield good image, but 0.3 micron out of focus yield poor image.
Then we can say that if the incoming wafer is not planar up to +/- 0.2 microns then the
lithography process can handle that. Thus, the total ups and downs (maximum to minimum)
can be 0.4 micron in this case. It also means that if the planarity is poor, (i.e. if the
topographical variations are more than 0.4 micron) then we cannot transfer the image from
the mask to the wafer successfully. The topography of the wafer has to be reduced by some
method before it is sent to lithography.

Hope you understand. However, I will post a video on this for better understanding.

26
26
 PRODUCTION ISSUES
Key parameters:
resolution
alignment (or misalignment)
depth of focus
Partial and full field

27

Now will discuss the field issues.

27
 PARTIAL FIELD AND FULL FIELD

Why not large mask?

Limited by the lens size
28

Small mask – low

throughput

The last topic that is important in manufacturing is the issue of partial field. Normally, a mask will not have only one chip. One chip may be of 3
mm x 5 mm size, but a mask can be much larger. Then one mask will have multiple copies of a chip. The large box is the mask. The smaller boxes
represent the chips. The gaps between the chips, and the border areas are used for keeping alignment marks. During the lithographic process, one
exposure of this mask is called “field” or “shot”. The alignment marks are actually placed in the ‘gaps’ between the chips or at the corners of the
field.
Two questions arises right away. 1. “Why not make the mask very large and make hundred chips in it?” 2. “On the other hand, why not make a
small mask with only one chip?”
We cannot make the mask very large because the size of the lens is not unlimited. For very large lenses, the cost becomes very high. Beyond a
limit, we cannot make the lens very large even if money is not a constraint. Thus, the size of the mask is limited by the size of the lens that we can
make.
It is possible to make a small mask containing only one chip. However, one has to remember that in the lithographic process, the printing is done
step by step. i.e. the mask is brought on top of wafer, aligned to one spot and light is switched on for a controlled time. Then the mask is moved
on to the next part, aligned, exposed and so on. So, it is a time consuming process. During production, through put, (i.e. the number of chips
produced per hour, or number of wafers processed per week) has to be high. The lithography equipment are very expensive, of the order of Rs. 5
crores (in 2010), and one cannot afford to buy too many of these equipment. Hence, it is necessary to maximize the utilization and minimize the
time spent per wafer in these expensive machines. In one exposure or “shot”, if many chips can be made, then the total time will be saved. We
also know that we cannot make a very large mask because of limitations on the size of lens. So, one makes the mask of the maximum acceptable
size based on lens limitations, and within that, fit as many chips as possible. In this example, it is nine chips.
With this background, we will look into the issue of partial field. The wafer is a circular piece, but a mask is a rectangular piece. It is obvious that in
most exposures, all the nine chips square can be fitted into the wafer very nicely, but near the wafer edge, some of the chips will fall outside the
wafer. These exposures are called “partial fields”.
In the figure convenience, different colors are used to show the full field and partial fields separately.
What is the problem with partial field? First, when we align the mask to the previous layer, we use the alignment marks, which will be on all four
corners of the mask (field). In partial field, only one or two corners will fall within the wafer and the rest will be outside the wafer. There is no
“previous layer” outside the wafer and hence the alignment has to be done with only one or two marks, which makes it difficult. Second, the
focusing is done automatically by the equipment for all exposures. In full field, all the image will fall on the wafer while in partial field, part of the
image falls outside the wafer. This makes it difficult for the equipment to focus and this leads to poor image quality.
Just because partial field is problematic, one can not leave these areas empty. It is a useful wafer area. Also, we saw that presence or absence of a
line will affect lithography process and that it can be corrected using OPC. Similarly, the presence or absence of patterns will affect neighboring
areas. i.e. If partial field areas are left as blank, it will affect the neighboring full field also during the subsequent process. Thus it is better to
expose these areas also so that these areas will have at least some images even if they are not perfect images. The alignment and focusing
algorithm used by the machine can be modified to control the partial field shots better. One can also optimize the position to some extent, but
beyond that not much can be done. There will always be some area which falls in the partial fields. One should be aware of this when they
estimate the yields for the production of a particular chip. The details of yield will be discussed in the later chapter.

28
 4. Deposition

Last chapter. We discussed photolithography technique in which patterns in the mask

will be transferred to the wafer. We discussed about various types of lithography, its
pros and limitations, steps involved in lithography technique and its details, figures of
merit, production issues.

We have seen in chapter 2, during FEOL and BEOL fabrication processes, deposition of
metals and insulators at the specific locations of the wafer is involved. So how to
deposit them? What are the techniques available? What are the advantages and
limitations of each deposition technique? We will discuss it in this chapter 4.

1
 Overview
 Need of deposition and Requirements
 Types of deposition
 Physical vapor deposition (PVD)
 Chemical vapor deposition (CVD)
 Electrochemical Deposition (ECD)
 Spin on coating

The overview of this chapter is given in the slide.

See the slide for various deposition techniques available.

2
 Thin film Deposition
 A material like copper, tungsten needs to be deposited on
Si in IC fabrication industries
 Done by many techniques (PVD, CVD, ECD..)
 Requirements
 Uniform throughout the wafer
 Good control is necessary
 Side wall coverage
 Void free fill
 Well adhesion
 No dust particles should fall on wafer
 Crystal structure of the film deposited must be sufficient
quality
 For alloys, composition must be uniform

As we seen in chapter 2( during BEOL process), deposition of certain materials is one of the
steps in IC fabrication industries.

So, how we are depositing these materials?

By various techniques which we will be focusing on this chapter.

What are our basic requirements during this step?

1. Deposition has be to uniform throughout the wafer. Ex thickness of the material at the
center of the wafer is 5 micron, it has to be the same at the edge of the wafer too.
Usually center –edge thickness variation will be there if we are not optimizing the
process parameters.
2. Good control – suppose if we want to deposit 5 micron/min, it has to be
3. If we have trenches, steps, then the side wall coverage has to be good.
4. Aspect ratio really affects the deposition process. So we have to ensure that the
deposition is void free
5. Adhesion of deposited material on the given substrate. The material should not be peel
off from the substrate.
6. During the deposition process, unwanted particles should not form and deposited on the
wafer.
7. The crystal structure of the film being deposited should be sufficient quality. Because the
film quality strongly influences the chip performance. For example, Cu must have higher
grain size
8. If we are depositing alloy, composition has to be uniform throughout the wafer.

So we must ensure that the above requirements are meet during the deposition process.

3
 Materials to be deposited
❑ PVD: Ti/TiN, Ta/TaN, Cu-seed, Al
❑CVD: W, Ti, Cu-seed
❑Electrochemical: Cu

❑Deposition by
❑ Evaporation (obsolete)
❑ Higher energy involved
❑ Deposition on other parts

Image credit: Advance Deposition Techniques for Thin Film and Coating
By Asim Jilani, Mohamed Shaaban Abdel-wahab and Ahmed Hosny Hammad; DOI: 10.5772/65702

In IC industries, lot of materials needs to be deposited. For ex

1. Ti/TiN – adhesion liners, barriers for metal to diffuse to dielectric

2. Ta/TaN – adhesion liners, barriers
3. Cu, Cu seed layer
4. Ti, W

All these materials are not deposited by the same technique. It will be understood in
the subsequent slides.

Initially, the materials are deposited by evaporation technique (oldest technique).

This technique is not currently used in IC industries. So I will be not discussing it in
detail. However, I will give a brief introduction about this process.

Here the material to be deposited should be heated above the boiling point and the
vapor will be deposited on the wafer (mentioned as substrate in the slide). Actually
the wafer is kept at low temperature, hence the vapor is cool down and form the
solid material. Few disadvantages associated with this technique.
Firstly, as the materials have high b.p, high energy is involved. Evaporation source
may be crucible heated with coil, electron beam melting (as shown in the slide), or
just tungsten filament coated with other materials.
Secondly, as the whole chamber is heated , deposition also occurs at other parts.
Thirdly, if we want to deposit alloy, the one which has low b.p will evaporate first and

4
then deposited. This is undesirable as the desired composition of the alloy could not
be reached.

As a result, evaporation is not employed now for depositing materials in IC industries.

However, it is used for specific applications in other industries.

4
 PVD and CVD
 CVD : Chemical reaction involved. Raw material is in
the gaseous form
 PVD: purely physical process. Raw material in solid
state but in the form of very small particles or atoms

As evaporation is not used in IC industries, we will be focusing on following

deposition techniques.
1. Physical vapor deposition (PVD)
2. Chemical vapor deposition (CVD)
3. Electrochemical deposition
4. Spin coating.

First, we will focus on PVD and CVD

The major difference b/w PVD and CVD is CVD : Chemical reactions involved. Raw
material is in the gaseous form
PVD: Purely physical process. Raw material in solid state but in the form of very small
particles or atoms

5
 PVD
 a.k. a sputtering
 Operating tempearute lower than evaporation
 Equipment: 4 ft in height and 4 ft in dia
 Material to be deposited (target): Disc of 1 inch
thickness and 5/6 inches dia.
 Electrical voltage (10000 V)

Let discuss PVD process first.

PVD is also known as sputtering.

The equipment dimension and Material to be deposited (also called as target)
dimensions are also given in the slide.
Operating temperature is lower than evaporation. So, it is not energy intensive
compared to that of evaporation. However, higher voltage is required.

6
  Vacuum pump
 Low pressure Ar gas
PVD process -ve
 Plasma created upon
high voltage
 Ar ions attracted
towards negative plate
and hit the Al with
Target Al
high force
 Al atoms comes out.
How many –
Sputtering yield
Plasma Region  Atoms come toward
the wafer and deposit
 But not all of them –
resputttering
 Sticking coefficient
To make more uniform
• Rotate the wafer
slowly
Vacuum pump • Heating the wafer
+ve

We will see the detailed process of PVD now

1. In the first step, the chamber has to be evacuated by vacuum pump.
2. Then, Ar gas has to be sent inside. The pressure has to be low. Why Ar and Why low pressure? We will see later
3. The gas is converted in to plasma upon applying high voltage. Plasma contains ions, atoms and electrons (no. of ions = no.
of electrons, so equi-potential). Here we have Ar+ ions, electrons.
4. Here, the backside of the wafer is connected to the positive terminal while the backside of material to be deposited
(target) is connected to the negative terminal.
5. As Argon are positively charged, it will move towards target which is connected to the negative terminal. Similarly
electrons are moving towards wafer side.
6. When Ar ions moving towards target material, it hits the target with high force and remove the surface atoms. The
removed surface atoms are fall on to the wafer and get deposited there.
Hope you got it. I will post a video on this.
Two parameters of interest
1. Sputtering yield – when Ar ions hits target, how many atoms comes out. It is defined by sputtering yield (No. of atoms
comes out when one Ar ion hits). The sputtering yield is influenced by many parameters: the energy with which Ar ion hits,
angle of incidence (impingement) of Ar ion on the target, the target material property (surface binding energy). If the
surface binding energy is high, then the sputtering yield will be low.
2. Sticking coefficient: After hitting, many surface atoms comes out and fall towards the wafer. But not all of them is going to
deposit on to the wafer. Some will bounce back, some will bounce the atoms that is deposited already. So fraction of
atoms that is deposited (out of atoms that is removed from the target) is given by sticking coefficient. If its 1, then all the
atoms are deposited. If its zero, then no atom is deposited
During PVD, we want both the values has to be higher.

What we have seen in the last slide is basic steps involved in PVD. Always, we could improve the process performance by few
techniques that includes
1. Rotate the wafer holder slowly
2. Heating the wafer
These techniques enhance the uniform deposition throughout the wafer (step coverage will be good).
The above techniques will increase the surface diffusion. For example, If more atoms are accumulated at the edges, then via
surface diffusion mechanism, atoms move to the other parts and thereby making the deposition uniform. Heating helps in
softening the deposited material and enhance the surface diffusion

7
 PVD
 Why argon?
 Tungsten (m. p : 3422 & b.p 5555)
 Energy intensive
 Alloys (low b.p evaporate early)
 Should not interact with target/wafer surface
 Ionizing helium/neon is more difficult.
 Also cheaper relatively

 Why low pressure?

 W, Ti, Ta. Cu, TaN, TiN

Already we have seen evaporation cannot be used if b.p of the material to be

deposited is higher (Tungsten b.p 5555) as it is energy intensive process. In
PVD, deposition occurs via bombardment of Ar ions with the target material, the
temperature employed is relatively lower.

Why Ar? Why not air?

We cannot use air. It may react with target and wafer which is undesirable. Ex:
Oxygen in air may oxidize the material. So we have to create inert atmosphere.
Buy why Ar? Why not other inert gas. Because ionization of Ar gas is relatively easy.
Also, it is cheaper.

Why we are using low pressure?

Low pressure (milli torr) is maintained by supplying controlled amount of Ar. The
reason is mean free path of the source atoms will be lower. It prevents
collision of atoms with background ions.

Various materials that can be deposited by PVD is given in the slide.

8
 Depositing insulators by PVD

So far what we have seen is DC sputtering. i.e. DC voltage is supplied for creating
plasma.

This is works mainly if the target is metal. Why not dielectric material like SiO2?

In the beginning, argon ions will come and hit the silicon dioxide and some of the
silicon dioxide will be removed from there and deposited on the wafer. But, the argon
will get stuck on the silicon dioxide. Since it is an insulator, the charge will not be
removed. The silicon dioxide will acquire a positive charge. The backside of the glass
will have negative charge, but there will not be any electrical conduction. Very soon,
the entire surface will be positively charged and argon ions, which are also positively
charged, cannot approach the glass. The argon ions will not be able to hit the target
and deposit the target material on the wafer. If we were using a metal, then the
positive charge will be neutralized because the metal will conduct the electron from
the backside to the plasma side. In order to deposit the insulator by PVD, electrons
must be supplied to the surface of the insulator on a regular basis. This is achieved by
using radio frequency (RF) AC voltage. This is sometimes called as RF sputtering.

See more details in the next slide. I will post a video on this.

(Ref: Prof. S. Ramanthan, IIT Madras)

9
 PVD- RF

10

How does the RF PVD function? The chamber, which uses RF sputtering, looks very similar to
the one with normal sputtering, but the voltage applied will be different in this case. This is
explained in the schematics shown in figure 3.7 and 3.8. If we take an AC voltage and add it
to a DC voltage, then we will get a combined voltage as shown in this figure. If we apply only
a pure AC voltage, then 50% of the time the wafer will be positive and 50% of the time the
target will be positive. But when we apply the combined DC plus AC voltage, the wafer will be
positive 75% of the time and the target will be negative for most of the time. For a short
time, the target will be positive and the wafer will be negative.
What is the use of this? What will happen when this RF AC voltage is applied along with the
DC? When the target is mostly negative, argon ions will come and hit it. Some of the
electrons will go and hit the wafer. The glass will be removed by the argon ion and they will
go and deposit on the wafer. For a short time, the electrode will be positive near the target;
that time the electrons in the plasma will be attracted to the target. They will hit the target.
The target has argon ions and the electrons will go and neutralize the argon ions, as shown in
Fig. 3.9. Hence, the target will become neutral. Essentially, the electrons are supplied to the
target surface from the plasma side and not from the electrical contact at the back.
Now will the argon ions go and hit the wafer in the same time? Because argon is much more
heavier than electron, and because the duration is very short, it will not hit the wafer that
much. Since the electrons are very light (low mass), they will not cause any damage and no
atom will be taken out because of the electrons.
We saw that argon ions will not hit the wafer because it’s for a shorter duration. Even if they
hit, they will hit with less force and few hits will occur. In the beginning, in fact, the wafer will
be made negative and the target will be made positive. Because of this, the argon will hit the
wafer a little, and remove some material and make it rough. This actually facilitates good
deposition of the material in the later stages. The initial roughening of the wafer will also
help in cleaning any of the contaminant deposited on the material before this process.
Now the AC has to be applied at a very high frequency. That is why it is called RF or radio
frequency. Now almost all of the sputtering equipment are RF sputtering equipment.

10
 PVD: Collimated Beam
-ve

Equivalent to long
Al throw
Shield Shield

Plasma Region

Controlled
supply of Ar

Vacuum pump +ve

11

There are some more advanced techniques in the PVD. One is called collimated PVD. Another
is called ionized metal plasma or IMP PVD.
During deposition, we want uniform deposition on the wafer. i.e. the deposited film thickness
must be the same at the centre of the wafer, at the edge of the wafer and anywhere in-
between.
If the target is very small compared to the wafer, it will look like a point source (will be
discussed in detail later in this chapter) for the deposited material. In that case, the wafer
centre will have higher deposition and the wafer edge will have lower deposition.
One way to improve this is to increase the target size. If the target is large, then the
deposition will be uniform. In that case, the target can be near the wafer and still we can get
uniform deposition.
On the other hand, we can pull the target away. If it is too far away, then most of the wafer
will be more or less at the same distance from the target and hence, the deposition will be
uniform. This is called “long throw”.
Additionally, the wafers can be rotated during the process as mentioned earlier, and this also
helps in obtaining uniform film thickness.
However if we increase the target distance, then the chamber will become very large and to
evacuate the chamber and operate, one will spend correspondingly high energy. The goal of
uniform deposition can be achieved by another method called collimated beam. The
schematic is shown in the figure
In this, a plate with holes is placed between the target and the wafers. The target atoms,
which are coming towards the wafer, will have to come in straight line. Only then they will
pass through the collimated plate. Otherwise, they will be stopped by the plate. This ensures

11
that all of them are coming at similar angle and the film deposited will be uniform.

11
 PVD: IMP
RF
Ti ions also present
Similar to
Ti collimated
Shield Shield

Ionizing Plasma Region Coils

For liners, IMP Ti is
Controlled very common
supply of Ar

Vacuum pump RF

12

The most advanced method to obtain uniform thickness is called ionized metal
plasma or IMP. A schematic of the IMP sputtering equipment is shown in figure. In
this, the metal clusters that are coming towards the wafers are ionized using ionizing
coils. Thus the titanium or aluminum metal atoms that are coming are ionized. They
become charged and they will be attracted towards the wafer. Hence, even if they
start at a different angle when they ejected out of the target, they will all move
vertically towards the wafer because of the attractive forces. Since they are all
coming at similar angles, the deposition will be uniform. The best quality of the film is
obtained when IMP sputtering is used.

12
 PVD: Comparison

Side
coverage

Bottom
coverage

13

Comparison of performance of various PVD techniques is given here (Refer LHS

figure). Here the performance is evaluated in terms of bottom coverage. The bottom
and side coverage is shown schematically in RHS figure. In ideal case, it will look like
this (i.e 100% coverage).

As you can see, comapared to standard PVD, collimated or long throw is better for
low aspect ratio structures. However, when the aspect ratio is higher, we have to go
for IMP PVD.

13
 Step Coverage
Geometric
shadowing

Self
shadowing

Low T and no heating Heated and rotated

14

We have seen various PVD techniques and its performance in the previous slide. In
the deposition technique, sidewall coverage is very important.

PVD is basically line of sight process. The flux is directional. i.e. if the incoming atoms
coming at particular angle, it will hit the substrate only at the particular locations of
the wafer as shown in the top LHS figure. It results in poor coverage . Also, due to
geometric shadowing (top LHS figure) and self shadowing (bottom LHS figure left
side), we will end up with poor side wall coverage.

Step coverage is improved by various techniques discussed previously like

1. Heating the wafer
2. Rotating the wafer holder.

The heating and rotating improve the side coverage via surface diffusion mechanism.

14
 Step Coverage

SC = 1 SC < 1

If the sticking coefficient is 1, then the step coverage will be poor as shown in
Fig a.

If the sticking coefficient is less than 1, then side wall coverage will be good

15

Sticking coefficient 1 represents that the atom strikes on the particular site, it adsorbs
there. Less than 1 condition represents that it will be reemitted and adsorbed (or
migrated) to somewhere else (including sidewalls).

Earlier, I mentioned that the higher value of sticking co-efficient is preferred.

However, in this contact, less than 1 is preferred.

15
 PVD (Point Vs planar source

Deposition uniformity on
Point source Planar source the wafer

16

Now we will focus on the difference b/w point source and planar source.

Actually the atoms are coming out from the target material and then move towards the
wafer. This is referred as emission flux
(F) from the source (here the source is target).

If the source is point like (top LHS figure), Flux leaving emission source is independent of
theta. It emits in all directions.
However, the deposition thickness is dependent on Φ which is the angle b/w receiving
surface (wafer) and F vector, and R
(distance b/w source and target).

If the source is planar-like (top middle figure), then emission flux is dependent on theta . It
emits mostly in upward direction.
Here, the deposition rate is dependent on both theta and Φ

If the wafer of length (-l to l) is kept above the point source, the deposition profile (thickness
vs. length) is given by the top RHS
figure. Usually the uniformity is better in point like source as flux is independent of theta.

Here I assumed the wafer is kept above the target material as in evaporation. In conventional
PVD, the target is kept above the
wafer. However, the deposition uniformity trend will be the same.

16
IN PVD, each small area of the target acts as a planar source. So if we make the target
length higher compared to wafer, then
uniformity will be better. So the superposition of all small planar sources gives better
uniformity as shown in bottom figure.

16
 PVD mechanisms
1. Direct sputtering
2. Emitted sputtering
3. Resputtering
4. Surface diffusion

17

1. Direct sputtering – sputtering of target atoms by Ar ions. Sputtering yield should

be high
2. Emitted sputtering – as seen in the slide no. 15 . The sputtered atoms after
striking on the wafer at particular site, re-emits and re-adsorbs on some other
site.This is occurred when sticking coefficient will be less than 1
3. Resputtering –shown in the figure.
4. Surface diffusion- diffsuion of atoms due to concentration difference b/w
different sites.For ex. At edges concentration may be high. However, to be noted
emitted sputtering results in better side wall coverage than surface diffusion

17
 4. Deposition (part 2)

In part 1, we discussed about various PVD techniques. In the PVD method, it is not
easy to deposit a material on the side walls. This is especially true if the depth is very
high and the opening is small. i.e. if the aspect ratio is very high, PVD cannot give a
good side wall coverage However, CVD can be used to get a good side wall coverage.

In this part, we will discuss about chemical vapour deposition (CVD)

1
 CVD
Reaction occurs on surface
nucleation occurs only on surface
similar to catalysis
Relatively higher pressure compared to PVD
lower mean free path
Anisotropic dep
better step coverage
conformal dep

CVD is just similar to catalytic reaction i.e. the reaction will occur only on the solid
surfaces i.e. heterogeneous reaction rate will be higher compared to that of
homogenous reaction rate. Lower concentration of precursors should be used to
maintain low mean free path and to avoid collision of reactant molecules in the open
space. i.e. we want the reaction to occur only on the wafer surface which is kept
inside the container. CVD can be conducted at atmospheric pressure or at low
vacuum conditions i.e. very high vacuum condition as in PVD process is not required.

Major advantages of CVD technique is

(1) Anisotrpic deposition –the deposition proceeds in one particular direction

(2) Better step coverage
(3) Conformal deposition - this will be discussed later in this chapter.

The detailed CVD process is given in the next slide.

2
 Operation: CVD/LPCVD

First the wafers are kept in the chamber and the chamber is evacuated. Then the
wafers will be heated to the desired temperature.

Next the gases are supplied and they react only on the surface of the wafer and
deposit the material. For example, let us assume that we want to deposit W on the
wafer. For this, a mixture of WF6, H2 and N2 (all in gaseous form) will be supplied to
the chamber at low pressure. The temperature of the wafer would be maintained
between 150 to 900oC.

In the CVD technology, the phrase “high temperature” refers to 800+ oC and low
temperature may refer to “> 400 oC”. Very low temperature may refer to room
temperature.

In most of the CVD tools, all the chamber walls will be maintained at relatively
lower temperature compared to the wafer (cold wall reactor). Only the wafers
would be heated. WF6 and H2 will react only at high temperature. Hence the reaction
will occur only on the wafer and not on the chamber walls. This type of CVD process
is called low pressure CVD or LPCVD. Using this method many materials such as W,
Ti, TiN, Cu, SiO2, Si3N4, Si etc can be deposited on wafer. The side wall coverage will
also be good.

Incase if the whole chamber is heated, it is referred as hot wall reactor. Cold wall
rector is mostly preferred.

3
The wafers are heated by either induction heating or radiation heating. For lower
temperatures, normal heaters may be used. For high temperatures, heating lamps are
used. The lamps enable us to start and stop the heating very quickly. This in turn
results in good control of the deposition process.

3
 CVD mechanism A
1 5
1. Transport of reactants to the wafer surface
2. Adsorption
3. Reaction and the solid product is formed 3
4. Desorption of gaseous byproduct 2 4
5. Transport of byproduct away from the surface

The five important steps involved in CVD mechanism is shown in the slide and the
schematics is given in RHS figures. Figure A shows what happens during CVD process
and Figure B shows what we achieved at the end of CVD process. Here blue and
green circle represent reactants molecules , red circle represents solid product (which
we want to deposit on wafer) and blue circle represents gaseous byproduct.

The steps involved are classified in to mass transfer limited steps or reaction limited
steps. i.e. at given process conditions which is predominating: mass transfer rate (or
diffusion rate of reactants and products) or reaction rate ( rate of a chemical
reaction)? As you know, the slowest step is the rate determining step of the overall
process.

When high temperatures are used, the reaction rate is very high and the rate of
diffusion of the reactants through the boundary later decides the film growth rate (as
shown in LHS of green line in the plot). On the other hand, when the temperatures
are lower, the mass transfer rate will decrease a bit, but the reaction rate will
decrease a lot, and the surface reaction rate will decide the film growth rate. A plot
of film growth rate vs inverse of temperature will appear as shown in the slide. Also,
at high temperatures, the degree of freedom is one (Pressure) i.e. temperature
variation in this regime will not cause any significant change in the deposition rate
and quality while at lower temperatures, we can vary both pressure and temperature
to control the deposition process.

4
Similarly, if the pressure is lowered, the diffusion rate of gaseous molecules will be
lowered. It reduces the unwanted reactions in the gaseous phase and the formation
of dust particles are likely to occur less. Also, all the molecules will approach the
substrate with low velocity , so the uniform deposition could be achieved. This is one
of the major reasons why LPCVD is preferred over APCVD (APCVD is discussed in next
slide)

4
 APCVD
❑ LPCVD is operated at low pressure and relatively low temperature
compared to APCVD. So it is reaction rate controlled. So we need to control
the temp precisely

❑ APCVD is operated at relatively high temp and is diffusion rate controlled.

So we need to control the gas flow rate precisely.

❑ Please note that controlling temp is more easy than controlling gas flow
rate

❑ Reactor design is based on whether it is reaction rate controlled or

diffusion rate controlled

There is also another CVD method run at normal pressure. It is called atmospheric
pressured CVD or AP-CVD. Here the temperature is relatively higher, in the range of
600 to 800 oC. In this method, a thick film (as the reaction rate is very high) can be
formed quickly. However, there is risk of generating many dust particles (as the
reaction may happen above the wafer surfaces and the products formed will fall on
the wafer) and the film quality will be poorer. This method is used only in a few select
cases where quality is not so important.

❑ LPCVD is operated at realtively low temp. So it is reaction rate controlled. So we

need to control the temp precisely

❑ APCVD is operated at relatively high temp and is diffusion rate controlled. So we

need to control the gas flow rate precisely.

❑ Please note that controlling temp is more easy than controlling gas flow rate. So
we prefer LPCVD for most of the cases.

❑ Reactor design is based on whether it is reaction rate controlled or diffusion rate

controlled (will discuss later in this chapter)

5
 LPCVD Vs APCVD
LPCVD APCVD
Gas phase reaction is likely to Reaction may occur in gas phase,
occur forming particles which fall on the
wafer
Low pressure ( a bit less than a Atmospheric pressure
torr)
Operating under reaction rate Operating under mass transfer
controlled regime controlled regime
Mostly used in IC industries Used only for specific cases where
quality of the material that
deposited is not so important
Uniform coating is achieved with As the velocity of the molecules
good step coverage due to low are higher, uniform coating is not
pressure achieved
6

The major differences b/w LPCVD and APCVD is summarized here:

6
 Reactions

Poly Si (LPCVD) : 600 °C

SiCl4 + 2 H 2  Si + 4 HCl

SiH 4  Si + 2 H 2
SiH 2Cl2  Si + 2 HCl

The chemical reactions involved in CVD process for different materials is given in next
few slides:

In this slides, chemical reactions involved for poly crystalline Si deposition is given.

The various precursors such as silicon tetra chloride, silane or dicholrosilane are used
as precursors for depositing silicon.
If the growth rate is very high (for silicon for example), then poly crystalline structure
forms. If it is low, we get single crystal structure.

The temperature is usually 600°C.

7
 LPCVD/Reactions
Silicon Nitride (300 or 700 C). Used for LOCOS

3SiH 4 + 4 NH 3  Si3 N 4 + 12 H 2
3SiH 2Cl2 + 4 NH 3  Si3 N 4 + 6 HCl + 6 H 2
Oxide (<500 C)

SiCl2 + 2 NO2 → SiO2 + 2 N 2 + HCl 900 C

SiH 4 + O2  SiO2 + 2 H 2 450 C;Quality issue

( C2 H 5O )4 Si + O3  SiO2 + Others 400+ C

Tetra Ethyl Oxy Silane
(TEOS)
8

The reactions for deposition of silicon nitride and silicon oxide is given here.
For silicon nitride deposition, I mentioned temperature could be either 300 or 700°C. in
LPCVD, the temp is 700°C. However, at times, we don’t want to conduct deposition at high
temperatures as it will degrade the other material properties. For example, if there are
dopants (Phosphorous/ Boron) present in Si, it will diffuse faster and moves to insulator
(SiO2). So in those cases, we have to conduct the same reactions at lower temperature in the
presence of plasma (Ar ions and electrons). We need higher energy to initiate the chemical
reactions. The energy could be provided in terms of heat (thermal energy) or via electrons.
i.e. electrons have very high energy in plasma conditions. This will aid the chemical reactions
to proceed without increasing the temperature. This type of CVD is called as PE-CVD (Plasma
enhanced CVD). Few disadvantages also associated with PE-CVD. For example, if you take the
first reaction in Silicon nitride deposition, the product we want is Si3N4. If you employ LPCVD,
we will get the stoichiometric compound. But under plasma conditions, lot of hydrogen will
be incorporated in silicon nitride, so we will get non-stoichiometric SiN compound.
In PECVD, high magnetic field can be applied to increase the density of plasma and improve
the deposited film quality. This process is called High Denisty Plasma CVD or HDP-CVD.
The nitride films would be called as LP nitride, PE-nitride or HDP-nitride depending on the
method used to deposit them.

Also, if you notice in the slide, the temperature is different for each reaction. The quality will
also differ with given precursor. So we have to choose the right precursor for given
application.

8
 LPCVD
W Dep
2WF6 + 3Si → 2W + 3SiF4
Substrate reduction ~300 C

WF6 + 3H 2 → W + HF
W-Silicide/ Ti Silicide

WF6 + 2SiH 4 → WSi2 + 6 HF + H 2

TiCl4 + 2SiH 4 → TiSi2 + 4 HCl + 2 H 2

2-Mar-22 9

Chemical reactions involved in W and W-silicide deposition is given here.

Tungsten can be deposited by the thermal decomposition of tungsten hexa fluoride

(which releases fluorine and that
Will react with silicon) or by reduction of WF6 by hydrogen.

Tantalum penta chloride can also be reduced by hydrogen (2 Ta Cl5 + 5 H2 → 2 Ta +

10 HCl).

Aluminum can be deposited by decomposition of Tri-iso butyl Al, but sputtering is

cheaper and gives good quality Al.

9
 LPCVD: Reactors
Horizontal tube reactor
Controlled temperature (and not necessarily uniform)

Gas IN Vacuum

2-Mar-22 10

So far, we discussed:

(1) Various CVD techniques: LPCVD, PECVD and APCVD

(2) Mass transfer and kinetic controlled regime
(3) Hot wall and cold wall reactor
(4) Chemical reactions involved in CVD process.

Now we will discuss about the equipment (reactors) used in CVD process.

We have seen, temperature is main controlling parameter in LPCVD process as it

conducted under kinetic controlled regime. So for this, horizontal tube reactor as
shown in the slide will be used.

Here wafers can be held very closely to each other. Because LPCVD is reaction rate
controlled. So gas flow rate and boundary layer thickness are not so critical. Here we
can control the temp of the chamber at different points separately.
The temperature need not to be uniform. Because when the reactants enters the
chambers from left side, there will be a depletion of reactants at right side. If the
concentration goes down, then growth rate decreases. So temp has to be high at
right side to main uniform growth rate for all the wafers. See the concentration,
temperature profile in the bottom figure.

10
 APCVD reactor Induction Heating

Inlet Outlet
Laminar Flow

11

For APCVD reactor, controlling gas flow rate and boundary layer thickness is
important . If the wafer is kept at horizontal chamber, the boundary layer thickness is
not same for all the wafers as shown in the slide. That’s why the wafer holder is not
horizontal. It is inclined to make the BL thickness uniform for all the wafers.

11
 Other designs
Vertical Reactor Barrel Reactor

Horizontal
Only few wafers per chamber
Vertical (pancake)
few wafers per chamber, but no depletion
Barrel Reactors
more capacity 12

In horizontal reactor, we have seen depletion of reactants at the other end of the
reactor (right end of the reactor) is possible. To avoid this depletion, vertical reactor
could be used. But here also, we could accommodate only limited number of wafers
will be used. So to increase the batch size, other designs such as barrel reactor are
introduced.

Wafers can be rotated to enhance the uniform deposition as shown in the slide.

Images credit: Prajwal Shankar et al, Linkoping university.

12
 Disadvantages of CVD
❑High corrosive and toxic gases
❑Formation of dust particles
❑High temp –chip fail

How to overcome high temp? PECVD

13

❑Many of the gases used in CVD and highly corrosive and toxic. Hence good safety
measures need to be taken. Also, the cost of the high purity chemicals is also high.
❑If the temperature and pressure are not controlled well, the reaction will occur in
air itself and form tungsten (or whatever we are trying to deposit). These tungsten
will appear like a dust and will fall on wafer. This dust particle will not stick well to the
wafer and will degrade the deposited film quality.
❑The temperature cannot be raised arbitrarily during chip manufacturing. This is
because a transistor is made with impurities doped in particular location. When the
silicon wafer is heated, the dopants will move and the transistor will not function
properly
❑We have seen already how to overcome temperature issues i.e. by plasma
conditions

13
 Other CVD techniques
❑MO-CVD
❑PE-CVD
❑MBE

14

Of late, organic gases containing metal atoms or ions are used in CVD. These are called metal-
organic or MO-CVD. Based on a process that is similar to CVD, it is possible to create films of
certain materials with exactly one atom thickness! This is called atomic layer deposition
(ALD).
Atomic Layer Deposition: ALD can be thought of as a CVD technique with precise flow
control. Consider a reaction between water vapor and trimethyl aluminum (TMA) to produce
alumina (Al2O3) layer. The overall reaction is
If both reactants are supplied to the chamber containing wafer, alumina layer will form on
the wafer, but the thickness will not be easy to control. However, in ALD, first only water
vapor is sent to the chamber. A monolayer of water will chemisorb onto the wafer. Then the
chamber is evacuated and all the water vapor present, except the adsorbed molecules, will
be removed. Next, a pulse of TMA is introduced in the chamber. Now, the TMA will react
with limited water molecules present on the wafer and produce exactly one layer of alumina.
The chamber is evacuated again and the water vapor and TMA are sent in sequence to grow
the exact number of alumina layers required. At present, ALD is used for growing gate oxides
in the advanced chips. Instead of SiO2, other materials such as HfO2 (hafnium oxide) are used
as gate oxide in these chips and ALD offers the control necessary to deposit thin layers.
Molecular beam epitaxy: Another technique in research stage is called molecular beam
epitaxy (MBE). This is done in very high vacuum (10-8 Pa). The material to be deposited is
heated and the molecules (or atoms) will evaporate. The wafer is kept at a lower
temperature. Due to the high vacuum, the molecules will have a long mean free path and will
not interact with one another. They will deposit on the wafer and due to the slow growth
rate, it is possible to get single crystal growth using MBE. The main disadvantage of MBE is
that it is a very slow process and hence is not yet suitable for implementation in
semiconductor industry.
Copper deposited by PVD or CVD method has slightly higher resistance than the film
deposited using electrochemical methods. Hence electrochemical deposition (ECD) is used
for coating the wafer with copper.
Epitaxy means single crystalline material

14
 Electrodeposition (ECD)

15

Copper is used as interconnect material in the ICs. Copper can be deposited by PVD or CVD.
However, the copper deposited by ECD has a lower resistivity and a better fill characteristic.
The basic principle of electrochemical deposition is very simple. Two metal plates should be
connected to the positive and negative end by wires. In a glass beaker, some water and
copper sulfate should be taken. If the metal plates are dipped inside the solution, without
touching each other and then the connected to the batteries, then copper will deposit onto
the metal connected to the negative terminal (cathode) and oxygen will evolve from the
metal connected to the positive terminal. In this system, the metal connected to the negative
terminal is called cathode and the metal connected to the positive terminal is called anode.
Using the same principle, gold or silver is also coated on inexpensive ornaments.

We have to remember that silicon is a semiconductor and the wafer must be made
conductive for electrochemical deposition. Therefore, a thin layer of copper is deposited on
the wafer using PVD or CVD first. This is called seed layer. Then the wafer is kept in a tank
containing copper sulfate solution. The negative terminal of a voltage controlling system is
connected to the wafer while the positive terminal will be connected to a copper block.
When copper is deposited on the wafer, the copper content of the solution will decrease. If
we use copper block as anode, then copper will dissolve from it and the solution will have a
uniform and constant copper content. By controlling the temperature of the bath and the
voltage applied, the thickness of the copper deposited can be controlled.
Apart from copper sulfate, a few other chemicals are usually added to the bath. This enables
the deposited film to have good quality, without voids.
Certain large organic chemicals, called macromolecules, are added to the bath to obtain a
leveled surface. These molecules tend to adsorb on the surface and suppress the deposition
rates. They are more likely to adsorb on the flat surface and less likely to adsorb inside
trenches and holes. Thus, they reduce the deposition rate on the top surface, but do not
affect the deposition rate inside the trench and holes significantly. These are called
suppressors or levelers. Certain chemicals called accelerators are also added to the

15
electrochemical bath. They improve the deposition rate. They compete with
suppressors in adsorbing to the surface and tend to adsorb more inside the trenches
and holes. They also lead to less surface roughness and more uniform grain size of
the deposit. They are sometimes called as brighteners. The addition of suppressor
and brighteners in appropriate concentration makes the ‘bottom up’ fill possible in
electrochemical deposition of copper. Note that the mechanism of action of
suppressors and brighteners are not always supported by experimental evidence and
in many cases remain as hypothesis. However since they result in good quality film,
they are used commercially.

15
 Other possible electrochemical reactions
At the cathode
Electrode position of copper Cu2+ + 2e- → Cu
Hydrogen evolution 2H + 2e- → H2
+

At the anode
Soluble anode
Dissolution of copper Cu − 2e- → Cu2+
Insoluble anode
Oxygen evolution H2O − 2e- → 2H+ + 0.5 O2

Overall reaction
Cu2+ + H2O → Cu + 2H+ + 0.5 O2

The various electrochemical reaction occurred is given in the slide

At the cathode side, we have reduction reactions (i.e. addition of electrons). We have
copper ions reduction and hydrogen ions reduction reaction

At the anode side, we have oxidation reaction (i.e. the removal of electrons): Cu
oxidation and H20 reduction.

As we want primarily Cu oxidation and Cu+ reduction, we have to control the

potential (Voltage) supplied to the electrodes.

The overall reaction is given in the slide.

16
 Electrochemical Deposition
Usually < 50% of max current
max current at mass transfer limited region
operation at tafel region (reaction limited region)
uniform voltage distribution is necessary (seed layer)
convection is key

DC or wave form
pulsed
can etch ‘sharp’ regions
(more planarity)
need sophisticated control
acidic pH (sulfate, pyrophosphate
etc)
basic pH (cyanide and other
solutions)
2-Mar-22 17

I will explain this plot through video.

17
 Types of Fill: Schematic

2-Mar-22 18

When we are depositing material in the given trench, it fill in various manner as
shown in figure (1) anti-conformal (2) conformal and (3) super filling.

Among these, we prefer super filling as it produces void free and seam free structure.
We have to control the process conditions in such as way so as to achieve this defect
free structure.

18
 Types of Fill: SEM
© casewestern univ

2-Mar-22 19

The SEM image of various filling (explained in the previous slide) is given here.

19
 Spin Coating
Similar to photo resist coating
used for organic / mix of organic+inorganic ILD
DVD, CD...
mainly used for low-k materials
low temperature
better flow characteristic / self planarizing
adhesion

2-Mar-22 20

Spin coating, I have already explained in chapter-3 when we are discussing

photoresist coating.

In summary, we have seen PVD, CVD, WCD and Spin coating

Spin coating – photoresist

ECD –mainly for Cu interconnects
PVD and CVD – widely used for many materials deposition but CVD is preferred when
good sidewall and bottom coverage is required.

20
After photolithography step, we will remove the developed photoresist in the developing solutio
Besides, after deposition process, we have to remove the material which is deposited in excess. H

1
 Index
Overview
Wet etch/Dry etch
Etch characteristics / requirements
Wet etch:
Oxide, Nitride, Silicon and Al
Cleaning
Summary

3/2/2022 2

This is the overview of the chapter.

2
 Background
One of the material removal techniques
Either in liquid or gaseous phase (Wet etch or Dry etch)
gas ==> plasma etch

A “lot” of 200 mm
wafers in a ‘cassette”
Teflon
©IBM web site

3/2/2022 3

Etching is one of the removal techniques. This could be classified as wet etch and dry etch based

In this figure, I am showing that a batch of wafers are kept in Teflon cassette (holder). As harsh c

3
 Wet Etch Unit: Sample Image
Wet etch
unit
©IBM
web site
Note:
Clean room
floor
“Bunny
suite”

3/2/2022 4

The Teflon cassette will be then fed in to etching chamber. This is marked by red circle in the sli

4
 Sample Image
Wet Deck. Arizona State University

semi-automatic

3/2/2022 5

The image shown in the previous slide is fully automated one. This is typically used in fabricatio

5
 Background
Etching: usually after Photo

Needs to be selective
To photoresist
To hard mask
To the bottom material (in most cases)
Isotropic vs Anisotropic

Blind Etch vs “Stop on” etch

Planarization Etch

should handle high Aspect Ratio

clean
cost
3/2/2022 6

As said earlier, the etching process is commonly performed after lithography step.

Two figures of merit in etching process

1. selectivity: The etchant should react only with the layer that to be removed not with any oth
2. Isotropic/anisotropic: If the etching proceeds in all the directions, it is said to be isotropic .

Usually, wet etching provides good selectivity but isotropic while in dry etching it is vice-versa

Blind etch: etching will not stop at any other layer. We are controlling only the time to control t
Stop on etch: Etch will stop at other layer. Suppose if we want to remove only copper but not th
If we are performing etch to correct the non-uniformities of the given surface, then it is referred

Other requirements of etching process are given in the slide.

6
 Wet vs Dry etch

Wet chemical etch: Usually isotropic

In some single crystals, chemical etch occurs in only
one direction ==> Anisotropic
Dry etch:
Plasma : Ion impact mechanical removal, gas reaction,
chemical removal
Can be anisotropic or isotropic. Controllable

(111)
Direction –
no etching
7

We use liquid chemicals for wet etching. We choose the chemical in such a way that it will react

However, we don’t acheive anisotropic etching. Because, as we know that chemicals would not

In dry etching, we could control it as per our needs. We will discuss dry etching a little later. No
Please note wet etching is purely chemical – selectivity is higher

7
 Requirements

Uniformity:
Macro scale: across the wafer uniformity, plasma
confinement, wet etch chemical replenishment
Micro Scale:
Micro loading or etch loading
Mass transfer/ Boundary layer controlled vs
kinetics controlled
process proximity correction

3/2/2022 8

Before discussing wet etching, we will see, what are our requirements during etching process?

Uniformity on the macroscale: Uniformity has to be there throughout the wafer. It could be achi

In a macroscale: Usually in etching process, loading effect refers to the following: if we put 1 w

But in a microscale, it represents the aerial density difference at different places of the wafer. In

8
 SiO2
Si3N4
Si Wet Etch
Al
Resist
Silicon Oxide, Silicon Nitride
Silicon
Aluminum, Chromium
Photoresist (develop)

Silicon Oxide:
HF
Buffered HF (Buffered Oxide Etch or BOE)
NH4F + HF
BHF+Glycerin to protect aluminum
HF+HCl (increases etch rate)
Temperature as controlling3/2/2022
element 9

Now we will discuss wet etching in detail.

Here, in this slide, chemical reactions involved in SiO2 etching is given here.

HF is widely used to etch Si and SiO2. The basic requirement here is the etchant product should

To have more controlled etch rate, buffered HF is used.

If we add HCl, etch rate increases.

To increase the selectivity b/w SiO2 and Al, glycerin is used.

Usually in wet chamber, temperature, time is controlled to control the etch rate.

9
 SiO2
Si3N4
Si Wet Etch
Al
Resist
Etch rates in
um/min
Etch rate strongly
depends on type of
oxide:
Thermal oxide
has low etch rate
BSG has low
etch rate
PSG, CVD
oxide high etch
rate
3/2/2022 10

BSG-Boro silicate glass – glass doped with Boron; glass is basically SiO2
PSG – phospho silicate glass – glass doped with phosphorus.

Etch rate is not same for all types of SiO2. it is different. Also. In the plot, you could see the tem

10
 SiO2
Si3N4
Si Wet Etch Steps
Al
Resist
Soak (etch) in tank
controlled temp, composition, time
double rinse (usually DI)
counter current
spin dry

3/2/2022 11

Even after taking wafers out from the wet chamber, some of the reactant chemicals are present o

Immediate washing of wafers and drying should be performed after wet etching.

So, the three major steps in wet etching are

(1) Immerse the wafers in the wet etch chamber – etching step. Here we are mainly controlling t
(2) Taking out the wafers from the etch chamber and rinse it with de-ionized water. The rinsing
In the cascade rinse, water is flowing from left (DI water in) to right (drain) while wafers are mo
(3) , Then the rinsed wafers should kept in spin dryer for drying. Here wafers are allowed to spin

11