In the name of Allah, the Most Gracious the Most Merciful

EE-214: Electronic Circuit Design 1

 COURSE CODE AND TITLE
EE-214: ELECTRONIC CIRCUIT DESIGN

EE-214: Electronic Circuit Design 2

Course Objective
 This course covers the fundamental knowledge of
electronic circuits including FETs, FETs Amplifiers and
Switching Circuits, Multistage Amplifiers, Amplifiers
Frequency Response, Basic Operational Amplifiers
Circuits, Special purpose Operational Amplifiers Circuits,
Active Filters, Oscillators, Feedback Oscillator and
Relaxation Oscillator Circuits.

EE-214: Electronic Circuit Design 3

Course PLOs
 PLO-1: Engineering Knowledge: An ability to apply knowledge of
mathematics, science, engineering fundamentals and an engineering
specialization to the solution of complex engineering problems.

 PLO-2: Problem Analysis: An ability to identify, formulate, research

literature, and analyze complex engineering problems reaching
substantiated conclusions using first principles of mathematics,
natural sciences and engineering sciences.

 PLO-3: Design/Development of Solutions: An ability to design

solutions for complex engineering problems and design systems,
components or processes that meet specified needs with appropriate
consideration for public health and safety, cultural, societal, and
environmental considerations.

EE-214: Electronic Circuit Design 4

Course CLOs
 CLO-1. Understand and Explain the concepts of FETs, FETs
Amplifiers and Switching Circuits, Amplifier Frequency Response,
Operational Amplifiers, Basic Operational Amplifier Circuits, Active
Filters and Oscillators.

 CLO-2. Solve problems of different electronic circuits related to FETs,

FETs Amplifiers and Switching Circuits, Amplifier Frequency
Response, Operational Amplifiers, Basic Operational Amplifier
Circuits, Active Filters and Oscillators.

 CLO-3. Design various electronics circuits including FETs, FETs

Amplifiers and Switching Circuits, Amplifier Frequency Response,
Operational Amplifiers, Basic Operational Amplifier Circuits, Active
Filters and Oscillators.

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Mapping to CLOs and PLOs
Course Learning Program Learning
Learning Domain
Outcome Outcome

CLO-1 PLO-1 Cognitive 2

CLO-2 PLO-2 Cognitive 3

CLO-3 PLO-3 Cognitive 6

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Course Outlines
 FIELD EFFECT TRANSISTORS
 JFET, JFET Characteristics and Parameters, JFET Biasing, Ohmic region,
MOSFET characteristics and parameters, MOSFET Biasing, IGBT.

 FET AMPLIFIER AND SWITCHING CIRCUITS

 Common-Source Amplifier, Common-Drain Amplifier, Common-Gate
Amplifier, Class D Amplifier, MOSFET Analog and Digital Switching.

 AMPLIFIER FREQUENCY RESPONSE

 Basic Concepts, The Decibel, Low frequency amplifier response, High
frequency amplifier response, Total amplifier frequency response,
Frequency response of multistage amplifiers.

 THE OPERATIONAL AMPLIFIER

 Introduction to operational amplifiers, Op-Amp input modes and parameters,
Negative feedback, Op-Amp with negative feedback, Effects of negative
feedback on Op-amp impedances, Bias current and offset voltage, Open-
loop and frequency response, Close-loop frequency response.

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Course Outlines
 BASIC OP-AMP CIRCUITS
 Comparators, Summing Amplifiers, Integrators and Differentiators Circuits.

 SPECIAL PURPOSE OP-AMP CIRCUITS

 Instrumentation Amplifiers, Isolation Amplifiers, Operational
Transconductance Amplifiers (OTAs), Log and Antilog Amplifiers.

 ACTIVE FILTERS
 Basic filter responses, Filter response characteristics, Active low-pass filters,
Active high-pass filters, Active band-pass filters, Active band-stop filters.

 OSCILLATORS
 The Oscillators, Feedback oscillators, Oscillators with RC and LC feedback
circuits, Relaxation Oscillators.

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Recommended Books
1. Electronic Devices by Floyd, latest Edition, Prentice hall

2. Principles of Electronic Devices and Circuits by Malvino, Latest

Edition.

3. Electronic Devices and Circuits: Conventional Flow Version, Pearson/

Prentice Hall by Michael Hassul and Donald E Zimmerman, Latest

Edition.

4. Electronic Devices & Circuits by Boylested, Nashelsky,9th Edition

5. Microelectronic Circuits by Sedra. A.S, Smith. K.C

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Grading Policy
Weightages

Quizzes : 10%
Assignments : 10%
Project : 10%
Mid Exam : 25%
Final Exam : 45%

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Grade Bench Mark
 The point is learning, which requires effort.

 There are no shortcuts here!

 Every time you seek to find a shortcut in learning, what you are
actually doing is cheating yourself out of a valuable experience.

Grade: D
Lecture Notes
Learner
Information Input
Source
Class
EE-214: Electronic Circuit Design 11
Grade Bench Mark
First: Never ever limit yourself to a single source of information. Use
multiple sources

Information source Grade: C

ask an expert
Learner
Information source
read a book

Information source
read another book

Information source
Internet search
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Grade Bench Mark
Secondly: Your use of information sources must fully effective. Approach
each of your sources with specific questions in mind with the goal of
finding answers to those questions

Information source Query

ask an expert Grade: B-
Information source Query
Learner
read a book

Information source
read another book

Query
Information source
Internet search
EE-214: Electronic Circuit Design
Query 13
Grade Bench Mark
Thirdly: Apply what you collect from your sources. Don't just let that
information lie idle in your brain – put it into immediate action. This is
where you begin to construct your own understanding

Grade: B+
Application
Write in your own words

Application
Describe what you learn

Application
output
Teach your friend

Application
Build something

Application
EE-214: Electronic Circuit Design Practice, practice, practice
 Grade Bench Mark
Lastly: Establishes a feedback loop, enabling the learner to self-correct
errors in understanding

Grade: A- or A 15
 Attendance and Expectations
Attendance in class is Mandatory
Class Etiquette:

(1) Don’t read other inappropriate materials in the class

(2) Don’t talk to anyone other than the instructor

(3) Don’t arrive late or leave early

(4) Don’t do work unrelated to this class

(5) Don’t sleep in class

(6) Don’t let cell phones ring

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 Lecture No. 01
Chapter No. 08
Field Effect Transistors (FETs)

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Wednesday, February 16, 2022
Chapter Outline
• Introduction to JFET

• JFET Characteristics and Parameters

• JFET biasing

• Introduction to MOSFET

• MOSFETs Characteristics and Parameters

• MOSFET Biasing

• Introduction to IGBT

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FIELD EFFECT TRANSISTORS (FETS)
• FETs are unipolar devices because, unlike BJTs that use both electron
and hole current, they operate only with one type of charge 2carrier.

• The term field-effect relates to the depletion region formed in the

channel of a FET as a result of a voltage applied on one of its terminals
(gate).

• Recall that a BJT is a current-controlled device; that is, the base current
(IB) controls the amount of collector current (IC).

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FIELD EFFECT TRANSISTORS (FETS)
• A FET is a voltage-controlled device, where the voltage between two
of the terminals (gate and source) controls the current through the
device.

• A major advantage of FETs is their very high input resistance.

•c 2012 Pearson Education. Upper Saddle River, NJ, 07458.
•All rights reserved.
•Electronic Devices, 9th edition

• Due to the nonlinear characteristics of FETs, they are generally not as

widely used in amplifiers as BJTs except where very high input
impedances are required.

• FETs are the preferred devices in low-voltage switching applications

because they are generally faster than BJTs when turned on and off.

• IGBTs are generally used in high-voltage switching applications.

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TYPES OF FIELD EFFECT TRANSISTORS(FETS)
n-Channel JFET
JFET
p-Channel JFET
FET

MOSFET (IGFET)

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET

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JUNCTION FIELD EFFECT TRANSISTOR (JFET)

• The JFET (junction field-effect transistor) is a type of FET that operates

with a reverse-biased pn junction to control current in a channel.

• Depending on their structure, JFETs fall into either of two categories:

 n-channel

 p-channel

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BASIC STRUCTURE

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BASIC OPERATION
• VDD provides a drain-to-source voltage
and supplies current from drain to source.

• VGG sets the reverse-bias voltage

between the gate and the source.

• The JFET is always operated with the

gate-source pn junction reverse-biased.

•Reverse-biasing of the gate-source junction with a negative gate voltage

produces a depletion region along the pn junction, which extends into the
n channel and thus increases its resistance by restricting the channel width.

Rchannel = ρ L / A = L / σ A

•The channel width and thus the channel resistance can be controlled by varying
the gate voltage, thereby controlling the amount of drain current, ID.

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EFFECTS OF VGS ON CHANNEL WIDTH,RESISTANCE AND DRAIN
CURRENT (VGS = VGG)

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JFET SYMBOLS

•Notice that the arrow on the gate points “in” for n-channel and “out” for
p channel.

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JFET CHARACTERISTCS AND PARAMETERS
There are three regions in the characteristic curve for a JFET as shown
for the case when VGS = 0V.

•Between A and B is the Ohmic region,

where current and voltage are related
by Ohm’s law.

•From B to C is the active region

(or constant-current) where current is
essentially independent of VDS.

•Beyond C is the breakdown region.

Operation here can damage the FET.

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JFET CHARACTERISTCS AND PARAMETERS
• Consider the case when the gate-to-source voltage is zero (VGS=0V).

• This is produced by shorting the gate to the source, where both are grounded.

Consider the curve between points A and B:

• As VDD (and thus VDS) is increased from 0V, ID will increase proportionally.

• In this area, the channel resistance is essentially constant because the depletion
region is not large enough to have significant effect.

• This is called the ohmic region because VDS and ID are related by Ohm’s law.

Consider point B on the curve:

• The curve levels off and enters the active region where ID becomes essentially
constant.

Consider the curve between points B and C:

• As VDS increases from point B to point C, the reverse-bias voltage from gate to drain
(VGD) produces a depletion region large enough to offset the increase in VDS, thus
keeping ID relatively constant.

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JFET CHARACTERISTCS AND PARAMETERS

EE-214: Electronic Circuit Design 29

JFET CHARACTERISTCS AND PARAMETERS
Pinch-Off Voltage
•For VGS=0V, the value of VDS at which ID becomes essentially constant (point B
on the curve) is the pinch-off voltage, VP.

For a given JFET, VP has a fixed value.

•A continued increase in VDS above the pinch-off voltage produces an almost

constant ID. This value of drain current is IDSS (Drain to Source current with gate
Shorted).

•IDSS is the maximum drain current that a specific JFET can produce regardless
of the external circuit, and it is always specified for the condition VGS=0V.

Breakdown
Consider point C on the curve:
•Breakdown occurs when ID begins to increase very rapidly with any further
increase in VDS.

• Breakdown can result in irreversible damage to the device.

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PINCH-OFF OCCURS AT A LOW VDS AS VGS INCREASES TO MORE
NEGATIVE VALUES

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VGS CONTROL ID

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JFET AT BREAK DOWN (CUTOFF)

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Example# 8.1

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Solution

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Example# 8.2

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Solution

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JFET TRANSFER CHARACTERISTIC CURVE (n-channel)

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JFET TRANSFER CHARACTERISTIC CURVE GENERATED FROM
DRAIN CHARACTERISTIC CURVE (n-channel)

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Example# 8.3

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Solution

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JFET FORWARD TRANSCONDUCTANCE
•The forward transconductance (transfer conductance), gm, is the change in drain
current (ΔID) for a given change in gate-to-source voltage (ΔVGS) with the drain-to-
source voltage constant. It is expressed as a ratio and has the unit of siemens (S).

•Other common designations for this

parameter are gfs and yfs (forward transfer
admittance).

•gm is an important factor in determining the

voltage gain of a FET amplifier.

•A datasheet normally gives the value of gm

measured at VGS = 0 V (gmo).

An approximate value for gm at any point

on the transfer characteristic curve can be
calculated by using the following formula:

EE-214: Electronic Circuit Design 42

JFET FORWARD TRANSCONDUCTANCE
• Datasheet for the 2N5457 JFET specifies a minimum gmo (gfs) of (the mho is the
same unit as the siemens (S)) with VDS = 15 V.

• An approximate value for gm at any point on the transfer characteristic curve can be
calculated by using the following formula:

When a value of gmo is not available, calculate it using values of IDSS and VGS(off ).
The vertical lines indicate an absolute value (no sign).

EE-214: Electronic Circuit Design 43

Example# 8.4

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Solution

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INPUT RESISTANCE AND CAPACITANCE
•JFET operates with its gate-source junction reverse-biased, which makes the input
resistance at the gate very high.

•High input resistance is one advantage of the JFET over the BJT.

•JFET datasheets often specify the input resistance by giving a value for the gate
reverse current, IGSS, at a certain gate-to-source voltage.

•The input capacitance, Ciss, is a result of the JFET operating with a reverse-biased
pn junction.

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Example# 8.5

Solution

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AC DRAIN-TO-SOURCE RESISTANCE
• From the drain characteristic curve that, above pinch-off, the drain current is
relatively constant over a range of drain-to-source voltages.

• A large change in VDS produces only a very small change in ID.

• The ratio of these changes is the ac drain-to-source resistance of the device

• Datasheets often specify this parameter in terms of the output conductance, gos,
or output admittance, yos, for VGS = 0 V.

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