ALLIANCE COLLEGE OF ENGINEERING AND DESIGN CORE

Chikkahagade Cross
Chandapura - Anekal Main Road, Anekal
Bangalore – 562106

CS 404: Computer Organization and Architecture (Credits 3:0:0)

Total Hours: 45 No. of hrs. /week: 3

Internal Marks: 50 External Marks: 50

Pre-requisites: Computer Basic Knowledge

INSTRUCTOR Prof. R. SELVARANI
Office: Office 24
Phone No:080-4619 9179
E-mail id: [email protected]
OFFICE 10AM to 4:00PM Monday to Friday
HOURS
This course provides comprehensive overview of computer architecture with
COURSE
OVERVIEW: specific emphasis on design of reduced instruction set computers.
Knowledge on modern computer system design, hardware support for
operating system functions, architectures of scalar pipelined processor,
superscalar processor, multi-threaded processor and multi-core processor,
and programming models for multi-threaded and multi-core processors are
included.

1. Students will understand the internal hardware design of a computer system and
COURSE
OBJECTIVES: analyze their operation with application program
2. Students will understand complete execution of software instruction and create
machine code instructions with a deep knowledge in binary number system.
3. Knowledge on Data hazards, Instruction hazards and effective hardware and
software implementation for instruction execution including exception handling will
be inculcated
4. Knowledge on various types of memory involved in computer system design and
effective management of memory system in instruction execution will be the
primary focus
5. Knowledge on associative I/O devices and interfaces for better management of these
peripherals during the creation of application program.

Core Learning Outcomes

Sl Learning Outcomes Assessment Criteria
No On completion of this unit you To achieve the learning outcome, you must
. should be able to: demonstrate the ability in describing the
1 1. Basic Structure of Computer
system: Functional units – Basic
operational concepts – Bus structures
– Performance and metrics –
Knowledge on the internal hardware design of a computer
Instructions and instruction
system which supports instruction execution (s/w
sequencing – Hardware – Software
program)
Interface – Instruction set architecture
– Addressing modes – RISC – CISC.
ALU design – Fixed point and
floating-point operations.
2 Fundamental concepts – Execution of
a complete instruction – Multiple bus
organization – Hardwired control – Knowledge on complete internals of computer system design
Micro programmed control – Nano
programming.
3 Basic concepts – Data hazards –
Instruction hazards – Influence on
Knowledge on computer architecture of a multi-processor
instruction sets – Data path and
system - Ex: Intel Quad Core Processor
control considerations – Performance
considerations – Exception handling.
4 Basic concepts – Semiconductor
RAM – ROM – Speed – Size and cost
– Cache memories – Improving cache Knowledge on computer memory management system &
performance – Virtual memory –
techniques.
Memory management requirements –
Associative memories – Secondary
storage devices.
5 Accessing I/O devices – Programmed
Input/Output -Interrupts – Direct
Memory Access – Buses – Interface Knowledge on computer peripheral devices architecture and
circuits – Standard I/O Interfaces interfaces
(PCI, SCSI, USB), I/O devices and
processors.
Approach to Learning - The teaching methods will consist of formal lectures, solving
numerals at various capacity and performance index, observational
study on design aspects of computer hardware system
- Classroom teaching along with the practical exposure to present
day system used every day
- Problem solving skills are improved by providing the application-
level problems in reference to memory speed and heat dissipation
for effective management of cost and time in the present scenario
- Problem analysis on performance indices of multi-processor
system
In real time
Assessment Strategy - The During Semester Exam (DSA) and Semester End Exam (SEE)
 are conducted to test the first four level of Bloom’s taxonomy.
- Open book test will be conducted to check the knowledge on
design and architecture of system operation.
- Regular assignments will be provided on innovative topics either
self-designed or proposed topics to understand the operational
intricacies of computer system
Course Outcomes Assessed Submission
SL Assessmen Description Weight
day/week
No. t method of
(assignments)
assessment
or length
method
(exam)
CO1 CO2 CO3 CO4 CO5 CO6
1 MSA Mid √ 50 marks (90
Semester 20 √ √ √ √ √ mins)
Assessment
2 CP Class √ Throughout the
Participation 5 √ √ √ √ √ course
3 AS Throughout the
Assignment 10 √ √ √ course
4 OT Mini project Throughout the
with course
presentation 10
5 AT Attendance 05 Throughout the
course
6 SEE Semester 100 marks (3
End- 50 √ √ √ √ √ Hours)
Examination

L1: Remembering L2: Understanding L3: Applying

L4: Analyzing L5: Evaluating L6: Creating
Hours /
level / Topics to be covered Class Exercise
Cos
1-9 Module1: BASIC STRUCTURE OF COMPUTERS Classroom teaching and
/ Functional units – Basic operational concepts – Bus structures –
discussion on the hard-core
L3 Performance and metrics – Instructions and instruction sequencing
internals of a computer
/ –Instruction set architecture – Addressing modes – RISC – CISC.system. Low level analysis on
CO2 ALU design – Fixed point and floating-point operations. their performance at various
architectures like RISC and
CISC etc.
10-17 Module 2: FUNDAMENTAL CONCEPTS – Execution of a Classroom teaching on
/ complete instruction – Multiple bus organization – Hardwired computer operation in view of
L3 control – Micro programmed control an instruction execution.
/
CO3
18-28 Module 3: PIPELINING Classroom teaching and
 / Basic concepts – Data hazards – Instruction hazards – Influence on discussion on data &
L2 instruction sets – Data path and control considerations – Instruction hazards to better
/ Performance considerations –Exception handling. understanding of memory
CO4 handling during their
programming for various
applications. Knowledge on
exceptions associated in
instruction execution and
avoidance techniques.
29-37 Module 4: MEMORY SYSTEM Classroom teaching and
/ Basic concepts – Semiconductor RAM – ROM – Speed – Size and discussion on various
L4 cost – Cache memories – Improving cache performance – Virtual computer memories
/ memory – Memory management requirements – Associative supporting for its operation.
CO5 memories – Secondary storage devices. Its hardware and working
principle with interfacing
techniques are the interest to
cover in this module
38-45 Module 5: I/O ORGANISATION Knowledge on Input /output
/ Accessing I/O devices – Programmed Input/Output -Interrupts – devices and their interfacing
L4 Direct Memory Access – Buses – Interface circuits – Standard I/O techniques are inculcated by
/ Interfaces (PCI, SCSI, USB), I/O devices and processors. completing this module to the
CO5 students.
RECOMMENDED READINGS:
Essential Readings:
1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth
Edition, Tata McGraw Hill, 2002.
Additional Readings:
1. David A. Patterson and John L. Hennessy, “Computer Organization and Design: The
Hardware/Software interface”, Third Edition, Elsevier, 2005.

2. William Stallings, “Computer Organization and Architecture – Designing for

Performance”, Sixth Edition, Pearson Education,

Useful YouTube lectures on internet:

• NPTEL video lectures
1. NPTEL video lecture on Computer Organization and Architecture (IIT
Madras, IIT Kharagpur)
2. NPTEL web materials on COA (IISc Bangalore)

PROGRAM OUTCOMES (Pos):

PO 1: Engineering Knowledge PO 2: Problem Analysis PO 3: Design/development of
solutions
PO 4: Conduct investigations of PO 5: Modern tool usage PO 6 : The engineer and society
complex problems
PO 7: Environment and PO 8: Ethics PO 9: Individual and teamwork
sustainability
 PO 10: Communication PO 11: Project management PO 12: Life-long learning
and finance

COURSE OUTCOMES (Cos):

At the end of this course students will
1. Gain knowledge in computer hardware internals and analyze on various higher end processor
operation
2. Gain fundamental knowledge on instruction execution at micro programmed level. Students will
be able to Design their own programming instruction for a given problem
3. Gain Knowledge on multiprocessor architecture and associated data and instruction hazards.
4. Gain knowledge on various memory systems associated with computer operation and analyze
their performance index.
5. Gain knowledge on various I/O devices, Interfacing techniques and Analyze data transfer
techniques.

COs MAPPING WITH POs:

Course Code: CS404 Course Title: Computer Organization and Architecture

Course Cos PO PO PO PO PO PO PO PO PO PO PO PO
code.Cours 1 2 3 4 5 6 7 8 9 10 11 12
e number
C404.1 CO1 3 3 3 3 - - - - - - - -
C404.2 CO2 3 3 3 3 - - - - - - - -
C404.3 CO3 3 3 2 2 - - - - - - -
C404.4 CO4 3 3 3 3 - - - - - - - -
C404.5 CO5 3 3 3 3 - -2 - - - - - -
C404.6 CO6 3 3 3 3 - 2 - 2 2 2 2 2
Average 3 2 2.83 2.83 - 2 - 2 2 2 2 2

Enter correlation levels 1, 2 or 3 as:

 1: Slight (Low)
 2: Moderate (Medium)
 3: Substantial (High)
 If there is no correlation, then put “-“
 Signature of the Course Instructor

ASSESSMENT RUBRICS

CP Criteria
Grade Exemplary Proficient Partially Need Points
proficient improvement scored
Point 5 4 3 2
Level of Student Student Student Student
engagemen listens and listens and listens and listens but
t in class proactively proactively contributes to never
contributes contributes class by contributes
to class by to class by sharing ideas to class by
sharing sharing ideas or clearing sharing ideas
ideas or or clearing doubts rarely or clearing
clearing doubts at doubts
doubts least once in
many every session
times in
every
session
Preparation Student is Student is Student is Student is
always usually rarely partially
prepared prepared prepared with prepared
with given with given given reading with given
reading reading materials and reading
materials materials and completed materials
and completed home works and
completed home works completed
home home works
works
OT
Problem Actively Improves Does not Does not try
Solving seeks and solutions come up with to solve
suggests based on solutions but problems or
solutions suggestions tries out help others
to by peer solutions to solve
problems suggested by problems
others
Teamwork All team Assisted Finished Contributed
members group/partner individual little to the
contributed in the task but did group effort
equally to finished not assist during the
the project. group/partner project.
finished during the
 project. project

.
AS Detailed Detailed Explanation Missed key
response response unclear, but points and
given with given but response the response
no errors final answer shows some is not
wrong understandin aligned to
g of the problem
problem

ASSIGNMENT 1:
 Topic: Design Instruction set for a given problem
 Start Date: TBD
 Submission deadline: TBD
 Return date:
ASSIGNMENT 2:
 Topic: Design an execution demo model for a given application

Start Date: TBD

 Submission deadline: TBD
 Return date:

ASSIGNMENT 3:
 Topic: Explain a multiprocessor architecture with design diagram
 Start Date: TBD
 Submission deadline: TBD
 Return date:

ASSIGNMENT 4:
 Topic: Design memory requirement for a given architecture
 Start Date: TBD
 Submission deadline: TBD
 Return date:
ASSIGNMENT 5:
 Topic: solve given situation in data transfer with DMA
 Start Date: TBD
 Submission deadline: TBD
 Return date: