PD Flow I - Floorplan
PD Flow I - Floorplan
Floorplan
PD Flow I – Floorplan
Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is ofte
and Route) / APR (Automatic Place & Route). Main steps in physical design are placement of all logical cells, clock tree synthe
process of physical design timing, power, design & technology constraints have to be met. Further design might require bein
power and performance.
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Import design is the first step in Physical Design. In this stage all required inputs & required references are read into the tool. A
done (design, technology consistency).
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Inputs required
1. Gate level netlist
2. Logical (Timing) & Physical views of standard cells & all other IPs used in the design
3. Timing constraints (SDC)
4. Power Intent (UPF / CPF)
5. FP DEF & Scan DEF
6. Technology file
7. RC Co-efficient files
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Why it is required?
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ICC/Innovus optimizes critical timing paths (violating paths) which are seen by it. There can be chances that PnR tool is show
timing QoR (huge violations) compared to Post Syn QoR seen in PT/Tempus. It can be because of correlation issue / constrai
unnecessary optimization; timing & design closure will be easy if we correlate Import Design timing QoR with Post Syn timing
2. FLOORPLAN
Floorplan is one the critical & important step in Physical design. Quality of your Chip / Design implementation depends on ho
good floorplan can be make implementation process (place, cts, route & timing closure) cake walk. On similar lines a bad flo
issues in the design (congestion, timing, noise, ir, routing issues). A bad floorplan will blow up the area, power & affects reliab
can increase overall IC cost (more effort to closure, more LVTs/ULVTs)
Before staring of Floorplan, it is better to have basic design understanding, data flow of the design, integration guidelines of a
in the design. And for block/partition level designs understanding the placement & IO interactions of the block in Full chip will
good floorplan.
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FLOORPLAN STEPS
1. Size & shape of the block (Usually provided by FC floorplan)
2. Voltage area creation (Power domains)
3. IO placement
4. Creating standard cell rows
5. Macro-placement
6. Adding routing & placement blockages (as required)
7. Adding power switches (Daisy chain)
8. Creating Power Mesh
9. Adding physical cells (Well taps, End Caps etc)
10. Placing & qualifying pushdown cells
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Detailed discussion
1. Abutted voltage area (Cells are not allowed to place in default voltage area)
As is no default domain area, voltage area feed-through (VA-FT) are required to cross over different voltage area
2. Non-abutted voltage area (Cells are allowed to place in default voltage area)
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3. IO / Pin placement
IOs / Pins are placed at the boundary of the block. Usually pin placement information is pushed down from FC floorplan. But t
changed based on block critical requirements. Any change in pin location has to be discussed with FC floorplan team. Timin
special attention, like next 2-3 levels of logic from IOs are pre-placed near the IOs). Source synchronous interfaces requires d
into considerations (This will require manual placement & scripting)
4. Row creation
Rows area created in the design using cell-site (unit / basic). Rows aid in systematic placement of standard cells. And stand
considering rows.
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Rows can be cut, wherever cell placement is not allowed OR hard placement blockage can also be used.
5. Macro placement
Step 1 – Understand Pins & Orientation requirements of Macros
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Step 2 – Follow data flow / hierarchy to place the Macros. Make use of reference floorplan if available
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Step 3 – All the pins of the Macros should point towards the core logic
Step 4 – Channels b/w macros should be big enough to accommodate all routing reqs & should get a minimum of one pair
the channel
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3. Spacing b/w macros should be enough for routing & power grid
4. Macros should not block partition
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5. [Iterations] Less congestion & good timing QoR – These cannot be achieved in one shot, but need few iterations [Thorou
the key things while iterating]
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Power switches are inserted in power mesh & supply to all gated domain cells will be through power switches. Hence a single
enough. A strong network of power switches connected in daisy chain fashion will be inserted in the design.
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8. Adding special cells (Well Taps, EndCaps, Spare Cells, Metal ECO-able cells etc)
Well connection – Almost all standard cell libraries are tap-less (substrate connections are not done @ cell level). So Well-ta
partition/chip level to tie the wells to VDD/VSS. Tap-gate spacing has to be met while adding well-tap array.
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EndCap Cells – These cells are inserted to take care of boundary DRC of Wells & Other layers. End Cap Cells ensure proper te
no DRC are created. This is a physical-only cell.
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