Department of Cse CP7103 Multicore Architecture UNIT - 1, Fundamentals of Quantitative Design and Analysis 100% THEORY Question Bank
Department of Cse CP7103 Multicore Architecture UNIT - 1, Fundamentals of Quantitative Design and Analysis 100% THEORY Question Bank
DEPARTMENT OF CSE
CP7103 Multicore Architecture
UNIT – 1, Fundamentals of Quantitative Design and Analysis
100% THEORY
QUESTION BANK
30. Give the various categories of instruction operators with example for each?
31. Commend the operation for media and signal processing?
32. What are the different type of control flow instructions?
33. Give the major methods of evaluating branch condition, their advantages and disadvantages
34. Explain instruction coding and its type?
35. What are the various compiler optimization available ?
36. What is the difference between DLP and TLP? Nov 2012
37. Compare MIPS and TM 32 processor
38. What is a vector processor?
39. What is Flynn’s taxonomy ?
40. Explain the various methods by which data level parallelism is obtained?
41. Compare RISC and CISC machines.
42. Differentiate von Neumann and hardware architecture.
43. What is pipelining?
44. What are the basic of RISC instruction set architecture?
45. What are the different stages of pipelined architecture?
46. Briefly describe basic performance issues in pipelining?
47. What are hazards? Mention its types?
48. How data hazards can be minimized?
49. What are structural hazards? how it can be minimized?
50. What are control hazards?
51. How is pipelining implemented?
52. What makes pipelining hard to implement?
53. What is latency? Nov 2012
54. What is reservation table?
55. What are forbidden and permissible latencies ? give example
56. What are contact cycle?
57. What is collision vector?
58. Explain pipeline throughput and efficiency
59. How do you compute pipeline CPI?
60. What is a basic block? May 2012
61. What is ILP?
62. What are forwarding and bypassing techniques?
63. What is loop-level parallelism ?
64. What are the various dependences? How to overcome it?
65. How to avoid hazards?
66. What are the different name dependences ? Nov 2012
67. What is a control dependence?
68. What is a data dependence?
69. What is dynamic scheduling? Compare dynamic scheduling with static pipeline scheduling?
70. Differentiate in-order and out-of-order execution of instruction?
71. What is imprecise exception?
72. Explain Tomasulo’s algorithm briefly?
73. Explain WAR hazards?
74. Explain WAW hazards?
75. Explain RAW hazards?
76. What is a reservation station ? mention its fields? Nov 2010
77. Give the merits of Tomasulo’s algorithm?
78. How to remove control dependences?
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